Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208564
Joao P. Alarcao, L. Oliveira, J. Oliveira, Rui Santos-Tavares
Noise canceling techniques have been successfully applied to the design of modern multi-band RF-CMOS inductor-less receivers. However, low voltage supply requirements are imposing new design challenges which are pushing the operation of the MOS transistor into moderate or weak inversion, making the setup of closed sizing expressions a difficult task. This paper presents a Si2 OpenAccess based circuit analysis tool that can combines a symbolic equation extractor with the transistor parameters obtained from precise models, reinforcing the performance estimation while reducing the design time. The tool is applied for a wide-band Low Noise Amplifier (LNA). The results are validated by comparing them with values obtained from SpectreRF eletrical simulations using a 130 nm CMOS technology.
{"title":"Analysis of a noise canceling LNA using a Si2 OpenAccess based tool — CADIT","authors":"Joao P. Alarcao, L. Oliveira, J. Oliveira, Rui Santos-Tavares","doi":"10.1109/MIXDES.2015.7208564","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208564","url":null,"abstract":"Noise canceling techniques have been successfully applied to the design of modern multi-band RF-CMOS inductor-less receivers. However, low voltage supply requirements are imposing new design challenges which are pushing the operation of the MOS transistor into moderate or weak inversion, making the setup of closed sizing expressions a difficult task. This paper presents a Si2 OpenAccess based circuit analysis tool that can combines a symbolic equation extractor with the transistor parameters obtained from precise models, reinforcing the performance estimation while reducing the design time. The tool is applied for a wide-band Low Noise Amplifier (LNA). The results are validated by comparing them with values obtained from SpectreRF eletrical simulations using a 130 nm CMOS technology.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208586
T. Rudnicki, R. Czerwinski, D. Polok, A. Sikora
The paper presents performance analysis of a permanent magnet synchronous motor (PMSM) drive with torque and speed control. The PMSM motor requires sinusoidal stator currents to produce constant torque. The paper presents constituents for the mathematical analysis of the motor operation within the dq-axis model. The mathematical model serves as inspiration for development of a drive design based on the DSP processor and IGBT power module. The measurement system consists of a control unit equipped with an inverter and an encoder, the PMSM drive (500W; 5Nm; 800 rpm), a torque measuring device and a motor that work in the generator mode. The performance analysis has been performed in two control intervals. It is possible to operate the PMSM with the speed that exceeds the rated rpm if the permanent-magnet excitation is weakened by a demagnetising field component produced by the stator winding. However, it leads to a decrease of the motor efficiency. The conducted experiments have shown, that in the second control interval it is possible to increase the motor speed by about 30% as compared to the nominal rpm (overspeed).
{"title":"Performance analysis of a PMSM drive with torque and speed control","authors":"T. Rudnicki, R. Czerwinski, D. Polok, A. Sikora","doi":"10.1109/MIXDES.2015.7208586","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208586","url":null,"abstract":"The paper presents performance analysis of a permanent magnet synchronous motor (PMSM) drive with torque and speed control. The PMSM motor requires sinusoidal stator currents to produce constant torque. The paper presents constituents for the mathematical analysis of the motor operation within the dq-axis model. The mathematical model serves as inspiration for development of a drive design based on the DSP processor and IGBT power module. The measurement system consists of a control unit equipped with an inverter and an encoder, the PMSM drive (500W; 5Nm; 800 rpm), a torque measuring device and a motor that work in the generator mode. The performance analysis has been performed in two control intervals. It is possible to operate the PMSM with the speed that exceeds the rated rpm if the permanent-magnet excitation is weakened by a demagnetising field component produced by the stator winding. However, it leads to a decrease of the motor efficiency. The conducted experiments have shown, that in the second control interval it is possible to increase the motor speed by about 30% as compared to the nominal rpm (overspeed).","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116281629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208559
G. Simon, G. Farkas
Thermal characterization techniques require precise powering and accurate data acquisition equipment. The proper powering is complex due to electrical and thermal stability issues and some device properties. A few methods require trials to ensure the proper powering of the devices. New compound semiconductor devices have further stability issues at low currents and high voltages. This paper analyzes setups for powering two-pole and three-pole semiconductor devices with great emphasis on the stability issues. Methods are presented which ensure stability and proper powering on the devices, such as programmed powering technique, which eliminates oscillations as well.
{"title":"Stability criteria of the thermal characterization of discrete components","authors":"G. Simon, G. Farkas","doi":"10.1109/MIXDES.2015.7208559","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208559","url":null,"abstract":"Thermal characterization techniques require precise powering and accurate data acquisition equipment. The proper powering is complex due to electrical and thermal stability issues and some device properties. A few methods require trials to ensure the proper powering of the devices. New compound semiconductor devices have further stability issues at low currents and high voltages. This paper analyzes setups for powering two-pole and three-pole semiconductor devices with great emphasis on the stability issues. Methods are presented which ensure stability and proper powering on the devices, such as programmed powering technique, which eliminates oscillations as well.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116112386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208517
M. Ghasemzadeh, A. Soltani, Amin Akbari, K. Hadidi
In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. An optimized resistance ratio averaging scheme is applied to: (1) reduce the offset, nonlinearity, (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors. The proposed ADC is simulated by Hspice using 0.35 μm TSMC technology and shows 32.24 dB/45.9 dB SNDR/SFDR, 5.06 bits ENOB, and the low power consumption of 45.12 mW from a 3.3V supply.
在这项工作中，提出了一个6位800 MS/s闪存模数转换器(ADC)。采用一种优化的电阻比平均方案:(1)减少偏置、非线性;(2)提高精度和失配不灵敏度;(3)使元件尺寸最小化，使ADC的尺寸更紧凑、面积更小、速度更快。为了最大限度地发挥这些成就，最有利的是，它完全由NMOS晶体管构建。采用0.35 μm TSMC技术的Hspice对该ADC进行了仿真，显示出32.24 dB/45.9 dB SNDR/SFDR, 5.06位ENOB，在3.3V电源下的低功耗为45.12 mW。
{"title":"A 6-bit 800MS/s flash ADC in 0.35μm CMOS","authors":"M. Ghasemzadeh, A. Soltani, Amin Akbari, K. Hadidi","doi":"10.1109/MIXDES.2015.7208517","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208517","url":null,"abstract":"In this work, a 6-bit 800 MS/s flash analog-to-digital converter (ADC) is proposed. An optimized resistance ratio averaging scheme is applied to: (1) reduce the offset, nonlinearity, (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors. The proposed ADC is simulated by Hspice using 0.35 μm TSMC technology and shows 32.24 dB/45.9 dB SNDR/SFDR, 5.06 bits ENOB, and the low power consumption of 45.12 mW from a 3.3V supply.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"83 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116409461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208479
P. Badura, E. Pietka
This paper presents the study on the automatic computer-aided balance assessment system. The approach employs ambient assisted living architecture based on inertial sensors. The assessment relies on selected activities from the Berg Balance Scale test by means of the system supplied by a set of features extracted from the accelerometric signals. The feature space dimensionality reduction stage selects the feature vector for each activity and sensor combination using the Fisher's linear discriminant. The system is trained and evaluated using expert scoring of examinations involving 52 patients with different balance abilities. The investigation on the system performance with various sets of available sensors is presented and discussed.
{"title":"Inertial sensor location analysis in automatic balance assessment","authors":"P. Badura, E. Pietka","doi":"10.1109/MIXDES.2015.7208479","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208479","url":null,"abstract":"This paper presents the study on the automatic computer-aided balance assessment system. The approach employs ambient assisted living architecture based on inertial sensors. The assessment relies on selected activities from the Berg Balance Scale test by means of the system supplied by a set of features extracted from the accelerometric signals. The feature space dimensionality reduction stage selects the feature vector for each activity and sensor combination using the Fisher's linear discriminant. The system is trained and evaluated using expert scoring of examinations involving 52 patients with different balance abilities. The investigation on the system performance with various sets of available sensors is presented and discussed.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123500002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208495
Krzysztof Fornalczyk, P. Napieralski, D. Szajerman, A. Wojciechowski, Przemyslaw Sztoch, Jakub Wawrzyniak
Stereoscopic films and interactive presentations are extensively popularized whereas their perceived quality still dissatisfies viewers. The reasons are shared between hardware inconsistencies and stereo image producers unawareness concerning factors influencing depth perception quality. This paper reviews aspects influencing 3D image perception visual comfort, presents visual comfort estimation methods and suggests how to measure image perception quality.
{"title":"Stereoscopic image perception quality factors","authors":"Krzysztof Fornalczyk, P. Napieralski, D. Szajerman, A. Wojciechowski, Przemyslaw Sztoch, Jakub Wawrzyniak","doi":"10.1109/MIXDES.2015.7208495","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208495","url":null,"abstract":"Stereoscopic films and interactive presentations are extensively popularized whereas their perceived quality still dissatisfies viewers. The reasons are shared between hardware inconsistencies and stereo image producers unawareness concerning factors influencing depth perception quality. This paper reviews aspects influencing 3D image perception visual comfort, presents visual comfort estimation methods and suggests how to measure image perception quality.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122750635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208551
Lukasz Matoga, A. Koczor, M. Golek, Pawel Zadek, P. Penkala
The paper presents logic concepts of scalable architecture of a system for emulation purposes along with dedicated, underlying FPGA-based board modules as an implementation platform. These modules provide scalability of emulation system and support full system functionality. This article also presents an analysis of feasibility of the scalable system based on a hybrid-structure. The system consists of dedicated hardware modules and third-party, easy-to-get evaluation boards to provide a cheap solution with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, connectors etc. the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. The paper discusses the use of this system throughout the different emulation modes as well as explains problems common to modern logic gate arrays. The article presents performance achievements of the implemented communication channel to the host and discusses the architectural features affecting system construction and efficiency.
{"title":"Modular FPGA-based hardware platform for emulation","authors":"Lukasz Matoga, A. Koczor, M. Golek, Pawel Zadek, P. Penkala","doi":"10.1109/MIXDES.2015.7208551","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208551","url":null,"abstract":"The paper presents logic concepts of scalable architecture of a system for emulation purposes along with dedicated, underlying FPGA-based board modules as an implementation platform. These modules provide scalability of emulation system and support full system functionality. This article also presents an analysis of feasibility of the scalable system based on a hybrid-structure. The system consists of dedicated hardware modules and third-party, easy-to-get evaluation boards to provide a cheap solution with fast bring-up time for emulation purposes. By complying to many industry standards in the areas of communication interfaces, memory modules, connectors etc. the presented platform acts as a cost-effective, desktop-size solution and can be used in early stages of hardware-assisted verification process. The paper discusses the use of this system throughout the different emulation modes as well as explains problems common to modern logic gate arrays. The article presents performance achievements of the implemented communication channel to the host and discusses the architectural features affecting system construction and efficiency.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130664607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208498
D. Makowski
Rapid evolution of the high-performance digital cameras entailed a development of new gigabit interfaces for video streaming and further image processing. A 25 megapixel camera, shooting with 100 frames per second, can easily produce a stream of data reaching tens of gigabits per second. The situation is more complex in case of image processing systems that acquire video stream from many cameras. In this case the video data throughput could reach 100 Gbps. Image acquisition systems require a flexible interface that allows sending data with high throughput. The image stream is usually transmitted to a high performance CPU that collects video data and performs further image processing. The PCI Express (PCIe) bus is widely used in modern computers. The PCIe standard provides a scalable, low latency connection between a CPU and peripheral devices. The paper discusses the application of a PCIe interface in an image acquisition system based on MTCA.4 standard. The system uses an external CPU connected to a MTCA.4 chassis. The initial results of performance evaluation are presented and discussed.
{"title":"Application of PCI express interface in high-performance video systems","authors":"D. Makowski","doi":"10.1109/MIXDES.2015.7208498","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208498","url":null,"abstract":"Rapid evolution of the high-performance digital cameras entailed a development of new gigabit interfaces for video streaming and further image processing. A 25 megapixel camera, shooting with 100 frames per second, can easily produce a stream of data reaching tens of gigabits per second. The situation is more complex in case of image processing systems that acquire video stream from many cameras. In this case the video data throughput could reach 100 Gbps. Image acquisition systems require a flexible interface that allows sending data with high throughput. The image stream is usually transmitted to a high performance CPU that collects video data and performs further image processing. The PCI Express (PCIe) bus is widely used in modern computers. The PCIe standard provides a scalable, low latency connection between a CPU and peripheral devices. The paper discusses the application of a PCIe interface in an image acquisition system based on MTCA.4 standard. The system uses an external CPU connected to a MTCA.4 chassis. The initial results of performance evaluation are presented and discussed.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130847194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208568
C. Stefanucci, P. Buccella, M. Kayal, J. Sallese
High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach based on transistor layout is presented that is compatible with parasitic substrate noise propagation in Smart Power ICs. The results of the model are compared with TCAD simulations and show how the substrate network replaces the parasitic BJTs in HVCMOS compact models. Potential shift of the substrate is also analysed for different geometrical configurations showing the high flexibility of the proposed modeling approach.
{"title":"Modeling parasitic vertical PNP in HVCMOS","authors":"C. Stefanucci, P. Buccella, M. Kayal, J. Sallese","doi":"10.1109/MIXDES.2015.7208568","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208568","url":null,"abstract":"High voltage CMOS active devices inherently have a parasitic vertical bipolar transistor. The parasitic PNP structure can be activated during high-power switching operation causing a potential shift of the substrate. In this work a spice-modeling approach based on transistor layout is presented that is compatible with parasitic substrate noise propagation in Smart Power ICs. The results of the model are compared with TCAD simulations and show how the substrate network replaces the parasitic BJTs in HVCMOS compact models. Potential shift of the substrate is also analysed for different geometrical configurations showing the high flexibility of the proposed modeling approach.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126129318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208510
D. Tomaszewski, K. Domanski, P. Prokaryn
In the paper a simple compact model of a transfer of a mechanical energy into an electrical energy is presented. The mechanical energy is stored in a vibrating bimetallic membrane with an electret layer. The membrane vibrations are forced by a set-up consisting of a cold and hot surfaces. During the vibrations this set-up acts as a variable capacitor with one of the electrodes being constantly charged. The charge stored on the other plate of this capacitor varies periodically and is transferred to the external storage capacitor via a simple Graetz circuit. Acompact model of this mechanism has been derived and implemented in an open-source Quite Universal Circuit Simulator (Qucs) program as a circuit including a specific Equation-Defined Device component. The simulation data have been compared with experimental ones, demonstrating promising features of the proposed approach.
{"title":"Qucs-based development of an energy harvester compact model","authors":"D. Tomaszewski, K. Domanski, P. Prokaryn","doi":"10.1109/MIXDES.2015.7208510","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208510","url":null,"abstract":"In the paper a simple compact model of a transfer of a mechanical energy into an electrical energy is presented. The mechanical energy is stored in a vibrating bimetallic membrane with an electret layer. The membrane vibrations are forced by a set-up consisting of a cold and hot surfaces. During the vibrations this set-up acts as a variable capacitor with one of the electrodes being constantly charged. The charge stored on the other plate of this capacitor varies periodically and is transferred to the external storage capacitor via a simple Graetz circuit. Acompact model of this mechanism has been derived and implemented in an open-source Quite Universal Circuit Simulator (Qucs) program as a circuit including a specific Equation-Defined Device component. The simulation data have been compared with experimental ones, demonstrating promising features of the proposed approach.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132837981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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