Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208548
Bernhard Raab, M. Kaufmann, Andreas Rauchenecker, T. Ostermann
A practical way for the realisation of LC VCOs is presented. The design plan takes frequency and power constraints as input parameters, uses available inductor, varactor and transistor models for basic simulations and delivers a dimensioned circuit. Both, low phase noise and low power design fundamentals are respected, as well as NMOS-, PMOS- and CMOS transistor cores can be used. The design plan is verified with examples using two different processes. Simulation results of selected examples are provided at the end of this work.
{"title":"Robust and efficient design plan for integrated differential negative-Gm LC VCOs","authors":"Bernhard Raab, M. Kaufmann, Andreas Rauchenecker, T. Ostermann","doi":"10.1109/MIXDES.2015.7208548","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208548","url":null,"abstract":"A practical way for the realisation of LC VCOs is presented. The design plan takes frequency and power constraints as input parameters, uses available inductor, varactor and transistor models for basic simulations and delivers a dimensioned circuit. Both, low phase noise and low power design fundamentals are respected, as well as NMOS-, PMOS- and CMOS transistor cores can be used. The design plan is verified with examples using two different processes. Simulation results of selected examples are provided at the end of this work.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129309359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208497
A. Mielczarek, P. Perek, D. Makowski, A. Napieralski, Przemyslaw Sztoch
The paper presents a FPGA-based dedicated system for rapid calibration of 3D camera rigs. The developed device aims to help during camera set-up, by allowing the operator to easily compare the images from two cameras with use of several composition methods. The paper indicates the challenges related to development of high-throughput video processing systems in FPGA circuits. The processing methods were developed and verified using a platform with recent Kintex-7 FPGA device from Xilinx. The article covers the details of the implementation of the image analyser prototype. Moreover it identifies the crucial design considerations and addresses the problems that any FPGA designer can encounter during development of video processing systems.
{"title":"Calibration of stereoscopic camera rigs using dedicated real-time SDI video processor","authors":"A. Mielczarek, P. Perek, D. Makowski, A. Napieralski, Przemyslaw Sztoch","doi":"10.1109/MIXDES.2015.7208497","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208497","url":null,"abstract":"The paper presents a FPGA-based dedicated system for rapid calibration of 3D camera rigs. The developed device aims to help during camera set-up, by allowing the operator to easily compare the images from two cameras with use of several composition methods. The paper indicates the challenges related to development of high-throughput video processing systems in FPGA circuits. The processing methods were developed and verified using a platform with recent Kintex-7 FPGA device from Xilinx. The article covers the details of the implementation of the image analyser prototype. Moreover it identifies the crucial design considerations and addresses the problems that any FPGA designer can encounter during development of video processing systems.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117143551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208473
T. Szmuc, M. Szpyrka
The applicability of formal methods to support for software development is discussed in the paper. Software for realtime systems (esp. Safety Critical Systems) is of special interest. Petri nets, Alvis language and temporal logic are examined in which way they may support the development process. Selected approaches for using methods and related examples are discussed to answer the question stated in the title.
{"title":"Formal methods — Support or scientific decoration in software development?","authors":"T. Szmuc, M. Szpyrka","doi":"10.1109/MIXDES.2015.7208473","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208473","url":null,"abstract":"The applicability of formal methods to support for software development is discussed in the paper. Software for realtime systems (esp. Safety Critical Systems) is of special interest. Petri nets, Alvis language and temporal logic are examined in which way they may support the development process. Selected approaches for using methods and related examples are discussed to answer the question stated in the title.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114351428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208556
P. Zając, M. Galicia, C. Maj, A. Napieralski
3D stacking of integrated circuits is a promising idea for increasing the processor performance. However, the major challenge is overcoming thermal issues due to excessive power density. In this paper, using Intel's Haswell processor as an example, we analyze the thermal behavior of an eight-core processor implemented as a 2D chip and as a 3D architecture with two layers. We also investigate the use of localized thermal vias for improving the thermal behaviour of the 3D stack. We show that the peak temperature can be significantly reduced (by 5.8°C in our case) due to the implementation of thermal vias.
{"title":"Investigation of localized thermal vias for temperature reduction in 3D multicore processors","authors":"P. Zając, M. Galicia, C. Maj, A. Napieralski","doi":"10.1109/MIXDES.2015.7208556","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208556","url":null,"abstract":"3D stacking of integrated circuits is a promising idea for increasing the processor performance. However, the major challenge is overcoming thermal issues due to excessive power density. In this paper, using Intel's Haswell processor as an example, we analyze the thermal behavior of an eight-core processor implemented as a 2D chip and as a 3D architecture with two layers. We also investigate the use of localized thermal vias for improving the thermal behaviour of the 3D stack. We show that the peak temperature can be significantly reduced (by 5.8°C in our case) due to the implementation of thermal vias.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114520169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208484
T. Sondej, D. Tomaszewski, K. Rózanowski
The article presents the method for implementation and results of examination of the Pan-Tompkins algorithm using a specialized 4-core Azurite processor, based on MIPS-II instruction set. The algorithm is used to determine heart rate on the basis of ECG signals. Azurite is a Multiprocessor System-on-Chip featuring an analog and a digital part. The digital part has been implemented in a Xilinx Virtex-6 FPGA system. An experimental study was carried out using one and three cores of Azurite processor as well as using the widely available microprocessor of the STM32F4 series (based on Cortex-M4F core). Same results were obtained for both types of cores. Division of the Pan-Tompkins algorithms into stages processed in 3 processor cores allowed for a 2.5 speedup of computations. Processing of a 27-second fragment of the ECG signal (sampling frequency of 250 Hz) using three cores of the Azurite processor (processor clock frequency of 100 MHz) took as little as 6.9 ms.
{"title":"Implementation of an algorithm for heart rate measurement in a specialized multi-core processor","authors":"T. Sondej, D. Tomaszewski, K. Rózanowski","doi":"10.1109/MIXDES.2015.7208484","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208484","url":null,"abstract":"The article presents the method for implementation and results of examination of the Pan-Tompkins algorithm using a specialized 4-core Azurite processor, based on MIPS-II instruction set. The algorithm is used to determine heart rate on the basis of ECG signals. Azurite is a Multiprocessor System-on-Chip featuring an analog and a digital part. The digital part has been implemented in a Xilinx Virtex-6 FPGA system. An experimental study was carried out using one and three cores of Azurite processor as well as using the widely available microprocessor of the STM32F4 series (based on Cortex-M4F core). Same results were obtained for both types of cores. Division of the Pan-Tompkins algorithms into stages processed in 3 processor cores allowed for a 2.5 speedup of computations. Processing of a 27-second fragment of the ECG signal (sampling frequency of 250 Hz) using three cores of the Azurite processor (processor clock frequency of 100 MHz) took as little as 6.9 ms.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125766468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208531
M. Melnyk, A. Kernytskyy, M. Lobur, M. Szermer, P. Zając, C. Maj, W. Zabierowski
This paper presents an approach to facilitate the design of a microbolometer. It is based on three main steps: the construction of a simplified model in Matlab, automatic transfer of the generated model into ANSYS and the verification of the model using ANSYS FEM (Finite Element Method) simulation. The novel idea is the second step, realized using a special application, which reads the parameters from the simplified model and automatically creates a batch file for ANSYS with all appropriate material and geometry data as well as loads and simulation parameters.
本文提出了一种简化微测热计设计的方法。它主要基于三个步骤:在Matlab中构建简化模型，将生成的模型自动转换到ANSYS中，并使用ANSYS FEM (Finite Element Method)仿真对模型进行验证。第二步采用了一个特殊的应用程序，该程序从简化模型中读取参数，并自动为ANSYS创建一个批处理文件，其中包含所有适当的材料和几何数据以及载荷和仿真参数。
{"title":"Custom method for automation of microbolometer design and simulation","authors":"M. Melnyk, A. Kernytskyy, M. Lobur, M. Szermer, P. Zając, C. Maj, W. Zabierowski","doi":"10.1109/MIXDES.2015.7208531","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208531","url":null,"abstract":"This paper presents an approach to facilitate the design of a microbolometer. It is based on three main steps: the construction of a simplified model in Matlab, automatic transfer of the generated model into ANSYS and the verification of the model using ANSYS FEM (Finite Element Method) simulation. The novel idea is the second step, realized using a special application, which reads the parameters from the simplified model and automatically creates a batch file for ANSYS with all appropriate material and geometry data as well as loads and simulation parameters.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124914564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208514
D. Tomaszewski, J. Malesinska, G. Gluszko
Two simple non-iterative methods of MOSFET threshold voltage parameter extraction are presented. They are valid for threshold voltage-based and charge-based compact models of MOS transistors. The methods take advantage of the features of the model formulae and their derivatives. The methods have been illustrated using both real measurements and data obtained via simulation of simple circuits used for extraction of the pinch-off voltage of the MOSFET EKV model. The simulations have been done using an open-source program Qucs.
{"title":"Simple methods of threshold voltage parameter extraction for MOSFET models","authors":"D. Tomaszewski, J. Malesinska, G. Gluszko","doi":"10.1109/MIXDES.2015.7208514","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208514","url":null,"abstract":"Two simple non-iterative methods of MOSFET threshold voltage parameter extraction are presented. They are valid for threshold voltage-based and charge-based compact models of MOS transistors. The methods take advantage of the features of the model formulae and their derivatives. The methods have been illustrated using both real measurements and data obtained via simulation of simple circuits used for extraction of the pinch-off voltage of the MOSFET EKV model. The simulations have been done using an open-source program Qucs.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208481
B. Kubik, Zbyszek Szczurek, P. Kowalski, A. Michnik, Barbara Szuster
The article is aimed at presenting the organizational concept of the wireless personal area network (WPAN network) transmitting biomedical data, used in the BioSip system. The network transmits data from recording modules attached to various locations on the subject's body to a collective node (data integrator) while maintaining all the necessary properties, such as low power consumption of the modules, increased resistance of the network to artefacts, the required transmission speed and signal delays. WPAN networks are based on various communication protocols, such as ZigBee, Bluetooth, ANT. In BioSip, the network uses its own protocol based on transmission mechanisms of the systems made by Nordic.
{"title":"Organization of fast biomedical data transmission in a low-power, high-reliability wireless personal area network (WPAN) dedicated to data acquisition from BioSip modules","authors":"B. Kubik, Zbyszek Szczurek, P. Kowalski, A. Michnik, Barbara Szuster","doi":"10.1109/MIXDES.2015.7208481","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208481","url":null,"abstract":"The article is aimed at presenting the organizational concept of the wireless personal area network (WPAN network) transmitting biomedical data, used in the BioSip system. The network transmits data from recording modules attached to various locations on the subject's body to a collective node (data integrator) while maintaining all the necessary properties, such as low power consumption of the modules, increased resistance of the network to artefacts, the required transmission speed and signal delays. WPAN networks are based on various communication protocols, such as ZigBee, Bluetooth, ANT. In BioSip, the network uses its own protocol based on transmission mechanisms of the systems made by Nordic.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124658499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208577
T. Golonek
This paper proposes the evolutionary technique of the stimulus signal optimization for the analog electronic circuit testing purpose. The obtained signal is coded with Sigma-Delta modulation usage that allows to generate it easily by simple microcontrollers without the necessity of expensive D/A peripherals applying. The signal with the controlled impulses density may be obtained on the external output terminal of the typical timer and finally, it defines the analog signal that can be reconstructed after low pass filtering.
{"title":"Analog testing stimulus optimization for generating by means of Sigma-Delta modulation","authors":"T. Golonek","doi":"10.1109/MIXDES.2015.7208577","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208577","url":null,"abstract":"This paper proposes the evolutionary technique of the stimulus signal optimization for the analog electronic circuit testing purpose. The obtained signal is coded with Sigma-Delta modulation usage that allows to generate it easily by simple microcontrollers without the necessity of expensive D/A peripherals applying. The signal with the controlled impulses density may be obtained on the external output terminal of the typical timer and finally, it defines the analog signal that can be reconstructed after low pass filtering.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120960578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208505
Elise Rosati, M. Madec, J. Kammerer, A. Rezgui, C. Lallement, J. Haiech
We recently demonstrated that it is possible to model and to simulate biological functions using hardware description languages (and associated simulators) traditionally used for micro-electronics. The main drawback of these languages is that they do not support partial differential equations. However, for several applications in biology, space-dependent quantities are unavoidable. This paper deals with a new approach to address these problems. It is based on previous investigations on electro-thermal simulations in integrated circuits. The tool is composed of four main parts: a mesher that divides space into small cubes (or squares in 2D), a set of interconnected biological models, a SPICE simulator that handles these models and a Python script that interfaces the different tools. Simulation results obtained with our tool are compared with experimental data on a specific case. Results are in good accordance from a qualitative viewpoint.
{"title":"Verilog-A compact space-dependent model for biology","authors":"Elise Rosati, M. Madec, J. Kammerer, A. Rezgui, C. Lallement, J. Haiech","doi":"10.1109/MIXDES.2015.7208505","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208505","url":null,"abstract":"We recently demonstrated that it is possible to model and to simulate biological functions using hardware description languages (and associated simulators) traditionally used for micro-electronics. The main drawback of these languages is that they do not support partial differential equations. However, for several applications in biology, space-dependent quantities are unavoidable. This paper deals with a new approach to address these problems. It is based on previous investigations on electro-thermal simulations in integrated circuits. The tool is composed of four main parts: a mesher that divides space into small cubes (or squares in 2D), a set of interconnected biological models, a SPICE simulator that handles these models and a Python script that interfaces the different tools. Simulation results obtained with our tool are compared with experimental data on a specific case. Results are in good accordance from a qualitative viewpoint.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134560157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：