Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208582
J. D. Melo, Pedro V. Leitão, J. Goes, N. Paulino
This paper presents a class-D power amplifier for medium quality sound systems using a second-order passive sigma-delta modulator (ΣΔM). The ΣΔM controls an output power stage consisting of a H-bridge. The loop filter of the ΣΔM was designed using a optimization procedure based on genetic algorithm (GA), that takes into account several parameters. This system was implemented using discrete components and the experimental results show that a DR of 75 dB is achieved with a peak signal-to-noise-plus-distortion ratio (SNDR) of 54 dB.
{"title":"A simple class-D audio power amplifier using a passive CT ΣΔ modulator for medium quality sound systems","authors":"J. D. Melo, Pedro V. Leitão, J. Goes, N. Paulino","doi":"10.1109/MIXDES.2015.7208582","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208582","url":null,"abstract":"This paper presents a class-D power amplifier for medium quality sound systems using a second-order passive sigma-delta modulator (ΣΔM). The ΣΔM controls an output power stage consisting of a H-bridge. The loop filter of the ΣΔM was designed using a optimization procedure based on genetic algorithm (GA), that takes into account several parameters. This system was implemented using discrete components and the experimental results show that a DR of 75 dB is achieved with a peak signal-to-noise-plus-distortion ratio (SNDR) of 54 dB.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208482
Paula Lubina, M. Rudzki
This paper presents a study aimed to assess applicability of artificial neural networks (ANNs) in human activity recognition from simple features derived from accelerometric signals. Secondary goal was to select the most descriptive signal features and sensor locations to be used as inputs to ANNs. Five triaxial accelerometers were attached to human body in the following places: one at back, two at waist laterally and two at both ankles. The set of activities to be recognized was established to include the most often performed actions in home environment. In total 25 subjects performed a set of predefined actions like walking, going up and down the stairs, sitting down and standing up from a chair. Acquired signals were divided into 0.5s time windows by a label defining the action performed. Several statistical signal features were calculated and used to train ANNs. Learning and testing were performed on separate data sets. Analysis using Fisher Linear Discriminant showed that despite the fact that some of the calculated values play a significant role in the distinction between similar activities, none of the features or sensors could be omitted in the recognition of the activities considered in the study. Accuracy of 97% has been achieved for discriminating sitting and walking, 89% for standing, 72-75% for walking the stairs. Transient actions like standing up and sitting down have been detected with accuracy 56% and 38%, respectively. Even though there are studies declaring higher accuracy, none of them considered a set of activities analyzed in this research.
{"title":"Artificial neural networks in accelerometer-based human activity recognition","authors":"Paula Lubina, M. Rudzki","doi":"10.1109/MIXDES.2015.7208482","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208482","url":null,"abstract":"This paper presents a study aimed to assess applicability of artificial neural networks (ANNs) in human activity recognition from simple features derived from accelerometric signals. Secondary goal was to select the most descriptive signal features and sensor locations to be used as inputs to ANNs. Five triaxial accelerometers were attached to human body in the following places: one at back, two at waist laterally and two at both ankles. The set of activities to be recognized was established to include the most often performed actions in home environment. In total 25 subjects performed a set of predefined actions like walking, going up and down the stairs, sitting down and standing up from a chair. Acquired signals were divided into 0.5s time windows by a label defining the action performed. Several statistical signal features were calculated and used to train ANNs. Learning and testing were performed on separate data sets. Analysis using Fisher Linear Discriminant showed that despite the fact that some of the calculated values play a significant role in the distinction between similar activities, none of the features or sensors could be omitted in the recognition of the activities considered in the study. Accuracy of 97% has been achieved for discriminating sitting and walking, 89% for standing, 72-75% for walking the stairs. Transient actions like standing up and sitting down have been detected with accuracy 56% and 38%, respectively. Even though there are studies declaring higher accuracy, none of them considered a set of activities analyzed in this research.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128064289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208560
Piotr Kocanda, A. Kos
The aim of this paper is energy dissipation analysis in regards to supply voltage and temperature. The basis of all simulations are 12 different transistors coming from 6 different CMOS technologies (from 180nm to 14nm). Dynamic energy used to switch a gate from one state to the other was evaluated in a range of temperature for different supply voltages. In order to guarantee a realistic timing of control signals a special testing circuit was designed. Change of dynamic energy, as a function of temperature, regardless of supply voltage fits in range of -0.5-7.3%. Static power dissipation, a result of existing leakage currents, rises with temperature. When temperature rises from 20 to 100°C static power multiplicities at least 3 times up to 85 times. When operating with low activity static energy consumptions has higher impact on total energy consumption. In most cases one cannot ignore temperature influence on energy consumption.
{"title":"Static and dynamic energy losses vs. temperature in different CMOS technologies","authors":"Piotr Kocanda, A. Kos","doi":"10.1109/MIXDES.2015.7208560","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208560","url":null,"abstract":"The aim of this paper is energy dissipation analysis in regards to supply voltage and temperature. The basis of all simulations are 12 different transistors coming from 6 different CMOS technologies (from 180nm to 14nm). Dynamic energy used to switch a gate from one state to the other was evaluated in a range of temperature for different supply voltages. In order to guarantee a realistic timing of control signals a special testing circuit was designed. Change of dynamic energy, as a function of temperature, regardless of supply voltage fits in range of -0.5-7.3%. Static power dissipation, a result of existing leakage currents, rises with temperature. When temperature rises from 20 to 100°C static power multiplicities at least 3 times up to 85 times. When operating with low activity static energy consumptions has higher impact on total energy consumption. In most cases one cannot ignore temperature influence on energy consumption.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208578
E. Voulgari, M. Noy, F. Anghinolfi, F. Krummenacher, M. Kayal
This paper introduces some design and measurement techniques that were used in the design and the testing of an ASIC for ultra-low current sensing. The idea behind this paper is to present the limitations in sub-picoampere current measurements and demonstrate an ASIC that can accurately measure the different sources of leakage currents and the methodology of measuring. Then the leakage current can be subtracted or compensated in order to accurately measure the ultra-low current that is generated from a sensor/detector. The proposed ASIC can measure currents as low as -50 fA, a value well below similar ASIC implementations.
{"title":"Design and measurement methodology for a sub-picoampere current digitiser","authors":"E. Voulgari, M. Noy, F. Anghinolfi, F. Krummenacher, M. Kayal","doi":"10.1109/MIXDES.2015.7208578","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208578","url":null,"abstract":"This paper introduces some design and measurement techniques that were used in the design and the testing of an ASIC for ultra-low current sensing. The idea behind this paper is to present the limitations in sub-picoampere current measurements and demonstrate an ASIC that can accurately measure the different sources of leakage currents and the methodology of measuring. Then the leakage current can be subtracted or compensated in order to accurately measure the ultra-low current that is generated from a sensor/detector. The proposed ASIC can measure currents as low as -50 fA, a value well below similar ASIC implementations.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114645299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208520
Andreas Dixius, D. Walter, S. Höppner, H. Eisenreich, R. Schüffny
This paper introduces a design independent extension to RTL-to-GDS design-flows for seamless insertion of timing-detection flip-flops at critical paths of a digital CMOS standard-cell circuit. It is possible to detect timing-errors for general purposes at any critical path including enable-inputs of clock-gating cells with typically 15% area overhead for 20% endpoint coverage while maintaining DFT capability. To ensure matching of critical-path endpoints and detector cells 3 incremental place &route iterations are needed on average.
{"title":"A deep-submicron CMOS flow for general-purpose timing-detection insertion","authors":"Andreas Dixius, D. Walter, S. Höppner, H. Eisenreich, R. Schüffny","doi":"10.1109/MIXDES.2015.7208520","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208520","url":null,"abstract":"This paper introduces a design independent extension to RTL-to-GDS design-flows for seamless insertion of timing-detection flip-flops at critical paths of a digital CMOS standard-cell circuit. It is possible to detect timing-errors for general purposes at any critical path including enable-inputs of clock-gating cells with typically 15% area overhead for 20% endpoint coverage while maintaining DFT capability. To ensure matching of critical-path endpoints and detector cells 3 incremental place &route iterations are needed on average.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123835374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208541
R. Dlugosz, G. Fischer
In this paper we present a novel successive approximation register (SAR) analog-to-digital converter (ADC) designed for the applications that demand many such converters working in parallel in a single chip. For this reason we have put a special emphasis on a very low chip area and low power dissipation. The ADC operates in the current-mode. The digital-to-analog converter (DAC), which is one of the components of the SAR ADCs, is in this case based on a concept of a two-stage split architecture that allows to obtain higher resolutions without a substantial increase of the chip area. As a result, the circuit implemented in the IHP CMOS 130nm technology occupies the area of only 0.01 mm2. At data rate of 0.55 MSamples/s and 10-bits of resolution it dissipates an average power of 13.2 μW. The supply voltage equals 1.2 V. The proposed circuit is programmable. The 2-stage DAC is composed of 10 branches. If smaller resolutions are sufficient, we can select the branches which are used to perform the conversion. This allows to control, to some extent, data rate of the ADC and the power dissipation.
{"title":"Low chip area, low power dissipation, programmable, current mode, 10-bits, SAR ADC implemented in the CMOS 130nm technology","authors":"R. Dlugosz, G. Fischer","doi":"10.1109/MIXDES.2015.7208541","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208541","url":null,"abstract":"In this paper we present a novel successive approximation register (SAR) analog-to-digital converter (ADC) designed for the applications that demand many such converters working in parallel in a single chip. For this reason we have put a special emphasis on a very low chip area and low power dissipation. The ADC operates in the current-mode. The digital-to-analog converter (DAC), which is one of the components of the SAR ADCs, is in this case based on a concept of a two-stage split architecture that allows to obtain higher resolutions without a substantial increase of the chip area. As a result, the circuit implemented in the IHP CMOS 130nm technology occupies the area of only 0.01 mm2. At data rate of 0.55 MSamples/s and 10-bits of resolution it dissipates an average power of 13.2 μW. The supply voltage equals 1.2 V. The proposed circuit is programmable. The 2-stage DAC is composed of 10 branches. If smaller resolutions are sufficient, we can select the branches which are used to perform the conversion. This allows to control, to some extent, data rate of the ADC and the power dissipation.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123902756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208540
J. Nilsson, J. Borg, J. Johansson
The design of a 450nW bandgap temperature sensor in the 0 to 175°C range is presented. The design demonstrates a leakage current compensation technique that is useful for low-power designs where transistor performance is limited. The technique mitigates the effects of leakage in Brokaw bandgap references by limiting the amount of excess current that is entering the bases of the main bipolar pair due to leakage. Using this technique, Monte Carlo simulations show an improvement factor of 7.6 for the variation of the temperature sensitivity over the full temperature range. For the variation of the reference voltage, Monte Carlo simulations show an improvement factor of 2.3. Sensors built using this technique can be used to accurately monitor the temperature of power semiconductors since wireless temperature sensors become feasible with sufficiently low power consumption.
{"title":"Leakage current compensation for a 450 nW, high-temperature, bandgap temperature sensor","authors":"J. Nilsson, J. Borg, J. Johansson","doi":"10.1109/MIXDES.2015.7208540","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208540","url":null,"abstract":"The design of a 450nW bandgap temperature sensor in the 0 to 175°C range is presented. The design demonstrates a leakage current compensation technique that is useful for low-power designs where transistor performance is limited. The technique mitigates the effects of leakage in Brokaw bandgap references by limiting the amount of excess current that is entering the bases of the main bipolar pair due to leakage. Using this technique, Monte Carlo simulations show an improvement factor of 7.6 for the variation of the temperature sensitivity over the full temperature range. For the variation of the reference voltage, Monte Carlo simulations show an improvement factor of 2.3. Sensors built using this technique can be used to accurately monitor the temperature of power semiconductors since wireless temperature sensors become feasible with sufficiently low power consumption.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115972716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208599
M. Grobelny, I. Grobelna
The paper introduces a logic controller design system, called PNAD, supporting UML activity diagrams in version 2.x as a semi-formal specification technique. The system enables transformation of activity diagrams into control Petri nets, their formal verification using model checking technique and the nuXmv tool, generation of synthesizable code in hardware description language VHDL and generation of C code for microcontrollers. The benefits include the support for discrete event system development since the specification till prototype implementation. Additionally, reverse transformation from control Petri nets into UML activity diagrams is also possible. The internal representation of diagrams is based on XML files. The usage of proposed system is illustrated on an example of concrete production process.
{"title":"Logic controller design system supporting UML activity diagrams","authors":"M. Grobelny, I. Grobelna","doi":"10.1109/MIXDES.2015.7208599","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208599","url":null,"abstract":"The paper introduces a logic controller design system, called PNAD, supporting UML activity diagrams in version 2.x as a semi-formal specification technique. The system enables transformation of activity diagrams into control Petri nets, their formal verification using model checking technique and the nuXmv tool, generation of synthesizable code in hardware description language VHDL and generation of C code for microcontrollers. The benefits include the support for discrete event system development since the specification till prototype implementation. Additionally, reverse transformation from control Petri nets into UML activity diagrams is also possible. The internal representation of diagrams is based on XML files. The usage of proposed system is illustrated on an example of concrete production process.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"48 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115393274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208596
P. Dabal, R. Pelka
Pseudo-random number generators (PRNGs) are one of the common parts of digital systems used in cryptography, diagnostics, simulation and in many other areas of modern science and technology. Here we present a novel architecture of the PRNG based on the chaotic nonlinear model and pipelined data processing. A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx and verified by standard statistical tests NIST SP800-22. For PRNGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRNG implementation in the programmable SoC device. The maximum output throughput of the proposed PRNG is equal to 38.44 Gbps and is significantly greater comparing to the chaotic PRNGs described so far.
{"title":"An efficient post-processing method for pipelined pseudo-random number generator in SoC-FPGA","authors":"P. Dabal, R. Pelka","doi":"10.1109/MIXDES.2015.7208596","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208596","url":null,"abstract":"Pseudo-random number generators (PRNGs) are one of the common parts of digital systems used in cryptography, diagnostics, simulation and in many other areas of modern science and technology. Here we present a novel architecture of the PRNG based on the chaotic nonlinear model and pipelined data processing. A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx and verified by standard statistical tests NIST SP800-22. For PRNGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRNG implementation in the programmable SoC device. The maximum output throughput of the proposed PRNG is equal to 38.44 Gbps and is significantly greater comparing to the chaotic PRNGs described so far.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115405091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208503
Bernd Landgraf
New challenges are arising with the entrance in sub-100 nm CMOS nodes. Dominant sources of the MOSFET leakage which differ from those of previous nodes are examined. Consequences for the analog circuit design due to smaller dimensions and an accompanying higher variance of important analog parameters like threshold voltage in combination with shrinking VDD headroom are highlighted. As an example, the matching behavior of long channel and short channel halo-doped MOSFETS is examined. Furthermore, the disadvantages of the BEOL (Back End Of Line) due to the smaller dimensions are analyzed. Especially the reliability requirements of these BEOL design rules are discussed. Consequences on the layout are demonstrated by applying an EM & IR drop tool.
{"title":"Challenges for analog circuits in sub-100 nm CMOS nodes","authors":"Bernd Landgraf","doi":"10.1109/MIXDES.2015.7208503","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208503","url":null,"abstract":"New challenges are arising with the entrance in sub-100 nm CMOS nodes. Dominant sources of the MOSFET leakage which differ from those of previous nodes are examined. Consequences for the analog circuit design due to smaller dimensions and an accompanying higher variance of important analog parameters like threshold voltage in combination with shrinking VDD headroom are highlighted. As an example, the matching behavior of long channel and short channel halo-doped MOSFETS is examined. Furthermore, the disadvantages of the BEOL (Back End Of Line) due to the smaller dimensions are analyzed. Especially the reliability requirements of these BEOL design rules are discussed. Consequences on the layout are demonstrated by applying an EM & IR drop tool.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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