Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208585
J. Jasielski, S. Kuta, W. Kołodziejski, W. Machowski
In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.
{"title":"Hybrid LBDD PWM modulator for digital class-BD audio amplifier based on STM32F407VGT6 microcontroller and analog DLL","authors":"J. Jasielski, S. Kuta, W. Kołodziejski, W. Machowski","doi":"10.1109/MIXDES.2015.7208585","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208585","url":null,"abstract":"In the paper a new architecture and implementation of the 9-bit hybrid LBDD PWM modulator for digital Class-BD audio amplifier has been proposed. First, the PCM audio signal is transformed into the requantized to 9-bit resolution DPWM data, using LBDD algorithm. Then the 9-bit DPWM data are converted into the two physical trains of PWM pulses to control the output power transistors, using two hybrid digital to time converters (HDTC). The HDTC converts 6 MSB data on the base counter method using advanced-control timers TIM1 and TIM8 of the STM32F407VGT6 microcontroller, while the remaining 4 LSB data - using a quantizer system based on the tapped voltage controlled delay line (TVCDL) put into the ADLL loop, which have been designed in 180nm CMOS technology from UMC. A basic feasibility study of proposed configuration has been performed.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123790450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208582
J. D. Melo, Pedro V. Leitão, J. Goes, N. Paulino
This paper presents a class-D power amplifier for medium quality sound systems using a second-order passive sigma-delta modulator (ΣΔM). The ΣΔM controls an output power stage consisting of a H-bridge. The loop filter of the ΣΔM was designed using a optimization procedure based on genetic algorithm (GA), that takes into account several parameters. This system was implemented using discrete components and the experimental results show that a DR of 75 dB is achieved with a peak signal-to-noise-plus-distortion ratio (SNDR) of 54 dB.
{"title":"A simple class-D audio power amplifier using a passive CT ΣΔ modulator for medium quality sound systems","authors":"J. D. Melo, Pedro V. Leitão, J. Goes, N. Paulino","doi":"10.1109/MIXDES.2015.7208582","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208582","url":null,"abstract":"This paper presents a class-D power amplifier for medium quality sound systems using a second-order passive sigma-delta modulator (ΣΔM). The ΣΔM controls an output power stage consisting of a H-bridge. The loop filter of the ΣΔM was designed using a optimization procedure based on genetic algorithm (GA), that takes into account several parameters. This system was implemented using discrete components and the experimental results show that a DR of 75 dB is achieved with a peak signal-to-noise-plus-distortion ratio (SNDR) of 54 dB.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208578
E. Voulgari, M. Noy, F. Anghinolfi, F. Krummenacher, M. Kayal
This paper introduces some design and measurement techniques that were used in the design and the testing of an ASIC for ultra-low current sensing. The idea behind this paper is to present the limitations in sub-picoampere current measurements and demonstrate an ASIC that can accurately measure the different sources of leakage currents and the methodology of measuring. Then the leakage current can be subtracted or compensated in order to accurately measure the ultra-low current that is generated from a sensor/detector. The proposed ASIC can measure currents as low as -50 fA, a value well below similar ASIC implementations.
{"title":"Design and measurement methodology for a sub-picoampere current digitiser","authors":"E. Voulgari, M. Noy, F. Anghinolfi, F. Krummenacher, M. Kayal","doi":"10.1109/MIXDES.2015.7208578","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208578","url":null,"abstract":"This paper introduces some design and measurement techniques that were used in the design and the testing of an ASIC for ultra-low current sensing. The idea behind this paper is to present the limitations in sub-picoampere current measurements and demonstrate an ASIC that can accurately measure the different sources of leakage currents and the methodology of measuring. Then the leakage current can be subtracted or compensated in order to accurately measure the ultra-low current that is generated from a sensor/detector. The proposed ASIC can measure currents as low as -50 fA, a value well below similar ASIC implementations.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114645299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208520
Andreas Dixius, D. Walter, S. Höppner, H. Eisenreich, R. Schüffny
This paper introduces a design independent extension to RTL-to-GDS design-flows for seamless insertion of timing-detection flip-flops at critical paths of a digital CMOS standard-cell circuit. It is possible to detect timing-errors for general purposes at any critical path including enable-inputs of clock-gating cells with typically 15% area overhead for 20% endpoint coverage while maintaining DFT capability. To ensure matching of critical-path endpoints and detector cells 3 incremental place &route iterations are needed on average.
{"title":"A deep-submicron CMOS flow for general-purpose timing-detection insertion","authors":"Andreas Dixius, D. Walter, S. Höppner, H. Eisenreich, R. Schüffny","doi":"10.1109/MIXDES.2015.7208520","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208520","url":null,"abstract":"This paper introduces a design independent extension to RTL-to-GDS design-flows for seamless insertion of timing-detection flip-flops at critical paths of a digital CMOS standard-cell circuit. It is possible to detect timing-errors for general purposes at any critical path including enable-inputs of clock-gating cells with typically 15% area overhead for 20% endpoint coverage while maintaining DFT capability. To ensure matching of critical-path endpoints and detector cells 3 incremental place &route iterations are needed on average.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123835374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208587
R. K. Sharma, P. Hazdra, S. Popelka
This paper presents the development of simulation models for proton and carbon irradiated 4H-SiC junction barrier Schottky (JBS) diodes. Compared to protons, heavier carbon ions introduce more defects with deeper levels in the SiC bandgap and more stable damage. For the first time, the free carrier concentration profile extracted from CV simulations for irradiated JBS diode has been compared with experimental data. The simulation exhibit excellent matching with experimental data and can be very useful for the optimization of SiC power devices. Furthermore, the developed model can be used for the simulation of carrier life time control in PiN diode.
{"title":"Simulation and characterization of ion irradiated 4H-SiC JBS diode","authors":"R. K. Sharma, P. Hazdra, S. Popelka","doi":"10.1109/MIXDES.2015.7208587","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208587","url":null,"abstract":"This paper presents the development of simulation models for proton and carbon irradiated 4H-SiC junction barrier Schottky (JBS) diodes. Compared to protons, heavier carbon ions introduce more defects with deeper levels in the SiC bandgap and more stable damage. For the first time, the free carrier concentration profile extracted from CV simulations for irradiated JBS diode has been compared with experimental data. The simulation exhibit excellent matching with experimental data and can be very useful for the optimization of SiC power devices. Furthermore, the developed model can be used for the simulation of carrier life time control in PiN diode.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121583914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208590
R. Kapela, P. Sniatala, A. Turkot, A. Rybarczyk, A. Pożarycki, P. Rydzewski, Michael J. Wyczalek, Adam Bloch
Cracks are the most requiring type of pavement distresses to detect and classify automatically. Due to its nature are easily absorbed by other types of pavement surface damages. Moreover, the diversity of pavement surface makes the image detection system requiring efficient computer algorithms. The paper presents the solutions tested on surface distress data which were collected automatically using downward facing cameras placed orthogonally to road pavement axis. Presented results focus on the crack-type pavement distresses. The achieved accuracy of the transverse, longitudinal and meshing cracks recognition based on the initial dataset prepared especially for this system, show it has very good chances to work efficiently with large image datasets collected during the inspection car runs.
{"title":"Asphalt surfaced pavement cracks detection based on histograms of oriented gradients","authors":"R. Kapela, P. Sniatala, A. Turkot, A. Rybarczyk, A. Pożarycki, P. Rydzewski, Michael J. Wyczalek, Adam Bloch","doi":"10.1109/MIXDES.2015.7208590","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208590","url":null,"abstract":"Cracks are the most requiring type of pavement distresses to detect and classify automatically. Due to its nature are easily absorbed by other types of pavement surface damages. Moreover, the diversity of pavement surface makes the image detection system requiring efficient computer algorithms. The paper presents the solutions tested on surface distress data which were collected automatically using downward facing cameras placed orthogonally to road pavement axis. Presented results focus on the crack-type pavement distresses. The achieved accuracy of the transverse, longitudinal and meshing cracks recognition based on the initial dataset prepared especially for this system, show it has very good chances to work efficiently with large image datasets collected during the inspection car runs.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121970640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208560
Piotr Kocanda, A. Kos
The aim of this paper is energy dissipation analysis in regards to supply voltage and temperature. The basis of all simulations are 12 different transistors coming from 6 different CMOS technologies (from 180nm to 14nm). Dynamic energy used to switch a gate from one state to the other was evaluated in a range of temperature for different supply voltages. In order to guarantee a realistic timing of control signals a special testing circuit was designed. Change of dynamic energy, as a function of temperature, regardless of supply voltage fits in range of -0.5-7.3%. Static power dissipation, a result of existing leakage currents, rises with temperature. When temperature rises from 20 to 100°C static power multiplicities at least 3 times up to 85 times. When operating with low activity static energy consumptions has higher impact on total energy consumption. In most cases one cannot ignore temperature influence on energy consumption.
{"title":"Static and dynamic energy losses vs. temperature in different CMOS technologies","authors":"Piotr Kocanda, A. Kos","doi":"10.1109/MIXDES.2015.7208560","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208560","url":null,"abstract":"The aim of this paper is energy dissipation analysis in regards to supply voltage and temperature. The basis of all simulations are 12 different transistors coming from 6 different CMOS technologies (from 180nm to 14nm). Dynamic energy used to switch a gate from one state to the other was evaluated in a range of temperature for different supply voltages. In order to guarantee a realistic timing of control signals a special testing circuit was designed. Change of dynamic energy, as a function of temperature, regardless of supply voltage fits in range of -0.5-7.3%. Static power dissipation, a result of existing leakage currents, rises with temperature. When temperature rises from 20 to 100°C static power multiplicities at least 3 times up to 85 times. When operating with low activity static energy consumptions has higher impact on total energy consumption. In most cases one cannot ignore temperature influence on energy consumption.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208571
P. Buccella, C. Stefanucci, J. Sallese, M. Kayal
When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our methodology consists in integrating a new substrate model in spice to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.
{"title":"Spice simulation of passive protection in smart power ICs","authors":"P. Buccella, C. Stefanucci, J. Sallese, M. Kayal","doi":"10.1109/MIXDES.2015.7208571","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208571","url":null,"abstract":"When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electrical key parameters of a passive protection directly within standard IC design flow avoiding time consuming TCAD simulations. Our methodology consists in integrating a new substrate model in spice to enable designers to derive themselves process specific design rules and reduce substrate couplings. This methodology enables designers to access valuable results in the early stage of IC design, where before such results could be obtained only in the final verification step.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127849497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208596
P. Dabal, R. Pelka
Pseudo-random number generators (PRNGs) are one of the common parts of digital systems used in cryptography, diagnostics, simulation and in many other areas of modern science and technology. Here we present a novel architecture of the PRNG based on the chaotic nonlinear model and pipelined data processing. A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx and verified by standard statistical tests NIST SP800-22. For PRNGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRNG implementation in the programmable SoC device. The maximum output throughput of the proposed PRNG is equal to 38.44 Gbps and is significantly greater comparing to the chaotic PRNGs described so far.
{"title":"An efficient post-processing method for pipelined pseudo-random number generator in SoC-FPGA","authors":"P. Dabal, R. Pelka","doi":"10.1109/MIXDES.2015.7208596","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208596","url":null,"abstract":"Pseudo-random number generators (PRNGs) are one of the common parts of digital systems used in cryptography, diagnostics, simulation and in many other areas of modern science and technology. Here we present a novel architecture of the PRNG based on the chaotic nonlinear model and pipelined data processing. A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx and verified by standard statistical tests NIST SP800-22. For PRNGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRNG implementation in the programmable SoC device. The maximum output throughput of the proposed PRNG is equal to 38.44 Gbps and is significantly greater comparing to the chaotic PRNGs described so far.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115405091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-25DOI: 10.1109/MIXDES.2015.7208540
J. Nilsson, J. Borg, J. Johansson
The design of a 450nW bandgap temperature sensor in the 0 to 175°C range is presented. The design demonstrates a leakage current compensation technique that is useful for low-power designs where transistor performance is limited. The technique mitigates the effects of leakage in Brokaw bandgap references by limiting the amount of excess current that is entering the bases of the main bipolar pair due to leakage. Using this technique, Monte Carlo simulations show an improvement factor of 7.6 for the variation of the temperature sensitivity over the full temperature range. For the variation of the reference voltage, Monte Carlo simulations show an improvement factor of 2.3. Sensors built using this technique can be used to accurately monitor the temperature of power semiconductors since wireless temperature sensors become feasible with sufficiently low power consumption.
{"title":"Leakage current compensation for a 450 nW, high-temperature, bandgap temperature sensor","authors":"J. Nilsson, J. Borg, J. Johansson","doi":"10.1109/MIXDES.2015.7208540","DOIUrl":"https://doi.org/10.1109/MIXDES.2015.7208540","url":null,"abstract":"The design of a 450nW bandgap temperature sensor in the 0 to 175°C range is presented. The design demonstrates a leakage current compensation technique that is useful for low-power designs where transistor performance is limited. The technique mitigates the effects of leakage in Brokaw bandgap references by limiting the amount of excess current that is entering the bases of the main bipolar pair due to leakage. Using this technique, Monte Carlo simulations show an improvement factor of 7.6 for the variation of the temperature sensitivity over the full temperature range. For the variation of the reference voltage, Monte Carlo simulations show an improvement factor of 2.3. Sensors built using this technique can be used to accurately monitor the temperature of power semiconductors since wireless temperature sensors become feasible with sufficiently low power consumption.","PeriodicalId":188240,"journal":{"name":"2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES)","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115972716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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