Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375898
B. Kasprowicz, Siamak Mogharrabi, Martin Carrier, Andrew G. Zanzal, Patrick Reynolds, Corey Shay, K. Best
In the next few years, advanced process technologies in advanced packaging fabs will migrate rapidly to reduction lithography to achieve 2/2 RDL and beyond. Reticle enhancement techniques, such as Optical Proximity Correction (OPC) may be required in multiple reticle layers to provide sufficient process latitude for high volume manufacturing. However, a challenge in the manufacturing of OPC reticles is the lack of a precise specifications for defect inspection with respect to the printability on wafers [1]. In this paper, the printability of reticle defects for 2/2 micrometers Redistribution Layer (RDL) design rule are studied via i-line resist process. The reticle defect printability is determined by considering the wafer process critical dimension (CD) variability. In the experiment, an i-line 2x reduction stepper with 0.1 NA imaging lens was used to expose the programmed defect reticle. The resist CD response to the reticle defect area is measured under a variety of process conditions, i.e., different exposure dose or focusThe programmed defect reticles consisted of both Clear and Dark Field polarities comprising of 2/2 design rules will be used for the printability study. Defects such as intrusions and protrusions at various sizes on RDL patterns, have been characterized. Defect disposition comparing reticle to designed programmed defects to those without will be shown as well as the impact of the defect on patterning performance. Finally, the allowable reticle defect requirement is assessed where the printable reticle defect size is tied to the wafer process specifications and the actual wafer process CD controllability. The influence of the reticle manufacturing processes on wafer patterning performance is examined. Through this comparison, insights into target specifications (MTT, CDU, defects) for advanced RDL reticles can be derived while balancing cost tradeoffs.
{"title":"Defect Printability for 2/2 RDL and The Impact of Advanced Reticle Processes","authors":"B. Kasprowicz, Siamak Mogharrabi, Martin Carrier, Andrew G. Zanzal, Patrick Reynolds, Corey Shay, K. Best","doi":"10.23919/IWLPC52010.2020.9375898","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375898","url":null,"abstract":"In the next few years, advanced process technologies in advanced packaging fabs will migrate rapidly to reduction lithography to achieve 2/2 RDL and beyond. Reticle enhancement techniques, such as Optical Proximity Correction (OPC) may be required in multiple reticle layers to provide sufficient process latitude for high volume manufacturing. However, a challenge in the manufacturing of OPC reticles is the lack of a precise specifications for defect inspection with respect to the printability on wafers [1]. In this paper, the printability of reticle defects for 2/2 micrometers Redistribution Layer (RDL) design rule are studied via i-line resist process. The reticle defect printability is determined by considering the wafer process critical dimension (CD) variability. In the experiment, an i-line 2x reduction stepper with 0.1 NA imaging lens was used to expose the programmed defect reticle. The resist CD response to the reticle defect area is measured under a variety of process conditions, i.e., different exposure dose or focusThe programmed defect reticles consisted of both Clear and Dark Field polarities comprising of 2/2 design rules will be used for the printability study. Defects such as intrusions and protrusions at various sizes on RDL patterns, have been characterized. Defect disposition comparing reticle to designed programmed defects to those without will be shown as well as the impact of the defect on patterning performance. Finally, the allowable reticle defect requirement is assessed where the printable reticle defect size is tied to the wafer process specifications and the actual wafer process CD controllability. The influence of the reticle manufacturing processes on wafer patterning performance is examined. Through this comparison, insights into target specifications (MTT, CDU, defects) for advanced RDL reticles can be derived while balancing cost tradeoffs.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116043052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375875
G. Farris
Semiconductor and Semi equipment industries expect to see a strong upturn in the next few years, with advanced packaging technologies a significant beneficiary of the markets strength. 5G, AI, Edge Computing, Persistent Memory, Integrated Power Management, and the transition to sub 5nm silicon technology are all driving the need for innovative packaging solutions. These solutions integrate silicon produced with disparate process nodes and deliver maximum performance at optimal cost. Heterogeneous Integration, utilizing a multitude of interconnect methodologies (from Fan-out to Silicon Interposer, to Chiplet), addresses this challenge but requires unique solutions for efficient, cost effective die placement. High speed, high precision multi-die placement, directly and efficiently extracted from a range of different sized wafers, is critical to enable cost effective assembly. This paper looks at the challenges and potential approaches for efficient and cost effective solutions.
{"title":"Emerging Process and Assembly Challenges in Electronics Manufacturing","authors":"G. Farris","doi":"10.23919/IWLPC52010.2020.9375875","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375875","url":null,"abstract":"Semiconductor and Semi equipment industries expect to see a strong upturn in the next few years, with advanced packaging technologies a significant beneficiary of the markets strength. 5G, AI, Edge Computing, Persistent Memory, Integrated Power Management, and the transition to sub 5nm silicon technology are all driving the need for innovative packaging solutions. These solutions integrate silicon produced with disparate process nodes and deliver maximum performance at optimal cost. Heterogeneous Integration, utilizing a multitude of interconnect methodologies (from Fan-out to Silicon Interposer, to Chiplet), addresses this challenge but requires unique solutions for efficient, cost effective die placement. High speed, high precision multi-die placement, directly and efficiently extracted from a range of different sized wafers, is critical to enable cost effective assembly. This paper looks at the challenges and potential approaches for efficient and cost effective solutions.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126136783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375887
Jacinta Aman Lim, Yun-Mook Park, Byung-Cheol Kim, Edil Devera
300mm carrier wafer for Fan-Out Wafer Level Packaging (FOWLP), is currently the mainstream format used for PMICs, RF and other single die applications. As volume of these devices continue to ramp up, the 300mm medium used for Fan-Out processing continues to stay the same. The need for migrating to panel sizes larger than 300mm becomes a necessity to lower down costs and handle higher volumes. The fastest adoption of Fan-Out technology is now in 5G, automotive and healthcare. Traditional applications such as audio codecs, PMICs, microcontroller units (MCU) and radio frequency (RF) continue to use Fan-Out Wafer Level Packaging (FOWLP) as an alternative to Wafer Level Chip Scale packaging (WLCSP) due to its 5 -sided or 6-sided die protection. As Fan Out packaging becomes mainstream and to get broader adoption of Fan-Out, the need for driving down the cost continues to be at the forefront of Fan-Out suppliers. 600mm × 600mm format utilized in this study leverages existing backend processing equipment used on 200mm and 300mm wafers for cost savings. Utilizing existing equipment would enable the panel to be singulated into 4 × 300mm or 9 × 200mm square segments to enable probe testing. Coupling the 6-sided die protection process (M-Series) with 600mm × 600mm panel level processing paves the way for innovative methods for Fan-Out processing. New photolithography processing utilizing laser direct imaging (Adaptive Patterning ™) to auto scale for die shift mitigation, is heavily dependent on segmentation of the panel. In this instance, the 600mm panel is either segmented into 4 × 300mm, 9 × 200mm or l×600mm for Photolithography steps. Depending on the number of fiducials used during the photolithography steps, capital expenditure and exposure accuracy would be highly dependent on the segmentation chosen. In addition, new metrology tools and panel warpage management will need to be considered for quality assurance. This paper will present a case study of utilizing 600mm × 600mm panel size to process a single die with 6-sided die protection (M-Series). Considerations for repassivation, redistribution layer and solder ball placement will be discussed. Challenges pertaining to large panel processing through the repassivation and redistribution layer will be presented, panel level inspection considerations post mold cure, reliability considerations and future of 600mm × 600mm panel level processing for 6-sided die protection will be summarized.
{"title":"600MM Wafer-Level Fan Out on Panel Level Processing with 6-Sided Die Protection","authors":"Jacinta Aman Lim, Yun-Mook Park, Byung-Cheol Kim, Edil Devera","doi":"10.23919/IWLPC52010.2020.9375887","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375887","url":null,"abstract":"300mm carrier wafer for Fan-Out Wafer Level Packaging (FOWLP), is currently the mainstream format used for PMICs, RF and other single die applications. As volume of these devices continue to ramp up, the 300mm medium used for Fan-Out processing continues to stay the same. The need for migrating to panel sizes larger than 300mm becomes a necessity to lower down costs and handle higher volumes. The fastest adoption of Fan-Out technology is now in 5G, automotive and healthcare. Traditional applications such as audio codecs, PMICs, microcontroller units (MCU) and radio frequency (RF) continue to use Fan-Out Wafer Level Packaging (FOWLP) as an alternative to Wafer Level Chip Scale packaging (WLCSP) due to its 5 -sided or 6-sided die protection. As Fan Out packaging becomes mainstream and to get broader adoption of Fan-Out, the need for driving down the cost continues to be at the forefront of Fan-Out suppliers. 600mm × 600mm format utilized in this study leverages existing backend processing equipment used on 200mm and 300mm wafers for cost savings. Utilizing existing equipment would enable the panel to be singulated into 4 × 300mm or 9 × 200mm square segments to enable probe testing. Coupling the 6-sided die protection process (M-Series) with 600mm × 600mm panel level processing paves the way for innovative methods for Fan-Out processing. New photolithography processing utilizing laser direct imaging (Adaptive Patterning ™) to auto scale for die shift mitigation, is heavily dependent on segmentation of the panel. In this instance, the 600mm panel is either segmented into 4 × 300mm, 9 × 200mm or l×600mm for Photolithography steps. Depending on the number of fiducials used during the photolithography steps, capital expenditure and exposure accuracy would be highly dependent on the segmentation chosen. In addition, new metrology tools and panel warpage management will need to be considered for quality assurance. This paper will present a case study of utilizing 600mm × 600mm panel size to process a single die with 6-sided die protection (M-Series). Considerations for repassivation, redistribution layer and solder ball placement will be discussed. Challenges pertaining to large panel processing through the repassivation and redistribution layer will be presented, panel level inspection considerations post mold cure, reliability considerations and future of 600mm × 600mm panel level processing for 6-sided die protection will be summarized.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128434913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375855
Max Min, Sylvie Kadivar
The explosion of big data along with the accelerated global socio economical transformations we are experiencing are dramatically transforming the way we live and work. These shifts are accelerating HPC, 5G, Mobile, AR/VR, IoT, Networking and AI infrastructure. Under “ More Moore ” paradigm, scaling down of new transistor and interconnect has been improved from 32nm high-K metal gate, 28nm/18nm FDSOI (Fully Depleted Silicon on Insulator), 14nm FINFET (Fin Field Effect Transistor), 7nm EUV (Extreme Ultraviolet Lithography) and down to 3nm GAA (Gate All Around). All these silicon technologies are helping to have more transistors and more functions in the system. However, developing transistors in advanced node processes is getting more challenging and costly. Consequently, further heterogeneous system integration requires solutions that go “ Beyond Moore ” paradigm. The solutions can be new system integration architecture and advanced packaging technologies [1]. For further discussion, let's discuss two memories: DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). DRAM has high density per mm2 and high latency whereas SRAM has low density per mm2 and low latency. In PC and Mobile era, low-latency SRAM was integrated into a logic as cache memory whereas high-latency DRAM was separately integrated as a discrete component that was assembled on system board or package. In new AI era where hundreds or thousands of computing cores are needed, there is a strong demand for new system architecture with low-latency, high-bandwidth and/or higher density SRAM in 3D. 3D SRAM integration is helping to have dedicated low-latency SRAM memory per computing core or cluster. Along with transistor scaling for SRAM and core logic, advanced 2.5/3D packaging technologies are essential to the success of design platforms tailored to these new demands requiring more and higher bandwidth SRAM memories next to computing logic devices with lower latency and satisfying the sharp curve of technology acceleration and adoption in new era [2]–[6]. After discussing DRAM and decoupling capacitor integration, this paper introduces the first generation of 3DIC wafer-level logic packaging technology called X-Cube and demonstrates the technology through package and functional test vehicles with stacked SRAM memories on top of a logic die.
{"title":"Accelerating Innovations in the New Era of HPC, 5G and Networking with Advanced 3D Packaging Technologies","authors":"Max Min, Sylvie Kadivar","doi":"10.23919/IWLPC52010.2020.9375855","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375855","url":null,"abstract":"The explosion of big data along with the accelerated global socio economical transformations we are experiencing are dramatically transforming the way we live and work. These shifts are accelerating HPC, 5G, Mobile, AR/VR, IoT, Networking and AI infrastructure. Under “ More Moore ” paradigm, scaling down of new transistor and interconnect has been improved from 32nm high-K metal gate, 28nm/18nm FDSOI (Fully Depleted Silicon on Insulator), 14nm FINFET (Fin Field Effect Transistor), 7nm EUV (Extreme Ultraviolet Lithography) and down to 3nm GAA (Gate All Around). All these silicon technologies are helping to have more transistors and more functions in the system. However, developing transistors in advanced node processes is getting more challenging and costly. Consequently, further heterogeneous system integration requires solutions that go “ Beyond Moore ” paradigm. The solutions can be new system integration architecture and advanced packaging technologies [1]. For further discussion, let's discuss two memories: DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). DRAM has high density per mm2 and high latency whereas SRAM has low density per mm2 and low latency. In PC and Mobile era, low-latency SRAM was integrated into a logic as cache memory whereas high-latency DRAM was separately integrated as a discrete component that was assembled on system board or package. In new AI era where hundreds or thousands of computing cores are needed, there is a strong demand for new system architecture with low-latency, high-bandwidth and/or higher density SRAM in 3D. 3D SRAM integration is helping to have dedicated low-latency SRAM memory per computing core or cluster. Along with transistor scaling for SRAM and core logic, advanced 2.5/3D packaging technologies are essential to the success of design platforms tailored to these new demands requiring more and higher bandwidth SRAM memories next to computing logic devices with lower latency and satisfying the sharp curve of technology acceleration and adoption in new era [2]–[6]. After discussing DRAM and decoupling capacitor integration, this paper introduces the first generation of 3DIC wafer-level logic packaging technology called X-Cube and demonstrates the technology through package and functional test vehicles with stacked SRAM memories on top of a logic die.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128451060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375901
M. Takeuchi, Tomoharu Nakayama, Hisamitsu Yamamoto
Typically, industrial electroless copper plating solutions use formaldehyde as a reducing agent. However, since formaldehyde has a strong odor and is a carcinogenic substance, it has an adverse effect on the working environment and the human body. Therefore, an electro-less copper plating solution containing no formaldehyde is desired. We have researched and developed a formaldehyde-free electro-less copper plating solution and evaluated its properties for applications such as panel level package (PLP). Price is the main reason for selecting agents with reducing power to copper for use in the plating market. We promoted to develop the plating solution using sodium hypophosphite as a reducing agent, which is the next least expensive after formalin solution. The reducing agent used in this plating solution has low catalytic activity for copper. As a result, when the palladium catalyst on the resin is covered with copper plating, the plating deposition rate is reduced. In order to prevent the deposition reaction from stopping during plating, a metal salt with high catalytic activity for this reducing agent is plated. The method of adding to the liquid was carried out. As a result, the bath stability of the development bath is excellent because no Cannizzaro reaction or disproportionate reaction of the first copper ion occurs, unlike ordinary electroless copper plating solutions. This is a major advantage in terms of running costs and requirements for ancillary the plating equipment. When the characteristics of the plating film by development bath were examined, the internal stress was found to be as low as 150 MPa on the tensile side. The adhesion to the ABF resin was high, ranging from 500 to 700 gf/cm. Also it exhibits excellent plating deposition inside blind via hole (BVH) which is equivalent to that of general electro-less copper plating solution, it can be applied to semi-additive process package boards where electro-less copper plating film is etched.
{"title":"Charactarization of Formaldehyde-Free Electro-Less Copper Plating for Semi-Additive Process","authors":"M. Takeuchi, Tomoharu Nakayama, Hisamitsu Yamamoto","doi":"10.23919/IWLPC52010.2020.9375901","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375901","url":null,"abstract":"Typically, industrial electroless copper plating solutions use formaldehyde as a reducing agent. However, since formaldehyde has a strong odor and is a carcinogenic substance, it has an adverse effect on the working environment and the human body. Therefore, an electro-less copper plating solution containing no formaldehyde is desired. We have researched and developed a formaldehyde-free electro-less copper plating solution and evaluated its properties for applications such as panel level package (PLP). Price is the main reason for selecting agents with reducing power to copper for use in the plating market. We promoted to develop the plating solution using sodium hypophosphite as a reducing agent, which is the next least expensive after formalin solution. The reducing agent used in this plating solution has low catalytic activity for copper. As a result, when the palladium catalyst on the resin is covered with copper plating, the plating deposition rate is reduced. In order to prevent the deposition reaction from stopping during plating, a metal salt with high catalytic activity for this reducing agent is plated. The method of adding to the liquid was carried out. As a result, the bath stability of the development bath is excellent because no Cannizzaro reaction or disproportionate reaction of the first copper ion occurs, unlike ordinary electroless copper plating solutions. This is a major advantage in terms of running costs and requirements for ancillary the plating equipment. When the characteristics of the plating film by development bath were examined, the internal stress was found to be as low as 150 MPa on the tensile side. The adhesion to the ABF resin was high, ranging from 500 to 700 gf/cm. Also it exhibits excellent plating deposition inside blind via hole (BVH) which is equivalent to that of general electro-less copper plating solution, it can be applied to semi-additive process package boards where electro-less copper plating film is etched.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131470898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375851
R. Santos, N. Ambrosius, Roman Ostholt, J. Delrue
Glass is not a new material for Wafer-Level Packaging (WLP) applications and technologies, however, its use is still very limited. Despite its low material cost and incredibly interesting properties, traditional glass microprocessing technologies inevitably increase its cost while negatively affecting the characteristics of glass that made it initially interesting. Laser Induced Deep Etching (LIDE®) is a glass processing technology, developed by LPKF Laser & Electronics [1], that enables highly precise and reliable micro featuring of glass. After processing, the glass is completely defect-free (no cracks, induced thermal stress, etc.) and retains all of its properties. LIDE consists of a two-step process: i) a maskless, direct-writing laser process that only requires a single pulse to modify the whole glass thickness, and ii) a wet etching process done in batch. In summary, this is an incredibly economical technology capable of bringing new life to glass for microelectronics and enabling its full potential for WLP applications. In this work, we will show how LIDE unlocks the use of glass for RF applications by taking full advantage of fused silica's low transmission loss and by enabling the creation of metallized paths in glass connected to through glass vias (TGV). We will also present high aspect-ratio glass interposers for more affordable 2.5D architectures. The formation of spacer wafers with high-accuracy openings of any shape, the production of capping wafers with anisotropically-etched straight sidewalls that significantly increase their die density, the use of glass springs for high precision passive die alignment features, and high throughput and quality dicing/singulation of glass wafers will also be introduced. Laser Induced Deep Etching (LIDE®) is a glass processing technology, developed by LPKF Laser & Electronics [1], that enables highly precise and reliable micro featuring of glass. After processing, the glass is completely defect-free (no cracks, induced thermal stress, etc.) and retains all of its properties. LIDE consists of a two-step process: i) a maskless, direct-writing laser process that only requires a single pulse to modify the whole glass thickness, and ii) a wet etching process done in batch. In summary, this is an incredibly economical technology capable of bringing new life to glass for microelectronics and enabling its full potential for WLP applications. In this work, we will show how LIDE unlocks the use of glass for RF applications by taking full advantage of fused silica's low transmission loss and by enabling the creation of metallized paths in glass connected to through glass vias (TGV). We will also present high aspect-ratio glass interposers for more affordable 2.5D architectures. The formation of spacer wafers with high-accuracy openings of any shape, the production of capping wafers with anisotropically -etched straight sidewalls that significantly increase their die density, the use of glass springs for hi
{"title":"Bringing New Life To Glass For Wafer-Level Packaging Applications","authors":"R. Santos, N. Ambrosius, Roman Ostholt, J. Delrue","doi":"10.23919/IWLPC52010.2020.9375851","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375851","url":null,"abstract":"Glass is not a new material for Wafer-Level Packaging (WLP) applications and technologies, however, its use is still very limited. Despite its low material cost and incredibly interesting properties, traditional glass microprocessing technologies inevitably increase its cost while negatively affecting the characteristics of glass that made it initially interesting. Laser Induced Deep Etching (LIDE®) is a glass processing technology, developed by LPKF Laser & Electronics [1], that enables highly precise and reliable micro featuring of glass. After processing, the glass is completely defect-free (no cracks, induced thermal stress, etc.) and retains all of its properties. LIDE consists of a two-step process: i) a maskless, direct-writing laser process that only requires a single pulse to modify the whole glass thickness, and ii) a wet etching process done in batch. In summary, this is an incredibly economical technology capable of bringing new life to glass for microelectronics and enabling its full potential for WLP applications. In this work, we will show how LIDE unlocks the use of glass for RF applications by taking full advantage of fused silica's low transmission loss and by enabling the creation of metallized paths in glass connected to through glass vias (TGV). We will also present high aspect-ratio glass interposers for more affordable 2.5D architectures. The formation of spacer wafers with high-accuracy openings of any shape, the production of capping wafers with anisotropically-etched straight sidewalls that significantly increase their die density, the use of glass springs for high precision passive die alignment features, and high throughput and quality dicing/singulation of glass wafers will also be introduced. Laser Induced Deep Etching (LIDE®) is a glass processing technology, developed by LPKF Laser & Electronics [1], that enables highly precise and reliable micro featuring of glass. After processing, the glass is completely defect-free (no cracks, induced thermal stress, etc.) and retains all of its properties. LIDE consists of a two-step process: i) a maskless, direct-writing laser process that only requires a single pulse to modify the whole glass thickness, and ii) a wet etching process done in batch. In summary, this is an incredibly economical technology capable of bringing new life to glass for microelectronics and enabling its full potential for WLP applications. In this work, we will show how LIDE unlocks the use of glass for RF applications by taking full advantage of fused silica's low transmission loss and by enabling the creation of metallized paths in glass connected to through glass vias (TGV). We will also present high aspect-ratio glass interposers for more affordable 2.5D architectures. The formation of spacer wafers with high-accuracy openings of any shape, the production of capping wafers with anisotropically -etched straight sidewalls that significantly increase their die density, the use of glass springs for hi","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375878
Tarek Ramadan, Sean Wang
Panel-level packaging such as fan-out wafer-level packaging (FOWLP) has been a promising technology for a number of years now, primarily as a means of packaging semiconductor devices containing interconnect densities that exceed the capabilities of standard wafer-level chipscale packaging (WLCSP). One of the historical barriers to the broad adoption of panel-level packaging is the yield loss associated with “die drift”-die that shift from their designed nominal positions within each package during the manufacturing process. To break through this barrier, we introduce a novel die drift patterning technology that recognizes and adjusts for die drift, making “design during manufacturing” feasible and practical. However, both panel-level packaging and the die drift patterning methodology introduce physical verification challenges that are unfamiliar to most package designers. Panel-level packaging uses a GDSII or OASIS format for the package design, similar to integrated circuit (IC) design databases. Although design rule checking (DRC) is normally run on each individual unit GDSII file, the Die drift patterning process must also be simulated on a complete panel as one overall GDSII mask. This panel GDSII mask includes unique characteristics, with typically thousands of units requiring concurrent verification. The process is substantially more challenging than a classic unit design, where many repetitive GDSII cells exist within a hierarchy that can be used by the verification tools to improve runtimes. Deca collaborated with Mentor, a Siemens business (Mentor) to optimize physical verification for this panel GDSII mask verification. Together, they worked to identify operational impediments and implement optimizations to the verification toolsuite that enabled the platform to support verification of the die drift patterning technology for M-Series fan-out panel level packaging, while also achieving a reasonable turnaround time (TAT) for panel verification. This optimization utilizes both CPU scaling capabilities and a novel computational approach that accounts for the unique characteristics of a die drift patterning panel-level GDSII mask.
{"title":"Physical Verification of Panel-Level Packaging Designs Utilizing Die Drift Patterning Technology","authors":"Tarek Ramadan, Sean Wang","doi":"10.23919/IWLPC52010.2020.9375878","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375878","url":null,"abstract":"Panel-level packaging such as fan-out wafer-level packaging (FOWLP) has been a promising technology for a number of years now, primarily as a means of packaging semiconductor devices containing interconnect densities that exceed the capabilities of standard wafer-level chipscale packaging (WLCSP). One of the historical barriers to the broad adoption of panel-level packaging is the yield loss associated with “die drift”-die that shift from their designed nominal positions within each package during the manufacturing process. To break through this barrier, we introduce a novel die drift patterning technology that recognizes and adjusts for die drift, making “design during manufacturing” feasible and practical. However, both panel-level packaging and the die drift patterning methodology introduce physical verification challenges that are unfamiliar to most package designers. Panel-level packaging uses a GDSII or OASIS format for the package design, similar to integrated circuit (IC) design databases. Although design rule checking (DRC) is normally run on each individual unit GDSII file, the Die drift patterning process must also be simulated on a complete panel as one overall GDSII mask. This panel GDSII mask includes unique characteristics, with typically thousands of units requiring concurrent verification. The process is substantially more challenging than a classic unit design, where many repetitive GDSII cells exist within a hierarchy that can be used by the verification tools to improve runtimes. Deca collaborated with Mentor, a Siemens business (Mentor) to optimize physical verification for this panel GDSII mask verification. Together, they worked to identify operational impediments and implement optimizations to the verification toolsuite that enabled the platform to support verification of the die drift patterning technology for M-Series fan-out panel level packaging, while also achieving a reasonable turnaround time (TAT) for panel verification. This optimization utilizes both CPU scaling capabilities and a novel computational approach that accounts for the unique characteristics of a die drift patterning panel-level GDSII mask.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133640151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375891
Kunal Shah
Wafer level packaging (WLP) in the semiconductor industry continues to grow especially in the areas of IOT, high speed/mobility, sensors, wearables, automotive and other critical applications. The requirements of the products from these markets include smaller footprint, perform optimally-electrically, cost-effective and reliable. WLP materials/chemistries are critical components in helping semiconductor manufacturers, OEMs to attain these requirements to achieve the best performance. One of the most important materials include surface finish on the copper features to support interconnect integration. The selection criteria of surface finish for high frequency, high density next generation WLP applications involve minimal insertion loss, long shelf life, cost-effective and high reliability. There are few options (ImAg, EPIG, EPAG, DIG, OSP, etc.) available in the market; however, there are concerns over fulfilling all the requirements for next generation applications. An innovative nickel-less approach involving a proprietary nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer has shown superior benefits over contemporaries. Reliability testing results will be discussed comparing performance benefit of novel surface finish.
{"title":"Novel Surface Finish for Next Generation Wafer Level Packaging Applications","authors":"Kunal Shah","doi":"10.23919/IWLPC52010.2020.9375891","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375891","url":null,"abstract":"Wafer level packaging (WLP) in the semiconductor industry continues to grow especially in the areas of IOT, high speed/mobility, sensors, wearables, automotive and other critical applications. The requirements of the products from these markets include smaller footprint, perform optimally-electrically, cost-effective and reliable. WLP materials/chemistries are critical components in helping semiconductor manufacturers, OEMs to attain these requirements to achieve the best performance. One of the most important materials include surface finish on the copper features to support interconnect integration. The selection criteria of surface finish for high frequency, high density next generation WLP applications involve minimal insertion loss, long shelf life, cost-effective and high reliability. There are few options (ImAg, EPIG, EPAG, DIG, OSP, etc.) available in the market; however, there are concerns over fulfilling all the requirements for next generation applications. An innovative nickel-less approach involving a proprietary nano-engineered barrier designed to coat copper contacts, finished with an outermost gold layer has shown superior benefits over contemporaries. Reliability testing results will be discussed comparing performance benefit of novel surface finish.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133905072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375899
Yuichi Kajikawa
Compression molding was developed and introduced by Towa in the early 2000s.Over the years, TOWA has continued to improve and enhance the performance and quality of compression molding and, as a result, it has been adopted for complex packaging solutions, especially those requiring low pressure or very thin molded packages. The ever-increasing demand for integration of different technologies and smaller and thinner footprint continues to march forward. These demands challenge mold compression technology to be further expanded and innovated to address even more complicated packaging requirements such as multi-die in large panel format. In parallel, quality and reliability while meeting these challenges for FOWLP in large panel are also considered in this paper. At present, FOWLP has been targeted for high-end products such as High-Performance Computing (HPC)/ Artificial Intelligence (AI) products using RDL-first / high-precision flip chip bonding process with thinning lines and increasing number of IOs. Furthermore, FO-PLP has become a low-end product target, and chip-first cost reduction is in progress. This paper will discuss the concerns & solutions created by compression molding for panelization to address its growing demand. Compression molding is also discussed as a solution to MUF (Mold Under-fill) associated with flip chip bonding due to the use of a degassing process that employs a highly airtight and high vacuum system, and the ability to dispense resin to the full molding area to suppressthe XY flow of resin during molding. In addition, since the structure is such that the force of the press is directly transmitted to the resin, the range of applicable pressure is wide and it is very effective especially for low pressure molding and particularly for fragile elements and ultra-thin interposers. These characteristics are very effective in the RDL-first process by providing a redistribution layer on the carrier, and helping in the suppression of warpage.
{"title":"Fan-Out Wafer-Level Packaging Advanced Manufacturing Solution for Fan-Out WLP/PLP by DFD (Die Face Down) Compression Mold","authors":"Yuichi Kajikawa","doi":"10.23919/IWLPC52010.2020.9375899","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375899","url":null,"abstract":"Compression molding was developed and introduced by Towa in the early 2000s.Over the years, TOWA has continued to improve and enhance the performance and quality of compression molding and, as a result, it has been adopted for complex packaging solutions, especially those requiring low pressure or very thin molded packages. The ever-increasing demand for integration of different technologies and smaller and thinner footprint continues to march forward. These demands challenge mold compression technology to be further expanded and innovated to address even more complicated packaging requirements such as multi-die in large panel format. In parallel, quality and reliability while meeting these challenges for FOWLP in large panel are also considered in this paper. At present, FOWLP has been targeted for high-end products such as High-Performance Computing (HPC)/ Artificial Intelligence (AI) products using RDL-first / high-precision flip chip bonding process with thinning lines and increasing number of IOs. Furthermore, FO-PLP has become a low-end product target, and chip-first cost reduction is in progress. This paper will discuss the concerns & solutions created by compression molding for panelization to address its growing demand. Compression molding is also discussed as a solution to MUF (Mold Under-fill) associated with flip chip bonding due to the use of a degassing process that employs a highly airtight and high vacuum system, and the ability to dispense resin to the full molding area to suppressthe XY flow of resin during molding. In addition, since the structure is such that the force of the press is directly transmitted to the resin, the range of applicable pressure is wide and it is very effective especially for low pressure molding and particularly for fragile elements and ultra-thin interposers. These characteristics are very effective in the RDL-first process by providing a redistribution layer on the carrier, and helping in the suppression of warpage.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122673447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375853
S. Erickson, Sanjay Malik
With growing demand for advanced computing systems and as personal handheld devices become more powerful, frontend manufacturers are required to reduce the physical footprint of and at the same time integrate more functionality into their chips. More I/O channels are packed into smaller areas than ever before in modern packages. The competing demands of increasing throughput and reducing costs makes the interconnection of these packages increasingly challenging. New methods to produce these high-density interconnections are required to meet these challenges. Chips are placed and connected both horizontally and vertically in 2.5D and 3D packaging. This created inherent topographical challenges for producing the interconnections. The industry's drive for cost reduction is building momentum toward more efficient and cost effective methods for creating the multi -layer high density interconnects. There are inherent topographical challenges associated with the growth of 2.5D and 3D packaging where chips are placed and interconnected horizontally and vertically. One critical area of interest is the formation of the passivation layer that enables connections between layers. Polyimides must be applied in a uniform layer to ensure that the inter-layer connections can properly be formed. Effectiveness of different film deposition methods is measured in terms of formation of uniform and void- free films to ensure intended mechanical and electrical integrity of the material is not compromised. Film deposition method can potentially influence not only film density but also polymer chain configuration that control key properties directly linked to the reliability of the material. While polarity of functional groups dictates moisture uptake, polymer chain configuration can control moisture permeability through the deposited film and its ability to act as corrosion barrier. We have previously reported creation of high -density vias printed in a dielectric film deposited by a revolutionary technique in the form of a novel nozzle-less ultrasonic spray technology. [1] This paper presents impact of such unique deposition method on key film properties like density and moisture permeability along with supporting reliability data under high temperature storage (HTS) and unbiased-HAST conditions. Other key performance parameters like filling and planarization over complex topography of an advanced dielectric material will be compared and analyzed for this approach against other liquid film deposition techniques.
{"title":"Producing Planarized Uniform Layer in Advanced Photosensitive Polyimide Over Complex Geometry for Fan Out PLP Applied with a Novel Nozzle-Less Spray Coating Technology","authors":"S. Erickson, Sanjay Malik","doi":"10.23919/IWLPC52010.2020.9375853","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375853","url":null,"abstract":"With growing demand for advanced computing systems and as personal handheld devices become more powerful, frontend manufacturers are required to reduce the physical footprint of and at the same time integrate more functionality into their chips. More I/O channels are packed into smaller areas than ever before in modern packages. The competing demands of increasing throughput and reducing costs makes the interconnection of these packages increasingly challenging. New methods to produce these high-density interconnections are required to meet these challenges. Chips are placed and connected both horizontally and vertically in 2.5D and 3D packaging. This created inherent topographical challenges for producing the interconnections. The industry's drive for cost reduction is building momentum toward more efficient and cost effective methods for creating the multi -layer high density interconnects. There are inherent topographical challenges associated with the growth of 2.5D and 3D packaging where chips are placed and interconnected horizontally and vertically. One critical area of interest is the formation of the passivation layer that enables connections between layers. Polyimides must be applied in a uniform layer to ensure that the inter-layer connections can properly be formed. Effectiveness of different film deposition methods is measured in terms of formation of uniform and void- free films to ensure intended mechanical and electrical integrity of the material is not compromised. Film deposition method can potentially influence not only film density but also polymer chain configuration that control key properties directly linked to the reliability of the material. While polarity of functional groups dictates moisture uptake, polymer chain configuration can control moisture permeability through the deposited film and its ability to act as corrosion barrier. We have previously reported creation of high -density vias printed in a dielectric film deposited by a revolutionary technique in the form of a novel nozzle-less ultrasonic spray technology. [1] This paper presents impact of such unique deposition method on key film properties like density and moisture permeability along with supporting reliability data under high temperature storage (HTS) and unbiased-HAST conditions. Other key performance parameters like filling and planarization over complex topography of an advanced dielectric material will be compared and analyzed for this approach against other liquid film deposition techniques.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122927493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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