Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375904
Kang Zhang, Kelvin Boh, Junqi Wei, T. Koh, Nuno Chen, Hannah Tang, Clinton Goh, Bridger Hoerner
Next-generation Under Bump Metallization (UBM) size reduction and increasing polymer thickness bring about thermomechanical benefits such as reduced low-k stress for advanced semiconductor packages. In addition, the adoption of fluorinated polymers provides low-k passivation which reduces signal delay and power consumption. However, these inflections at advanced nodes create new challenges for bump contact resistance ($mathrm{R}_{mathrm{C}}$) due to increased polymer outgassing and smaller via size. This paper describes an advanced pre-clean chamber and optimized pre-clean process condition developed to improve $mathrm{R}_{mathrm{C}}$ on various polymers. It is shown that the improved pre-clean efficiency results in significantly lower carbon, oxygen and fluorine contaminants at the Ti/Al interface, measured by TEM/EDX analysis. The $mathrm{R}_{mathrm{C}}$ values measured on a test vehicle with three-wire Kelvin test structures demonstrated a >60% lower $mathrm{R}_{mathrm{C}}$ and improved $mathrm{R}_{mathrm{C}}$ standard deviation. The new pre-clean chamber also enables higher throughput while maintaining a low wafer temperature for outgassing control.
{"title":"Advanced Preclean Chamber for Ubm/Rdl Contact Resistance Improvement in Advanced Node Packaging Application","authors":"Kang Zhang, Kelvin Boh, Junqi Wei, T. Koh, Nuno Chen, Hannah Tang, Clinton Goh, Bridger Hoerner","doi":"10.23919/IWLPC52010.2020.9375904","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375904","url":null,"abstract":"Next-generation Under Bump Metallization (UBM) size reduction and increasing polymer thickness bring about thermomechanical benefits such as reduced low-k stress for advanced semiconductor packages. In addition, the adoption of fluorinated polymers provides low-k passivation which reduces signal delay and power consumption. However, these inflections at advanced nodes create new challenges for bump contact resistance ($mathrm{R}_{mathrm{C}}$) due to increased polymer outgassing and smaller via size. This paper describes an advanced pre-clean chamber and optimized pre-clean process condition developed to improve $mathrm{R}_{mathrm{C}}$ on various polymers. It is shown that the improved pre-clean efficiency results in significantly lower carbon, oxygen and fluorine contaminants at the Ti/Al interface, measured by TEM/EDX analysis. The $mathrm{R}_{mathrm{C}}$ values measured on a test vehicle with three-wire Kelvin test structures demonstrated a >60% lower $mathrm{R}_{mathrm{C}}$ and improved $mathrm{R}_{mathrm{C}}$ standard deviation. The new pre-clean chamber also enables higher throughput while maintaining a low wafer temperature for outgassing control.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127957274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently we have developed novel polyimide adhesive sheet materials (PI sheet) which have advantages such as planarization, via-filling, low shrinkage (low stress) during curing and easy fabrication of multi-layer and cavity structures compared to spin-coating polyimide materials. The PI sheets are expected to be used in wafer level package (WLP) applications such as 5G telecommunication systems (5G) and Micro Electro Mechanical Systems (MEMS). To meet 5G and MEMS requirements, we recently have developed novel low-dielectric loss (low Df) and high mechanical properties PI sheets with good adhesion to Cu and polyimide layers on a substrate. We have achieved Df values of 0.003 and 0.007 at 20GHz for non-photosensitive (NP) PI sheet and photo-sensitive (PS) PI sheet, respectively. The use of low Df PI sheet as a redistribution layer can help realize low transmission loss due to low Df value itself and also to low conductor loss due to good adhesion to the smooth copper surface of the wiring.
{"title":"Development Of Low Dielectric Loss Polyimides And Fabrication Of Advanced Packagings For 5g ApplicationS","authors":"T. Fujiwara, Yoshiko Tatsuta, Kazuyuki Matsumura, Daisuke Kanamori, Hitoshi Araki, Akira Shimada, Masao Tomikawa","doi":"10.23919/IWLPC52010.2020.9375856","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375856","url":null,"abstract":"Recently we have developed novel polyimide adhesive sheet materials (PI sheet) which have advantages such as planarization, via-filling, low shrinkage (low stress) during curing and easy fabrication of multi-layer and cavity structures compared to spin-coating polyimide materials. The PI sheets are expected to be used in wafer level package (WLP) applications such as 5G telecommunication systems (5G) and Micro Electro Mechanical Systems (MEMS). To meet 5G and MEMS requirements, we recently have developed novel low-dielectric loss (low Df) and high mechanical properties PI sheets with good adhesion to Cu and polyimide layers on a substrate. We have achieved Df values of 0.003 and 0.007 at 20GHz for non-photosensitive (NP) PI sheet and photo-sensitive (PS) PI sheet, respectively. The use of low Df PI sheet as a redistribution layer can help realize low transmission loss due to low Df value itself and also to low conductor loss due to good adhesion to the smooth copper surface of the wiring.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126776121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375893
M. Letz, T. Gotschke, B. Hoppe, Markus Heiss, Matthias Jotz
In principle there exists a large variety of compositions for oxide glasses. Also a variety of hot forming processes is present for glasses, which allows near end shape processing. In particular thin glasses, directly drawn from a melt, are of interest as a substrate material for packaging of electronics with heterogeneous integration. One main reason seems to be economic manufacturing methods but also mechanic properties like stiffness, correlating to relatively large Youngs moduli, which is the basis for accurate manufacturing with single digit micrometer accuracy. The thermal expansion of glasses can in principle be tailored in a range from 2 ppm/K–12 ppm/K depending on the needs of particular applications. Structuring of glasses either with vias for IC packaging or in combination with cut-outs for fan-out embedding of active and passive components in the substrate layer are possible. Structuring methods which allow millions of vias and thousands of cut-outs in panel level formats are discussed. An efficient and economic metallization process with good adhesion and good electrical performance is a further step for commercializing structured glasses into packaging applications. High frequency applications like inclusion of antenna in package or high-speed digital applications with Gbit/s data rates give further demands on the properties of such structured glasses. In the current work we review the status of glasses for wafer- and panel level packaging. Glasses are available in a large variety; focusing and industrial standardization will speed up industrial readiness of glasses for electronic packaging.
{"title":"Glass in wafer- and panel-level packaging: Changes, challenges, hurdles and barriers","authors":"M. Letz, T. Gotschke, B. Hoppe, Markus Heiss, Matthias Jotz","doi":"10.23919/IWLPC52010.2020.9375893","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375893","url":null,"abstract":"In principle there exists a large variety of compositions for oxide glasses. Also a variety of hot forming processes is present for glasses, which allows near end shape processing. In particular thin glasses, directly drawn from a melt, are of interest as a substrate material for packaging of electronics with heterogeneous integration. One main reason seems to be economic manufacturing methods but also mechanic properties like stiffness, correlating to relatively large Youngs moduli, which is the basis for accurate manufacturing with single digit micrometer accuracy. The thermal expansion of glasses can in principle be tailored in a range from 2 ppm/K–12 ppm/K depending on the needs of particular applications. Structuring of glasses either with vias for IC packaging or in combination with cut-outs for fan-out embedding of active and passive components in the substrate layer are possible. Structuring methods which allow millions of vias and thousands of cut-outs in panel level formats are discussed. An efficient and economic metallization process with good adhesion and good electrical performance is a further step for commercializing structured glasses into packaging applications. High frequency applications like inclusion of antenna in package or high-speed digital applications with Gbit/s data rates give further demands on the properties of such structured glasses. In the current work we review the status of glasses for wafer- and panel level packaging. Glasses are available in a large variety; focusing and industrial standardization will speed up industrial readiness of glasses for electronic packaging.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132381870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375883
Robert Hillinger
AI, 5G, IoT, ADAS, AR/VR and other new applications is giving the semiconductor industry plenty of growth opportunities. With the adoption of these technologies the pressure is on, to increase performance. The industry is using the power advantages of lower technology nodes and Advanced Packaging to put increased functionality on a single small form-factor which makes production processes even more challenging. This advancements in semiconductor technology and added device complexity put additional pressure on monitoring and controlling Semiconductor packaging processes. The optimization of processes is a precondition for high reliability which is achieved by selecting appropriate materials and controlling critical process parameters. Currently Chip test, monitoring and control of packaging processes is widely done via optical-, displacement Sensors and Electrical Testing. Improved methods for process monitoring and failure identification are needed to maintain or improve the quality and yield of a packaging process. The physical force quantity causing a device failure may not be accessible to conventional measuring methods but is equally important to control and monitor production processes such as bonding, pick and place and encapsulation. Piezo dynamic force measurement technology allows force to be monitored and controlled with high resolution even at low forces. As a result, deviations can be detected early, errors avoided, and Semiconductor Advanced Packaging Equipment builders can achieve higher and more accurate machine performance. Semiconductor Manufacturing-Packing companies in the semiconductor industry benefit from higher process visibility, performance, lower quality cost and traceability of process data.
{"title":"Force Measurement with Piezo Electric Sensors in Advanced Packaging","authors":"Robert Hillinger","doi":"10.23919/IWLPC52010.2020.9375883","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375883","url":null,"abstract":"AI, 5G, IoT, ADAS, AR/VR and other new applications is giving the semiconductor industry plenty of growth opportunities. With the adoption of these technologies the pressure is on, to increase performance. The industry is using the power advantages of lower technology nodes and Advanced Packaging to put increased functionality on a single small form-factor which makes production processes even more challenging. This advancements in semiconductor technology and added device complexity put additional pressure on monitoring and controlling Semiconductor packaging processes. The optimization of processes is a precondition for high reliability which is achieved by selecting appropriate materials and controlling critical process parameters. Currently Chip test, monitoring and control of packaging processes is widely done via optical-, displacement Sensors and Electrical Testing. Improved methods for process monitoring and failure identification are needed to maintain or improve the quality and yield of a packaging process. The physical force quantity causing a device failure may not be accessible to conventional measuring methods but is equally important to control and monitor production processes such as bonding, pick and place and encapsulation. Piezo dynamic force measurement technology allows force to be monitored and controlled with high resolution even at low forces. As a result, deviations can be detected early, errors avoided, and Semiconductor Advanced Packaging Equipment builders can achieve higher and more accurate machine performance. Semiconductor Manufacturing-Packing companies in the semiconductor industry benefit from higher process visibility, performance, lower quality cost and traceability of process data.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375877
Sarah Parrish
What approaches are available for the flip of devices prior to die bond when the top wafer surface cannot be touched? Conventional 180 degree flip on a chip by chip basis during the die sort process requires rubber vacuum pick-up tools to touch both the top and bottom surfaces of device during the required transfers from one pick-up tool to another. However, for a growing number of applications ranging from medical devices, imaging sensors, MEMS, and bumped die used in flip chip applications, touching the sensitive top surface of a device is not desirable, while the need to flip the device remains. Factors to be evaluated in seeking a successful invert process without top surface contact include throughput, wear resistance of tooling, device and tooling material properties, and risk for top surface damage (yield). A pick and place process using an edge gripper instead of vacuum pick-up tip allowed for no contact of device surface but did not provide a robust device flip process due to imprecise device positioning. However, a non-surface contact approach to protect surface features was able to be achieved by using a radius/channel style pick-up tool to pick the die from the wafer and deposit onto a die inverter arm with vacuum surface contact pick-up tool to hold the device in place from the bottom with vacuum. This arm then rotated 180 degrees to place the device into a second radius/channel style pick-up tool, with the tool touching two of the top edges only. Based on the radius design of the channel style tools, the die protruded past the face of the tool, allowing it to be repicked by the main pick-up tool and then subsequently placed to the output. This non-contact approach was found to successfully protect the device surface during the flip. Future research will focus on improving precision of edge grippers so they may also be a potential solution, as well as the testing of the radius/channel pick-up tip approach for applicability with thin devices.
{"title":"Non-Surface Contact Approach for Device Flip","authors":"Sarah Parrish","doi":"10.23919/IWLPC52010.2020.9375877","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375877","url":null,"abstract":"What approaches are available for the flip of devices prior to die bond when the top wafer surface cannot be touched? Conventional 180 degree flip on a chip by chip basis during the die sort process requires rubber vacuum pick-up tools to touch both the top and bottom surfaces of device during the required transfers from one pick-up tool to another. However, for a growing number of applications ranging from medical devices, imaging sensors, MEMS, and bumped die used in flip chip applications, touching the sensitive top surface of a device is not desirable, while the need to flip the device remains. Factors to be evaluated in seeking a successful invert process without top surface contact include throughput, wear resistance of tooling, device and tooling material properties, and risk for top surface damage (yield). A pick and place process using an edge gripper instead of vacuum pick-up tip allowed for no contact of device surface but did not provide a robust device flip process due to imprecise device positioning. However, a non-surface contact approach to protect surface features was able to be achieved by using a radius/channel style pick-up tool to pick the die from the wafer and deposit onto a die inverter arm with vacuum surface contact pick-up tool to hold the device in place from the bottom with vacuum. This arm then rotated 180 degrees to place the device into a second radius/channel style pick-up tool, with the tool touching two of the top edges only. Based on the radius design of the channel style tools, the die protruded past the face of the tool, allowing it to be repicked by the main pick-up tool and then subsequently placed to the output. This non-contact approach was found to successfully protect the device surface during the flip. Future research will focus on improving precision of edge grippers so they may also be a potential solution, as well as the testing of the radius/channel pick-up tip approach for applicability with thin devices.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375882
Jay Chao, Rong Zhang, David Grimes, Kail Shim, T. Do, Yijia Ma, R. Trichur
Wafer level encapsulation has become increasingly important to build up components for mobile and high-performance computing applications. Ranging from system-in-package and antenna modules to high band-width memory device, many of those wafer-level applications demand new features from encapsulant materials. Besides to provide mechanical protection, new wafer-level encapsulants are preferred to bring in extra features: a) reducing package warpage during wafer-level processing; b) being EU REACH compliant, c) showing excellent flowability for trench-fill or gap-fill. In our new material development, these new features can be achieved in a new type of filled epoxy system. The new class of encapsulants maintains high glass transition temperature (Tg), at the same level of typical semiconductor encapsulants, while demonstrating low-warpage during the wafer-level process, an estimation of more than 50% improvement from typical encapsulants. Owing to the use of fine fillers and new resin chemistry, fine gap-filling is possible. Combination of low-warpage and good flowability allows us to serve better in wafer-level applications. Some case studies will be discussed, including: 1) using liquid compression molding (LCM) process to encapsulate the wafers that have built-in trench-gaps, fine-gaps, or solder-bumps. 2) using stencil printing process to encapsulate trenched wafers. In both process routes, low-warpage, void-free gap-fill can be achieved from the packages. Moreover, the encapsulated test-vehicles passed JEDEC MSL-1 reliability conditions. The results demonstrated that this new wafer-level encapsulants have the potential to meet the growing demands from various wafer-level applications.
{"title":"Low -Warpage Encapsulants for Wafer Level Packaging","authors":"Jay Chao, Rong Zhang, David Grimes, Kail Shim, T. Do, Yijia Ma, R. Trichur","doi":"10.23919/IWLPC52010.2020.9375882","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375882","url":null,"abstract":"Wafer level encapsulation has become increasingly important to build up components for mobile and high-performance computing applications. Ranging from system-in-package and antenna modules to high band-width memory device, many of those wafer-level applications demand new features from encapsulant materials. Besides to provide mechanical protection, new wafer-level encapsulants are preferred to bring in extra features: a) reducing package warpage during wafer-level processing; b) being EU REACH compliant, c) showing excellent flowability for trench-fill or gap-fill. In our new material development, these new features can be achieved in a new type of filled epoxy system. The new class of encapsulants maintains high glass transition temperature (Tg), at the same level of typical semiconductor encapsulants, while demonstrating low-warpage during the wafer-level process, an estimation of more than 50% improvement from typical encapsulants. Owing to the use of fine fillers and new resin chemistry, fine gap-filling is possible. Combination of low-warpage and good flowability allows us to serve better in wafer-level applications. Some case studies will be discussed, including: 1) using liquid compression molding (LCM) process to encapsulate the wafers that have built-in trench-gaps, fine-gaps, or solder-bumps. 2) using stencil printing process to encapsulate trenched wafers. In both process routes, low-warpage, void-free gap-fill can be achieved from the packages. Moreover, the encapsulated test-vehicles passed JEDEC MSL-1 reliability conditions. The results demonstrated that this new wafer-level encapsulants have the potential to meet the growing demands from various wafer-level applications.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121599336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375862
Allison T. Osmanson, Y. Kim, H. Madanipour, Mohsen Tajedini, C. Kim, P. Thompson, Q. Cherr, L. Nguyen
Electromigration (EM) induced failure is inevitable in wafer-level chip scale package microelectronic packages (WCSP), especially with the implementation of lead-free solders. Many factors contribute to EM failure such as joule heating and current crowding. EM can induce void formation, which can eventually lead to open-circuit failure. Due to its nature, EM is a critical failure concern to the microelectronic industry and can be influenced by current conditions. This study examines the failure mechanisms in solder joints implemented in WCSP packages in Direct Current (DC) and DC-pulse current conditions with varying Duty Factors (DF). DF represents the on-off time for DC to flow through the device under test (DUT). Further, a transient simulative study using finite element method (FEM) explores the failure mechanism and investigates the stress development with DC and DF conditions. Findings suggested that a lower duty factor yielded longer time to failure (TTF). Meanwhile, higher pulsed DC DF yielded a lower TTF than DC. This study aims to explain the failure mechanism with each DF. This study aims to explain this phenomenon and suggests the need for further exploration.
{"title":"Current Crowding and Stress Effects in WCSP Solder Interconnects: A Simulative and Practical Study about the Effects of Major Electromigration Failure Mechanisms in DC and Pulsed-DC Conditions","authors":"Allison T. Osmanson, Y. Kim, H. Madanipour, Mohsen Tajedini, C. Kim, P. Thompson, Q. Cherr, L. Nguyen","doi":"10.23919/IWLPC52010.2020.9375862","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375862","url":null,"abstract":"Electromigration (EM) induced failure is inevitable in wafer-level chip scale package microelectronic packages (WCSP), especially with the implementation of lead-free solders. Many factors contribute to EM failure such as joule heating and current crowding. EM can induce void formation, which can eventually lead to open-circuit failure. Due to its nature, EM is a critical failure concern to the microelectronic industry and can be influenced by current conditions. This study examines the failure mechanisms in solder joints implemented in WCSP packages in Direct Current (DC) and DC-pulse current conditions with varying Duty Factors (DF). DF represents the on-off time for DC to flow through the device under test (DUT). Further, a transient simulative study using finite element method (FEM) explores the failure mechanism and investigates the stress development with DC and DF conditions. Findings suggested that a lower duty factor yielded longer time to failure (TTF). Meanwhile, higher pulsed DC DF yielded a lower TTF than DC. This study aims to explain the failure mechanism with each DF. This study aims to explain this phenomenon and suggests the need for further exploration.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117304907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375880
B. Matuskova, B. Povazay, R. Holly, F. Bügelsack, T. Zenger, T. Uhrmann, B. Thallner
Moving from monolithic scaling to the second (2D) and to the third dimension (3D) is becoming increasingly important within industry. In the last years heterogeneous and chiplet integration, utilizing advanced packaging technologies, has increased in complexity as well as in variability. Higher performance, wider bandwidth and lower power consumption and space requirements drive the approach toward 3D integration, whereas the need of finer RDL line/spacing as well as smaller μ-bumps and μ-pillars critical dimension tighten integration design rules at the package and substrate level. Individual chiplet's I/O bumps and interconnects pitch scaling nowadays moves towards 2/2μm L/S. Although the flexible re-integration of larger dies from smaller chiplets, from various technology nodes to partitioned dies has shown numerous advantages over monolithic SoC technologies with larger freedom of design, this approach shifts the complexity into the integration and with it into the lithographic patterning processes. In this work a profound evaluation of common advanced packaging high resolution, thin and thick resists for RDL & μ-bump/μ-pillar manufacturing is presented, utilizing maskless exposure to demonstrate its patterning performance. Resolution tests, focal position & exposure matrices, including resist sidewall profiles are discussed in view of the 2/2μm L/S requirements for heterogeneous integration. Furthermore, the high-speed digital processing meets the needs for design flexibility and scalability for a wide range of packaging technologies by enabling both, die- and wafer-level designs, fast tape-out changes together with sub-μm adaptability.
{"title":"Maskless Lithography Optimized for Heterogeneous and Chiplet Integration","authors":"B. Matuskova, B. Povazay, R. Holly, F. Bügelsack, T. Zenger, T. Uhrmann, B. Thallner","doi":"10.23919/IWLPC52010.2020.9375880","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375880","url":null,"abstract":"Moving from monolithic scaling to the second (2D) and to the third dimension (3D) is becoming increasingly important within industry. In the last years heterogeneous and chiplet integration, utilizing advanced packaging technologies, has increased in complexity as well as in variability. Higher performance, wider bandwidth and lower power consumption and space requirements drive the approach toward 3D integration, whereas the need of finer RDL line/spacing as well as smaller μ-bumps and μ-pillars critical dimension tighten integration design rules at the package and substrate level. Individual chiplet's I/O bumps and interconnects pitch scaling nowadays moves towards 2/2μm L/S. Although the flexible re-integration of larger dies from smaller chiplets, from various technology nodes to partitioned dies has shown numerous advantages over monolithic SoC technologies with larger freedom of design, this approach shifts the complexity into the integration and with it into the lithographic patterning processes. In this work a profound evaluation of common advanced packaging high resolution, thin and thick resists for RDL & μ-bump/μ-pillar manufacturing is presented, utilizing maskless exposure to demonstrate its patterning performance. Resolution tests, focal position & exposure matrices, including resist sidewall profiles are discussed in view of the 2/2μm L/S requirements for heterogeneous integration. Furthermore, the high-speed digital processing meets the needs for design flexibility and scalability for a wide range of packaging technologies by enabling both, die- and wafer-level designs, fast tape-out changes together with sub-μm adaptability.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129609492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375898
B. Kasprowicz, Siamak Mogharrabi, Martin Carrier, Andrew G. Zanzal, Patrick Reynolds, Corey Shay, K. Best
In the next few years, advanced process technologies in advanced packaging fabs will migrate rapidly to reduction lithography to achieve 2/2 RDL and beyond. Reticle enhancement techniques, such as Optical Proximity Correction (OPC) may be required in multiple reticle layers to provide sufficient process latitude for high volume manufacturing. However, a challenge in the manufacturing of OPC reticles is the lack of a precise specifications for defect inspection with respect to the printability on wafers [1]. In this paper, the printability of reticle defects for 2/2 micrometers Redistribution Layer (RDL) design rule are studied via i-line resist process. The reticle defect printability is determined by considering the wafer process critical dimension (CD) variability. In the experiment, an i-line 2x reduction stepper with 0.1 NA imaging lens was used to expose the programmed defect reticle. The resist CD response to the reticle defect area is measured under a variety of process conditions, i.e., different exposure dose or focusThe programmed defect reticles consisted of both Clear and Dark Field polarities comprising of 2/2 design rules will be used for the printability study. Defects such as intrusions and protrusions at various sizes on RDL patterns, have been characterized. Defect disposition comparing reticle to designed programmed defects to those without will be shown as well as the impact of the defect on patterning performance. Finally, the allowable reticle defect requirement is assessed where the printable reticle defect size is tied to the wafer process specifications and the actual wafer process CD controllability. The influence of the reticle manufacturing processes on wafer patterning performance is examined. Through this comparison, insights into target specifications (MTT, CDU, defects) for advanced RDL reticles can be derived while balancing cost tradeoffs.
{"title":"Defect Printability for 2/2 RDL and The Impact of Advanced Reticle Processes","authors":"B. Kasprowicz, Siamak Mogharrabi, Martin Carrier, Andrew G. Zanzal, Patrick Reynolds, Corey Shay, K. Best","doi":"10.23919/IWLPC52010.2020.9375898","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375898","url":null,"abstract":"In the next few years, advanced process technologies in advanced packaging fabs will migrate rapidly to reduction lithography to achieve 2/2 RDL and beyond. Reticle enhancement techniques, such as Optical Proximity Correction (OPC) may be required in multiple reticle layers to provide sufficient process latitude for high volume manufacturing. However, a challenge in the manufacturing of OPC reticles is the lack of a precise specifications for defect inspection with respect to the printability on wafers [1]. In this paper, the printability of reticle defects for 2/2 micrometers Redistribution Layer (RDL) design rule are studied via i-line resist process. The reticle defect printability is determined by considering the wafer process critical dimension (CD) variability. In the experiment, an i-line 2x reduction stepper with 0.1 NA imaging lens was used to expose the programmed defect reticle. The resist CD response to the reticle defect area is measured under a variety of process conditions, i.e., different exposure dose or focusThe programmed defect reticles consisted of both Clear and Dark Field polarities comprising of 2/2 design rules will be used for the printability study. Defects such as intrusions and protrusions at various sizes on RDL patterns, have been characterized. Defect disposition comparing reticle to designed programmed defects to those without will be shown as well as the impact of the defect on patterning performance. Finally, the allowable reticle defect requirement is assessed where the printable reticle defect size is tied to the wafer process specifications and the actual wafer process CD controllability. The influence of the reticle manufacturing processes on wafer patterning performance is examined. Through this comparison, insights into target specifications (MTT, CDU, defects) for advanced RDL reticles can be derived while balancing cost tradeoffs.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116043052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-13DOI: 10.23919/IWLPC52010.2020.9375852
Matthias Fettke, Timo Kubsch, Vinith Bejugam, Alexander Frick, Andrej Kolbasow, Sergej Walter, T. Teutsch
The current study aims at presenting a cost-effective, facile and novel interconnection approach that employs a unique solder ball jetting process (SB2) for stack formations. Conventional methodologies for bridging boards, chips or filling VIAs can be substituted by a solder ball stacking process. In the SB2 process, a bond-head singulates solder spheres which are then liquefied by laser energy and expelled onto a target using nitrogen pressure. Multiple solder droplets could be dispensed at the same location before subsequent translocation of the bond-head. Continued jetting outlined herein could be used to form single or multiple columns (colonnade), or even fill VIA structures. The challenge is to select a parametric window which prevents disintegration of solder stacks at the interface of boards or chips due to parasitic air inclusions or other factors [1]. The process window for three different stacks of solder spheres with varying diameters and aspect ratios (> > 5) are presented and discussed in this work. This work highlights possible combinations of solder stack configurations regarding the size and number of solder balls per stack and the resulting geometrical characteristics. The metallurgical properties of the solder interface were inspected by cross sectional analysis and X-ray. The mechanical strength and corresponding fracture modes were analyzed with a shear test unit and an optical microscope. The vertical offsets associated with column heights were examined with a 3D profilometer. An FEM simulation was performed, confirming and supplementing the experimental findings. Test vehicles pertaining to board-to-board or chip to chip connections using solder ball stacking are demonstrated. As an evaluation material, Si Chips with AlNiAu metallic pads were populated by SAC_305 (Sn 96.5%, Ag 3.0%, Cu 0.5%) stacked solder ball columns. The chip-to-chip assembly was accomplished additionally using a laser-assisted bonding process (LAB). To demonstrate the wide range of applicability and opportunities for column design, low melting-point solder spheres were placed on the corresponding chip to form a solder interface with the pre-processed columns/stacks during the flip-chip process. The ensuing colonnade hybridswere used to support conventional bonding in standard reflow ovens. Finally, future prospects of intended reliability and stability studies are elucidated as well as the opportunity to use this process technique for filling VIAs.
目前的研究旨在提出一种经济、简便、新颖的互连方法，该方法采用独特的焊接球喷射工艺(SB2)来形成堆叠。桥接电路板、芯片或填充过孔的传统方法可以用焊料球堆积工艺代替。在SB2工艺中，一个键头模拟焊接球，然后用激光能量液化焊接球，用氮压将其排出靶上。多个焊锡液滴可以在同一位置被分配，然后再转移粘结头。此处概述的持续喷射可用于形成单个或多个柱(柱廊)，甚至填充VIA结构。挑战在于选择一个参数窗口，以防止由于寄生空气夹杂物或其他因素导致电路板或芯片界面上的焊料堆解体。提出并讨论了具有不同直径和长宽比(> > 5)的三种不同焊球堆的工艺窗口。这项工作强调了关于每堆锡球的大小和数量以及由此产生的几何特性的锡堆配置的可能组合。采用横截面分析和x射线检测焊点界面的冶金性能。利用剪切试验装置和光学显微镜对其力学强度和相应的断裂模式进行了分析。用三维轮廓仪检查与柱高度相关的垂直偏移量。进行了有限元模拟，验证和补充了实验结果。演示了与使用焊料球堆叠的板对板或芯片对芯片连接有关的测试车辆。作为评价材料，用SAC_305 (Sn 96.5%， Ag 3.0%， Cu 0.5%)堆积锡球柱填充带有AlNiAu金属衬垫的Si芯片。此外，还使用激光辅助键合工艺(LAB)完成了芯片到芯片的组装。为了证明柱设计的广泛适用性和机会，在倒装过程中，将低熔点焊锡球放置在相应的芯片上，与预处理的柱/堆形成焊锡界面。随后的柱体杂化用于支持标准回流炉中的常规粘合。最后，阐明了未来可靠性和稳定性研究的前景，以及使用该工艺技术填充过孔的机会。
{"title":"A Study About Facile Interconnect Formations Involving SB2-JET Solder Ball Stacking and Colonnade Patterning in Hybrid Package Architectures","authors":"Matthias Fettke, Timo Kubsch, Vinith Bejugam, Alexander Frick, Andrej Kolbasow, Sergej Walter, T. Teutsch","doi":"10.23919/IWLPC52010.2020.9375852","DOIUrl":"https://doi.org/10.23919/IWLPC52010.2020.9375852","url":null,"abstract":"The current study aims at presenting a cost-effective, facile and novel interconnection approach that employs a unique solder ball jetting process (SB2) for stack formations. Conventional methodologies for bridging boards, chips or filling VIAs can be substituted by a solder ball stacking process. In the SB2 process, a bond-head singulates solder spheres which are then liquefied by laser energy and expelled onto a target using nitrogen pressure. Multiple solder droplets could be dispensed at the same location before subsequent translocation of the bond-head. Continued jetting outlined herein could be used to form single or multiple columns (colonnade), or even fill VIA structures. The challenge is to select a parametric window which prevents disintegration of solder stacks at the interface of boards or chips due to parasitic air inclusions or other factors [1]. The process window for three different stacks of solder spheres with varying diameters and aspect ratios (> > 5) are presented and discussed in this work. This work highlights possible combinations of solder stack configurations regarding the size and number of solder balls per stack and the resulting geometrical characteristics. The metallurgical properties of the solder interface were inspected by cross sectional analysis and X-ray. The mechanical strength and corresponding fracture modes were analyzed with a shear test unit and an optical microscope. The vertical offsets associated with column heights were examined with a 3D profilometer. An FEM simulation was performed, confirming and supplementing the experimental findings. Test vehicles pertaining to board-to-board or chip to chip connections using solder ball stacking are demonstrated. As an evaluation material, Si Chips with AlNiAu metallic pads were populated by SAC_305 (Sn 96.5%, Ag 3.0%, Cu 0.5%) stacked solder ball columns. The chip-to-chip assembly was accomplished additionally using a laser-assisted bonding process (LAB). To demonstrate the wide range of applicability and opportunities for column design, low melting-point solder spheres were placed on the corresponding chip to form a solder interface with the pre-processed columns/stacks during the flip-chip process. The ensuing colonnade hybridswere used to support conventional bonding in standard reflow ovens. Finally, future prospects of intended reliability and stability studies are elucidated as well as the opportunity to use this process technique for filling VIAs.","PeriodicalId":192698,"journal":{"name":"2020 International Wafer Level Packaging Conference (IWLPC)","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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