Terminal devices (TDs) connect to networks through access points (APs) integrated into the edge server. This provides a prerequisite for TDs to upload tasks to cloud data centers or offload them to edge servers for execution. In this process, signal coverage, data transmission, and task execution consume energy, and the energy consumption of signal coverage increases sharply as the radius increases. Lower power leads to less energy consumption in a given time segment. Thus, power control for APs is essential for reducing energy consumption. Our objective is to determine the power assignment for each AP with same capacity constraints such that all TDs are covered, and the total power is minimized. We define this problem as a minimum power capacitated cover (MPCC) problem and present a minimum local ratio (MLR) power control approach for this problem to obtain accurate results in polynomial time. Power assignments are chosen in a sequence of rounds. In each round, we choose the power assignment that minimizes the ratio of its power to the number of currently uncovered TDs it contains. In the event of a tie, we pick an arbitrary power assignment that achieves the minimum ratio. We continue choosing power assignments until all TDs are covered. Finally, various experiments verify that this method can outperform another greedy-based way.
{"title":"A Local-Ratio-Based Power Control Approach for Capacitated Access Points in Mobile Edge Computing","authors":"Qinghui Zhang, Weidong Li, Qian Su, Xuejie Zhang","doi":"10.1145/3546000.3546027","DOIUrl":"https://doi.org/10.1145/3546000.3546027","url":null,"abstract":"Terminal devices (TDs) connect to networks through access points (APs) integrated into the edge server. This provides a prerequisite for TDs to upload tasks to cloud data centers or offload them to edge servers for execution. In this process, signal coverage, data transmission, and task execution consume energy, and the energy consumption of signal coverage increases sharply as the radius increases. Lower power leads to less energy consumption in a given time segment. Thus, power control for APs is essential for reducing energy consumption. Our objective is to determine the power assignment for each AP with same capacity constraints such that all TDs are covered, and the total power is minimized. We define this problem as a minimum power capacitated cover (MPCC) problem and present a minimum local ratio (MLR) power control approach for this problem to obtain accurate results in polynomial time. Power assignments are chosen in a sequence of rounds. In each round, we choose the power assignment that minimizes the ratio of its power to the number of currently uncovered TDs it contains. In the event of a tie, we pick an arbitrary power assignment that achieves the minimum ratio. We continue choosing power assignments until all TDs are covered. Finally, various experiments verify that this method can outperform another greedy-based way.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131420211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaobin Zong, Yu-feng Mao, Zhaocheng Sun, Lei Kou, Y. Zheng, Tiejun Li
The research on track planning and obstacle avoidance methods of wave glider is an indispensable ability for its smooth work in the ocean. As a real-time track planning and obstacle avoidance algorithm, artificial potential field algorithm has attracted extensive attention. Aiming at the problem that the target point can not be reached in the traditional artificial potential field algorithm, the distance factor between the wave glider and the target point is introduced into the repulsive potential field; The relative velocity potential field function is introduced and the influence of velocity potential field is enhanced to solve the threat of dynamic obstacles to wave gliders. Then, based on the motion characteristics of wave gliders, the influence of stable waves in a certain range on track planning and obstacle avoidance is analyzed. Finally, the simulation analysis is carried out. The simulation results show that this method has good track planning and obstacle avoidance effect, and the generated path is smooth. Fixed the problem of not being able to reach the target.
{"title":"Track planning and obstacle avoidance of wave glider based on improved artificial potential field algorithm","authors":"Xiaobin Zong, Yu-feng Mao, Zhaocheng Sun, Lei Kou, Y. Zheng, Tiejun Li","doi":"10.1145/3546000.3546033","DOIUrl":"https://doi.org/10.1145/3546000.3546033","url":null,"abstract":"The research on track planning and obstacle avoidance methods of wave glider is an indispensable ability for its smooth work in the ocean. As a real-time track planning and obstacle avoidance algorithm, artificial potential field algorithm has attracted extensive attention. Aiming at the problem that the target point can not be reached in the traditional artificial potential field algorithm, the distance factor between the wave glider and the target point is introduced into the repulsive potential field; The relative velocity potential field function is introduced and the influence of velocity potential field is enhanced to solve the threat of dynamic obstacles to wave gliders. Then, based on the motion characteristics of wave gliders, the influence of stable waves in a certain range on track planning and obstacle avoidance is analyzed. Finally, the simulation analysis is carried out. The simulation results show that this method has good track planning and obstacle avoidance effect, and the generated path is smooth. Fixed the problem of not being able to reach the target.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114247242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hardware processors and optimization for secure operations in embedded devices have been a research hotspot in recent years. To full use of the limited computing and storage resources in embedded devices, it is necessary to explore the design space of software and hardware architectures in the early stage of SoC design. Therefore, SystemC-based electronic system-level (ESL) simulators are very useful for fast hardware modeling and verification. In this paper, we propose and design a SystemC-based cryptographic SoC virtual prototyping (Crypto-SoC VP) to speed up function and performance simulation of embedded security devices. We use RISC-V Crypto-Benchmark to analyze the simulation performance of the Crypto-SoC VP. SM4 crypto-accelerator with different hardware and software modes is also integrated in this VP. The experimental results show the efficiency of our design. The simulation speed on our virtual prototyping is over 50 times that of the traditional RTL simulation, while the simulation difference is only about 5%.
{"title":"High-Performance Cryptographic SoC Virtual Prototyping Platform Based on RISC-V VP","authors":"Junwei Wu, Xin Zheng, Shaofen Zeng, Huaien Gao, Xiaoming Xiong","doi":"10.1145/3546000.3546013","DOIUrl":"https://doi.org/10.1145/3546000.3546013","url":null,"abstract":"Hardware processors and optimization for secure operations in embedded devices have been a research hotspot in recent years. To full use of the limited computing and storage resources in embedded devices, it is necessary to explore the design space of software and hardware architectures in the early stage of SoC design. Therefore, SystemC-based electronic system-level (ESL) simulators are very useful for fast hardware modeling and verification. In this paper, we propose and design a SystemC-based cryptographic SoC virtual prototyping (Crypto-SoC VP) to speed up function and performance simulation of embedded security devices. We use RISC-V Crypto-Benchmark to analyze the simulation performance of the Crypto-SoC VP. SM4 crypto-accelerator with different hardware and software modes is also integrated in this VP. The experimental results show the efficiency of our design. The simulation speed on our virtual prototyping is over 50 times that of the traditional RTL simulation, while the simulation difference is only about 5%.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115469970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Data is encrypted using digital signature technology, which is a crucial step to ensure information security. An SoC with encryption ensures the security of data transmission. The previous SoC design method is to develop hardware first and then develop software, and it is difficult to achieve software and hardware co-design. Therefore, we propose a virtual prototype platform to solve this problem. With the help of SystemC and gem5, we successfully built a virtual prototype platform and conducted simulation experiments through this virtual prototype platform. The experiment results show that the proposed method realizes the software and hardware co-design. In addition, the SystemC cycle-accurate model used in the virtual prototype platform is converted into an RTL model by means of translator conversion, and the experimental results of the virtual prototype platform are compared and verified. The proposed virtual platform to develop and verify SoC models will reduce simulation time. 1
{"title":"A Digital Signature Virtual Platform Based on Hardware-Software Co-Design","authors":"Feng-Ming Lin, Shuting Cai, Heming Liu","doi":"10.1145/3546000.3546016","DOIUrl":"https://doi.org/10.1145/3546000.3546016","url":null,"abstract":"Data is encrypted using digital signature technology, which is a crucial step to ensure information security. An SoC with encryption ensures the security of data transmission. The previous SoC design method is to develop hardware first and then develop software, and it is difficult to achieve software and hardware co-design. Therefore, we propose a virtual prototype platform to solve this problem. With the help of SystemC and gem5, we successfully built a virtual prototype platform and conducted simulation experiments through this virtual prototype platform. The experiment results show that the proposed method realizes the software and hardware co-design. In addition, the SystemC cycle-accurate model used in the virtual prototype platform is converted into an RTL model by means of translator conversion, and the experimental results of the virtual prototype platform are compared and verified. The proposed virtual platform to develop and verify SoC models will reduce simulation time. 1","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122632361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the widely use of new energy vehicles, charging safety has increasingly become a topic of public concern. Based on the analysis of the factors which affect charging safety, this paper proposes to build a charging safety monitoring platform to realize real-time charging monitoring and improve the charging safety of new energy vehicles. Based on DTW time clustering monitoring model and temperature management model, the platform monitors the abnormal conditions of temperature, electric quantity and voltage, and realizes the monitoring and early warning of abnormal conditions such as no power charging, temperature mutation, current abnormality, instantaneous overvoltage / overcurrent.
{"title":"Research on new energy vehicle charging safety monitoring platform based on DTW time clustering algorithm","authors":"Chao Liu, R. Zang, Ying Xin, Yu Wang","doi":"10.1145/3546000.3546032","DOIUrl":"https://doi.org/10.1145/3546000.3546032","url":null,"abstract":"With the widely use of new energy vehicles, charging safety has increasingly become a topic of public concern. Based on the analysis of the factors which affect charging safety, this paper proposes to build a charging safety monitoring platform to realize real-time charging monitoring and improve the charging safety of new energy vehicles. Based on DTW time clustering monitoring model and temperature management model, the platform monitors the abnormal conditions of temperature, electric quantity and voltage, and realizes the monitoring and early warning of abnormal conditions such as no power charging, temperature mutation, current abnormality, instantaneous overvoltage / overcurrent.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131392120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bin Huang, Anjun Liu, Min Tian, Jingshan Pan, Yu Zhang
The open-source fluid dynamics software Palabos based on the Lattice Boltzmann Method (LBM) has been widely used in porous media, biological fluids, free interfaces and other physical problems. Palabos has excellent MPI parallel performance and can complete large scale computation of computational fluid dynamics. To realize the heterogeneous parallelism of Palabos, we test the performance of Palabos on a large-scale simulation on a general-purpose cluster at first. The experimental results show that Palabos has a good performance in 16000 MPI processes. Then, we designed a CUDA parallel optimization algorithm for the case of cavity flow according to address mapping and shared memory optimization. Numerical experiments results show that the speedup ratio can achieve about a 1.5x acceleration ratio when the number of the grid is 512×512×512.
{"title":"Parallel Performance and Optimization of the Lattice Boltzmann Method Software Palabos Using CUDA","authors":"Bin Huang, Anjun Liu, Min Tian, Jingshan Pan, Yu Zhang","doi":"10.1145/3546000.3546014","DOIUrl":"https://doi.org/10.1145/3546000.3546014","url":null,"abstract":"The open-source fluid dynamics software Palabos based on the Lattice Boltzmann Method (LBM) has been widely used in porous media, biological fluids, free interfaces and other physical problems. Palabos has excellent MPI parallel performance and can complete large scale computation of computational fluid dynamics. To realize the heterogeneous parallelism of Palabos, we test the performance of Palabos on a large-scale simulation on a general-purpose cluster at first. The experimental results show that Palabos has a good performance in 16000 MPI processes. Then, we designed a CUDA parallel optimization algorithm for the case of cavity flow according to address mapping and shared memory optimization. Numerical experiments results show that the speedup ratio can achieve about a 1.5x acceleration ratio when the number of the grid is 512×512×512.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123716292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chenyu Huang, Huaien Gao, Yongfeng Zhong, Shuting Cai
With the continuous development of chip design technology, many chip description languages continuously emerge. Both Verilog and SystemC play an important role in chip description. Verilog is a widely used hardware description language that can be used in multiple stages of the hardware design process, including modeling, synthesis, and simulation. At the same time, to shorten the design cycle of chips, it has become a trend to use SystemC for hardware design and modeling. Therefore, we need to this end to convert between the two, namely Verilog And SystemC(VASC), is proposed. Experiments show that, compared to existing open-source tools, the VASC has excellent accuracy and faster compilation speed.
随着芯片设计技术的不断发展，许多芯片描述语言不断涌现。Verilog和SystemC在芯片描述中都起着重要的作用。Verilog是一种广泛使用的硬件描述语言，可用于硬件设计过程的多个阶段，包括建模、综合和仿真。同时，为了缩短芯片的设计周期，使用SystemC进行硬件设计和建模已成为一种趋势。因此，我们需要为此在两者之间进行转换，即Verilog And SystemC(VASC)，被提出。实验表明，与现有的开源工具相比，VASC具有良好的准确性和更快的编译速度。
{"title":"A High-Performance Bidirectional Compiler for Conversion Between SystemC and Verilog","authors":"Chenyu Huang, Huaien Gao, Yongfeng Zhong, Shuting Cai","doi":"10.1145/3546000.3546019","DOIUrl":"https://doi.org/10.1145/3546000.3546019","url":null,"abstract":"With the continuous development of chip design technology, many chip description languages continuously emerge. Both Verilog and SystemC play an important role in chip description. Verilog is a widely used hardware description language that can be used in multiple stages of the hardware design process, including modeling, synthesis, and simulation. At the same time, to shorten the design cycle of chips, it has become a trend to use SystemC for hardware design and modeling. Therefore, we need to this end to convert between the two, namely Verilog And SystemC(VASC), is proposed. Experiments show that, compared to existing open-source tools, the VASC has excellent accuracy and faster compilation speed.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125084152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Text implication recognition aims to judge the semantic and logical relationship between two paragraphs of text. The reasoning process involves syntactic analysis, vocabulary understanding, logical reasoning, social experience, and common sense. It is a way to judge whether the computer is to a certain extent. The challenging research task of "understanding" text semantics is also one of the more important benchmark tasks in the field of natural language processing. It is found that in the past ten years, the total number of publications in this field has been increasing year by year, and the popularity is also increasing. At present, there are mainly text implication relationship recognition methods based on similarity, text implication relationship recognition methods based on alignment, and deep neural networks. The textual implication relationship recognition method. This article summarizes the different methods.
{"title":"Research on Recognition Method of Textual Implication","authors":"Chenglong Wang, Chunyang Wang, Huimin Li, Tong Liu, Shuang Guo","doi":"10.1145/3546000.3546004","DOIUrl":"https://doi.org/10.1145/3546000.3546004","url":null,"abstract":"Text implication recognition aims to judge the semantic and logical relationship between two paragraphs of text. The reasoning process involves syntactic analysis, vocabulary understanding, logical reasoning, social experience, and common sense. It is a way to judge whether the computer is to a certain extent. The challenging research task of \"understanding\" text semantics is also one of the more important benchmark tasks in the field of natural language processing. It is found that in the past ten years, the total number of publications in this field has been increasing year by year, and the popularity is also increasing. At present, there are mainly text implication relationship recognition methods based on similarity, text implication relationship recognition methods based on alignment, and deep neural networks. The textual implication relationship recognition method. This article summarizes the different methods.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125773607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaoxiong Lu, J. Zhang, Kai Chen, Mini Wu, Qingxue Li, Xiaomeng Yu
The research of power equipment defect detection based on image feature has become a hot issue nowadays. In order to solve the problems of low efficiency and accuracy in traditional power equipment defect detection methods, a defect detection method of power metering equipment based on image deep learning is proposed in this work. We train the deep feature learning network model and obtain the optimal solution of network weights in right of training. The association rules are designed and the defect detection mechanism is designed in combination with the collected meter reading dataset. Based on the designed deep network model, defects are identified with the preprocessed images. In the meantime, in order to reduce the power consumption and time delay of data transmission in the process of defect recognition, we introduce the idea of edge computing, so that part of the defect recognition tasks can realize end-to-end intelligence while taking images. Experimental results show that the proposed method can improve defect detection capability and guarantee the normal operation of power metering equipment largely.
{"title":"Explore Deep Feature Learning to Power Equipment Monitoring and Defect Detection","authors":"Xiaoxiong Lu, J. Zhang, Kai Chen, Mini Wu, Qingxue Li, Xiaomeng Yu","doi":"10.1145/3546000.3546022","DOIUrl":"https://doi.org/10.1145/3546000.3546022","url":null,"abstract":"The research of power equipment defect detection based on image feature has become a hot issue nowadays. In order to solve the problems of low efficiency and accuracy in traditional power equipment defect detection methods, a defect detection method of power metering equipment based on image deep learning is proposed in this work. We train the deep feature learning network model and obtain the optimal solution of network weights in right of training. The association rules are designed and the defect detection mechanism is designed in combination with the collected meter reading dataset. Based on the designed deep network model, defects are identified with the preprocessed images. In the meantime, in order to reduce the power consumption and time delay of data transmission in the process of defect recognition, we introduce the idea of edge computing, so that part of the defect recognition tasks can realize end-to-end intelligence while taking images. Experimental results show that the proposed method can improve defect detection capability and guarantee the normal operation of power metering equipment largely.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114346292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Lou, Jiacheng Zhang, Lei Zhang, Q. Hong, Yueqi Zhou, Xinghua Li
Cyber physical transportation system (CPS-T) is a traffic perception, control and service system based on algorithm, model, data and computing power. With the help of radar point cloud, video image, GNSS, sensor and other types of monitoring equipment, the highway data can be collected with high quality and transmitted with high reliability under the condition of relatively complete communication conditions. This paper studies the technical application of CPS-T for highways. Through the deployment of communication technology and data cloud platform, it can intelligently perceive and analyze dynamic and static operation data, accurately identify or predict key ramps, bottleneck sections and mainstream traffic channels, and dynamically implement active control strategies such as ramp control, shoulder control, lane control and rate adjustment, so as to realize the advance guidance and control of highway traffic flow. The relevant research has been measured in the highway sections of Shanghai and Zhejiang Province, and the research results have strong engineering reference value.
{"title":"Research on highway CPS-T of wide area communication and data cloud","authors":"R. Lou, Jiacheng Zhang, Lei Zhang, Q. Hong, Yueqi Zhou, Xinghua Li","doi":"10.1145/3546000.3546005","DOIUrl":"https://doi.org/10.1145/3546000.3546005","url":null,"abstract":"Cyber physical transportation system (CPS-T) is a traffic perception, control and service system based on algorithm, model, data and computing power. With the help of radar point cloud, video image, GNSS, sensor and other types of monitoring equipment, the highway data can be collected with high quality and transmitted with high reliability under the condition of relatively complete communication conditions. This paper studies the technical application of CPS-T for highways. Through the deployment of communication technology and data cloud platform, it can intelligently perceive and analyze dynamic and static operation data, accurately identify or predict key ramps, bottleneck sections and mainstream traffic channels, and dynamically implement active control strategies such as ramp control, shoulder control, lane control and rate adjustment, so as to realize the advance guidance and control of highway traffic flow. The relevant research has been measured in the highway sections of Shanghai and Zhejiang Province, and the research results have strong engineering reference value.","PeriodicalId":196955,"journal":{"name":"Proceedings of the 6th International Conference on High Performance Compilation, Computing and Communications","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131848483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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