Pub Date : 1998-06-14DOI: 10.1109/HTEMDS.1998.730694
R. Grzybowski
Advances in SOI IC technology and the development of wide band gap semiconductors such as SiC are enabling practical deployment of high temperature electronics. While ICs are key to the realization of complete high temperature electronic systems, passive components including resistors, capacitors, magnetics and crystals are also required. This paper presents a representative cross-section of high temperature passive component characterization data with an emphasis on long term drift behavior. The goal of this study was to accumulate of the order of 5000 hours of long term parametric drift data at 200/spl deg/C on a large variety of carefully selected, commercially available passive component technologies. Device types represented include both small signal and power resistors and capacitors, and some results obtained from a study of crystals for use in oscillators designed to operate in extended temperature applications from -55/spl deg/C to 200/spl deg/C. Specific problems encountered with the use of these devices in harsh environments are discussed for each family of components.
{"title":"Long term behavior of passive components for high temperature applications-an update","authors":"R. Grzybowski","doi":"10.1109/HTEMDS.1998.730694","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730694","url":null,"abstract":"Advances in SOI IC technology and the development of wide band gap semiconductors such as SiC are enabling practical deployment of high temperature electronics. While ICs are key to the realization of complete high temperature electronic systems, passive components including resistors, capacitors, magnetics and crystals are also required. This paper presents a representative cross-section of high temperature passive component characterization data with an emphasis on long term drift behavior. The goal of this study was to accumulate of the order of 5000 hours of long term parametric drift data at 200/spl deg/C on a large variety of carefully selected, commercially available passive component technologies. Device types represented include both small signal and power resistors and capacitors, and some results obtained from a study of crystals for use in oscillators designed to operate in extended temperature applications from -55/spl deg/C to 200/spl deg/C. Specific problems encountered with the use of these devices in harsh environments are discussed for each family of components.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129315095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730653
T. Chow, N. Ramungul, M. Ghezzo
The present status of high-voltage SiC semiconductor switching devices is reviewed. The figures of merit that have been used for unipolar and bipolar devices to quantify the intrinsic performance improvement over silicon are presented. The choice and design of several key device structures are discussed. The performance expectations of the major two- and three-terminal unipolar and bipolar devices in 4H-SiC are presented. The recent rapid development of SiC material and process technology is described. The progress in high-voltage power device experimental demonstration is reviewed. The material and process technology issues that must be addressed for device commercialization are discussed.
{"title":"Recent advances in high-voltage SiC power devices","authors":"T. Chow, N. Ramungul, M. Ghezzo","doi":"10.1109/HTEMDS.1998.730653","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730653","url":null,"abstract":"The present status of high-voltage SiC semiconductor switching devices is reviewed. The figures of merit that have been used for unipolar and bipolar devices to quantify the intrinsic performance improvement over silicon are presented. The choice and design of several key device structures are discussed. The performance expectations of the major two- and three-terminal unipolar and bipolar devices in 4H-SiC are presented. The recent rapid development of SiC material and process technology is described. The progress in high-voltage power device experimental demonstration is reviewed. The material and process technology issues that must be addressed for device commercialization are discussed.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"148 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116557022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730641
R. Asai
The correlation between the HCl-H/sub 2/ pre-growth etching of 6H-SiC substrates and the electrical characteristics of Schottky barrier diodes on the epitaxial layers has been investigated. The morphology of 6H-SiC (Si-face) off-axis substrates and the subsequent epitaxial layers was changed by the etching. Electrical measurements revealed that the impurity concentration of the epitaxial layers and the diode characteristics were affected by the pre-growth etching. It was shown that the leakage current of the diode could be reduced to 5/spl times/10/sup -/8 A/cm/sup 2/ (at 200 V) by optimizing the etching.
{"title":"Effects of HCl-H/sub 2/ pre-growth etching on quality of 6H-SiC epitaxial layers","authors":"R. Asai","doi":"10.1109/HTEMDS.1998.730641","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730641","url":null,"abstract":"The correlation between the HCl-H/sub 2/ pre-growth etching of 6H-SiC substrates and the electrical characteristics of Schottky barrier diodes on the epitaxial layers has been investigated. The morphology of 6H-SiC (Si-face) off-axis substrates and the subsequent epitaxial layers was changed by the etching. Electrical measurements revealed that the impurity concentration of the epitaxial layers and the diode characteristics were affected by the pre-growth etching. It was shown that the leakage current of the diode could be reduced to 5/spl times/10/sup -/8 A/cm/sup 2/ (at 200 V) by optimizing the etching.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128508104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730697
D.D. Avrov, A. Bakin, S. I. Dorozhkin, V.P. Rastegaev, Yu.M. Tairov, B. Bilalov, G. Safaraliev, S. A. Shabanov, A. Lebedev
The electrophysical properties of SiC-AlN, SiC-BeO, and Al/sub 2/O/sub 3/ ceramics at high temperatures were investigated. Samples of ceramics were obtained by the hot-pressure method. The investigation shows that specific resistance at 300 K is: 10/sup 12/ /spl Omega/.cm, 10/sup 9/ /spl Omega/.cm, and 10/sup 7/ /spl Omega/.cm for SiC-BeO ceramics containing 0.5%, 1.0%, and 2.0% BeO respectively; 10/sup 12/ /spl Omega/.cm, 10/sup 8/ /spl Omega/.cm, and 10/sup 6/ /spl Omega/.cm for SiC-AlN ceramics containing /spl ges/50%, 20% and 10% AlN respectively; and 10/sup 1/2 /spl Omega/.cm for Al/sub 2/O/sub 3/. The specific resistance of all of these ceramics at 1500 K is about 10 /spl Omega/.cm.
{"title":"Electrical conductivity of ceramics of SiC-AlN, SiC-BeO, Al/sub 2/O/sub 3/ in the temperature range 300-1800 K","authors":"D.D. Avrov, A. Bakin, S. I. Dorozhkin, V.P. Rastegaev, Yu.M. Tairov, B. Bilalov, G. Safaraliev, S. A. Shabanov, A. Lebedev","doi":"10.1109/HTEMDS.1998.730697","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730697","url":null,"abstract":"The electrophysical properties of SiC-AlN, SiC-BeO, and Al/sub 2/O/sub 3/ ceramics at high temperatures were investigated. Samples of ceramics were obtained by the hot-pressure method. The investigation shows that specific resistance at 300 K is: 10/sup 12/ /spl Omega/.cm, 10/sup 9/ /spl Omega/.cm, and 10/sup 7/ /spl Omega/.cm for SiC-BeO ceramics containing 0.5%, 1.0%, and 2.0% BeO respectively; 10/sup 12/ /spl Omega/.cm, 10/sup 8/ /spl Omega/.cm, and 10/sup 6/ /spl Omega/.cm for SiC-AlN ceramics containing /spl ges/50%, 20% and 10% AlN respectively; and 10/sup 1/2 /spl Omega/.cm for Al/sub 2/O/sub 3/. The specific resistance of all of these ceramics at 1500 K is about 10 /spl Omega/.cm.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133523636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730690
S. Gasser
Contacts are the limiting factor in the performance of electronic devices operated at high temperatures. To fulfil the advanced requirements for contacts in that application, the most effective metallization scheme, at present, is one which is functionally divided into intermediate layers. A diffusion barrier is introduced between the interconnecting metal and the semiconductor to minimize interactions between the two. The best results are obtained with chemically inert ternary amorphous alloys that lack extended defects and grain boundaries. The contacting layer determines the electrical characteristics of the contact. Its design is complicated by the complex multielemental nature of its chemical interaction with high-temperature compound semiconductors. The concept and implementation of diffusion barriers and contacting layers are discussed with an emphasis on contacting layers to SiC.
{"title":"High-temperature contact metallization to semiconductors","authors":"S. Gasser","doi":"10.1109/HTEMDS.1998.730690","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730690","url":null,"abstract":"Contacts are the limiting factor in the performance of electronic devices operated at high temperatures. To fulfil the advanced requirements for contacts in that application, the most effective metallization scheme, at present, is one which is functionally divided into intermediate layers. A diffusion barrier is introduced between the interconnecting metal and the semiconductor to minimize interactions between the two. The best results are obtained with chemically inert ternary amorphous alloys that lack extended defects and grain boundaries. The contacting layer determines the electrical characteristics of the contact. Its design is complicated by the complex multielemental nature of its chemical interaction with high-temperature compound semiconductors. The concept and implementation of diffusion barriers and contacting layers are discussed with an emphasis on contacting layers to SiC.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730655
O. Vermesan, T. Rispal, L. Soulier
This paper describes the design and implementation of a low power/low voltage mixed signal BiCMOS ASIC that operates at temperatures up to 200/spl deg/C. The ASIC is integrated into a gauge for downhole pressure and temperature measurements. It incorporates four measurement channels (CLK1-clock one, CLK2-clock two, P-pressure, T-temperature), with four high precision X-tal Pierce oscillators and a signal processing path for each channel. The output frequency from the CLK1 channel is used as a precision reference for the pressure and temperature channels and as an external clock. The ASIC is designed for high pressure transducers and incorporated into a downhole memory and wireline quartz gauge. The ASIC was fabricated into a 1.2 /spl mu/m BiCMOS double poly, double metal process. The voltage supply range is from 5 V to 3.3 V and the circuit occupies a silicon area of 15 mm/sup 2/. The ASIC is packaged in a ceramic 28 pin SOIC package.
{"title":"Low power ASIC for high temperature applications","authors":"O. Vermesan, T. Rispal, L. Soulier","doi":"10.1109/HTEMDS.1998.730655","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730655","url":null,"abstract":"This paper describes the design and implementation of a low power/low voltage mixed signal BiCMOS ASIC that operates at temperatures up to 200/spl deg/C. The ASIC is integrated into a gauge for downhole pressure and temperature measurements. It incorporates four measurement channels (CLK1-clock one, CLK2-clock two, P-pressure, T-temperature), with four high precision X-tal Pierce oscillators and a signal processing path for each channel. The output frequency from the CLK1 channel is used as a precision reference for the pressure and temperature channels and as an external clock. The ASIC is designed for high pressure transducers and incorporated into a downhole memory and wireline quartz gauge. The ASIC was fabricated into a 1.2 /spl mu/m BiCMOS double poly, double metal process. The voltage supply range is from 5 V to 3.3 V and the circuit occupies a silicon area of 15 mm/sup 2/. The ASIC is packaged in a ceramic 28 pin SOIC package.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123001030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730692
R. Wenzel, F. Goesmann, R. Schmid-Fetzer
Silicon carbide is a very promising semiconductor material for high temperature applications and it can also be expected to become the material of choice for power semiconductor devices. One of the requirements for a working semiconductor device is the availability of a low resistance and thermally stable ohmic contact. Contact systems on n-6H-SiC using titanium-based contact materials (Ti/sub 3/SiC/sub 2/, TiSi/sub 2/, TiC), diffusion barriers (Pd, Ti, TiC, TiCN, W) and top metallizations (Al, Au, Pd) were investigated. Best results were obtained using the SiC-Ti/sub 3/SiC/sub 2/-Pd-Au contact layer structure, which is morphologically and electrically stable for up to 90 hours at 600/spl deg/C and exhibits good ohmic behaviour.
碳化硅是一种非常有前途的高温半导体材料，它也有望成为功率半导体器件的首选材料。工作半导体器件的要求之一是具有低电阻和热稳定的欧姆接触。研究了钛基接触材料(Ti/sub 3/SiC/sub 2/、TiSi/sub 2/、TiC)、扩散势垒(Pd、Ti、TiC、TiCN、W)和顶部金属化(Al、Au、Pd)在n-6H-SiC表面的接触体系。使用SiC- ti /sub - 3/SiC/sub - 2/-Pd-Au接触层结构获得了最好的结果，该结构在600/spl度/C下具有形貌和电稳定性长达90小时，并且具有良好的欧姆行为。
{"title":"Diffusion barriers on titanium-based ohmic contact structures on SiC","authors":"R. Wenzel, F. Goesmann, R. Schmid-Fetzer","doi":"10.1109/HTEMDS.1998.730692","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730692","url":null,"abstract":"Silicon carbide is a very promising semiconductor material for high temperature applications and it can also be expected to become the material of choice for power semiconductor devices. One of the requirements for a working semiconductor device is the availability of a low resistance and thermally stable ohmic contact. Contact systems on n-6H-SiC using titanium-based contact materials (Ti/sub 3/SiC/sub 2/, TiSi/sub 2/, TiC), diffusion barriers (Pd, Ti, TiC, TiCN, W) and top metallizations (Al, Au, Pd) were investigated. Best results were obtained using the SiC-Ti/sub 3/SiC/sub 2/-Pd-Au contact layer structure, which is morphologically and electrically stable for up to 90 hours at 600/spl deg/C and exhibits good ohmic behaviour.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122310129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730695
C. Gallagher, B. Shearer, G. Matijasevic
Currently, there are two major drivers for high operating temperature (HOT) electronics in the 135-200/spl deg/C range. Products with significant heat generation such as power electronics or small portable electronics without space for cooling mechanisms provide a large market segment in the low end of this temperature range. The upper end of the temperature regime is represented by products that are placed into a HOT environment such as distributed sensors and control systems. Use of polymers for packaging in these applications is typically hampered by the low thermal conductivity and thermal degradation resistance of polymeric materials used in low-cost laminate PWB technology. Also, HOT applications generally require exposure to rigorous thermal cycling for power up and down and environmental exposure. Classes of polymeric materials appropriate for the various aspects of electronic packaging at high operating temperatures and -55/spl deg/C-225/spl deg/C cycling are discussed. Also, a new electronic packaging technology which uses some elements of laminate, except that circuits are directly deposited on insulated metal substrates, is presented. This packaging has several-fold better thermal conductivity than conventional ceramic or polyimide glued-to-heat-sink HOT packaging, is more mechanically robust than ceramic, is lightweight and compact and can be deposited on 3D surfaces to minimize space requirements. Multilayer circuits with dimensions as small as 50 /spl mu/m lines and spaces and 75 /spl mu/m vias are possible, as well as large dimension circuits for power applications. This approach is also more cost effective than conventional HOT packaging.
{"title":"Materials selection issues for high operating temperature (HOT) electronic packaging","authors":"C. Gallagher, B. Shearer, G. Matijasevic","doi":"10.1109/HTEMDS.1998.730695","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730695","url":null,"abstract":"Currently, there are two major drivers for high operating temperature (HOT) electronics in the 135-200/spl deg/C range. Products with significant heat generation such as power electronics or small portable electronics without space for cooling mechanisms provide a large market segment in the low end of this temperature range. The upper end of the temperature regime is represented by products that are placed into a HOT environment such as distributed sensors and control systems. Use of polymers for packaging in these applications is typically hampered by the low thermal conductivity and thermal degradation resistance of polymeric materials used in low-cost laminate PWB technology. Also, HOT applications generally require exposure to rigorous thermal cycling for power up and down and environmental exposure. Classes of polymeric materials appropriate for the various aspects of electronic packaging at high operating temperatures and -55/spl deg/C-225/spl deg/C cycling are discussed. Also, a new electronic packaging technology which uses some elements of laminate, except that circuits are directly deposited on insulated metal substrates, is presented. This packaging has several-fold better thermal conductivity than conventional ceramic or polyimide glued-to-heat-sink HOT packaging, is more mechanically robust than ceramic, is lightweight and compact and can be deposited on 3D surfaces to minimize space requirements. Multilayer circuits with dimensions as small as 50 /spl mu/m lines and spaces and 75 /spl mu/m vias are possible, as well as large dimension circuits for power applications. This approach is also more cost effective than conventional HOT packaging.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114485347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730656
S. Cristoloveanu, G. Reichert
The present status of silicon-on-insulator (SOI) technologies, structures and devices is reviewed with the aim of demonstrating the attractiveness of CMOS SOI for high-temperature applications. The basic MOSFET parameters (leakage current, threshold voltage, carrier mobility and subthreshold swing) are described as a function of temperature up to 300/spl deg/C. The temperature behaviour of more specific SOI mechanisms, induced by the floating body, interface coupling and parasitic bipolar transistor, is also discussed.
{"title":"Recent advances in SOI materials and device technologies for high temperature","authors":"S. Cristoloveanu, G. Reichert","doi":"10.1109/HTEMDS.1998.730656","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730656","url":null,"abstract":"The present status of silicon-on-insulator (SOI) technologies, structures and devices is reviewed with the aim of demonstrating the attractiveness of CMOS SOI for high-temperature applications. The basic MOSFET parameters (leakage current, threshold voltage, carrier mobility and subthreshold swing) are described as a function of temperature up to 300/spl deg/C. The temperature behaviour of more specific SOI mechanisms, induced by the floating body, interface coupling and parasitic bipolar transistor, is also discussed.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123774050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-22DOI: 10.1109/HTEMDS.1998.730636
R. Nadella, O. W. Holland
The effect of light ion implantation damage on the resistivity of n-type 4H-silicon carbide was investigated using hydrogen and helium. Resistivity variation as a function of post-implant annealing temperature and measurement temperature was studied. Maximum resistivities of the order of 10/sup 7/ and 10/sup 8/ /spl Omega/-cm were observed for hydrogen and helium implanted samples, respectively, at room temperature. With increasing measurement temperature, resistivities decreased with activation energies of 0.36 and 0.16 eV for hydrogen and helium, respectively. Resistivities start to decrease after annealing at /spl ges/600/spl deg/C. Rutherford backscattering measurements show implantation damage in the high-resistivity samples.
{"title":"Hydrogen and helium implants for obtaining high-resistance layers in n-type 4H silicon carbide","authors":"R. Nadella, O. W. Holland","doi":"10.1109/HTEMDS.1998.730636","DOIUrl":"https://doi.org/10.1109/HTEMDS.1998.730636","url":null,"abstract":"The effect of light ion implantation damage on the resistivity of n-type 4H-silicon carbide was investigated using hydrogen and helium. Resistivity variation as a function of post-implant annealing temperature and measurement temperature was studied. Maximum resistivities of the order of 10/sup 7/ and 10/sup 8/ /spl Omega/-cm were observed for hydrogen and helium implanted samples, respectively, at room temperature. With increasing measurement temperature, resistivities decreased with activation energies of 0.36 and 0.16 eV for hydrogen and helium, respectively. Resistivities start to decrease after annealing at /spl ges/600/spl deg/C. Rutherford backscattering measurements show implantation damage in the high-resistivity samples.","PeriodicalId":197749,"journal":{"name":"1998 High-Temperature Electronic Materials, Devices and Sensors Conference (Cat. No.98EX132)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115767691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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