Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136849
Mathieu Rosiere, J. Desbarbieux, Nathalie Drach-Temam, F. Wajsbürt
Complex applications, such as multimedia, telephony or cryptography, in embedded systems must provide more and more performance that can be achieved by using multiple levels of parallelism. Today, FPGA are viable alternatives for these kinds of applications. Unfortunately, the available processors on FPGA do not provide sufficient performance. This work proposes the Morpheo tool that is a generator of configurable high performance processors dedicated to FPGA. As the FPGA architecture is more restrictive than on ASIC, VHDL models produced by Morpheo can also be used for an ASIC implementation. The main advantage is that there is no need for specific components, therefore, processors are easier to generate. Despite the architectural changes related to the FPGA target, the IPC (Instructions Per Cycle) of 2-way and 4-way superscalar processors are, respectively, 0.81 and 0.74 times that of M5 processors (ASIC targeted) with corresponding parameters. These processors can be placed in a Xilinx Virtex-5 xc5vlx330 using 15% and 31% of hardware available resources and perform at, respectively, 79 MHz and 72 MHz.
{"title":"Morpheo: A high-performance processor generator for a FPGA implementation","authors":"Mathieu Rosiere, J. Desbarbieux, Nathalie Drach-Temam, F. Wajsbürt","doi":"10.1109/DASIP.2011.6136849","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136849","url":null,"abstract":"Complex applications, such as multimedia, telephony or cryptography, in embedded systems must provide more and more performance that can be achieved by using multiple levels of parallelism. Today, FPGA are viable alternatives for these kinds of applications. Unfortunately, the available processors on FPGA do not provide sufficient performance. This work proposes the Morpheo tool that is a generator of configurable high performance processors dedicated to FPGA. As the FPGA architecture is more restrictive than on ASIC, VHDL models produced by Morpheo can also be used for an ASIC implementation. The main advantage is that there is no need for specific components, therefore, processors are easier to generate. Despite the architectural changes related to the FPGA target, the IPC (Instructions Per Cycle) of 2-way and 4-way superscalar processors are, respectively, 0.81 and 0.74 times that of M5 processors (ASIC targeted) with corresponding parameters. These processors can be placed in a Xilinx Virtex-5 xc5vlx330 using 15% and 31% of hardware available resources and perform at, respectively, 79 MHz and 72 MHz.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126261529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136881
T. Kryjak, M. Komorkiewicz, M. Gorgon
FPGA devices are a perfect platform for implementing image processing algorithms. In the article, an advanced video system is presented, which is able to detect moving objects in video sequences. The detection method is using two algorithms. First of all, a multimodal background generation method allows reliable scene modelling in case of rapid changes in lighting conditions and small background movement. Finally a segmentation based on three parameters lightness, colour and texture is applied. This approach allows to remove shadows from the processed image. Authors proposed some improvements and modifications to existing algorithms in order to make them suitable for reconfigurable platforms. In the final system only one, low cost, FPGA device is able to receive data from high speed digital camera, perform a Bayer transform, RGB to CIE Lab colour space conversion, generate a moving object mask and present results to the operator in real-time.
{"title":"Real-time moving object detection for video surveillance system in FPGA","authors":"T. Kryjak, M. Komorkiewicz, M. Gorgon","doi":"10.1109/DASIP.2011.6136881","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136881","url":null,"abstract":"FPGA devices are a perfect platform for implementing image processing algorithms. In the article, an advanced video system is presented, which is able to detect moving objects in video sequences. The detection method is using two algorithms. First of all, a multimodal background generation method allows reliable scene modelling in case of rapid changes in lighting conditions and small background movement. Finally a segmentation based on three parameters lightness, colour and texture is applied. This approach allows to remove shadows from the processed image. Authors proposed some improvements and modifications to existing algorithms in order to make them suitable for reconfigurable platforms. In the final system only one, low cost, FPGA device is able to receive data from high speed digital camera, perform a Bayer transform, RGB to CIE Lab colour space conversion, generate a moving object mask and present results to the operator in real-time.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136877
E. Bezati, H. Yviquel, M. Raulet, M. Mattavelli
This paper presents a methodology to specify from a high-level data-flow description an application for both hardware and software synthesis. Firstly, an introduction to RVC-Cal data-flow programming and Orcc framework is presented. Furthermore, an analysis of a close to gate intermediate representation (XLIM) is bestowed. As a proof of concept a JPEG codec was written purely in RVC-Cal to test the co-synthesis tools and then an analysis of the generated hardware and software results are given. Our experience shows that using RVC-Cal can unify the process of creating the same application for software and hardware without modifying a single source code for each solution.
{"title":"A unified hardware/software co-synthesis solution for signal processing systems","authors":"E. Bezati, H. Yviquel, M. Raulet, M. Mattavelli","doi":"10.1109/DASIP.2011.6136877","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136877","url":null,"abstract":"This paper presents a methodology to specify from a high-level data-flow description an application for both hardware and software synthesis. Firstly, an introduction to RVC-Cal data-flow programming and Orcc framework is presented. Furthermore, an analysis of a close to gate intermediate representation (XLIM) is bestowed. As a proof of concept a JPEG codec was written purely in RVC-Cal to test the co-synthesis tools and then an analysis of the generated hardware and software results are given. Our experience shows that using RVC-Cal can unify the process of creating the same application for software and hardware without modifying a single source code for each solution.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124832717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136891
M. Farahani, Eduardo Castillo Guerra, B. Colpitts
This paper presents a new common subexpression elimination (CSE) algorithm to realize FIR filters based on multiple constant multiplications (MCMs). This algorithm shares the maximum number of partial terms amongst minimal signed digit (MSD)-represented coefficients. It modifies the iterated matching (ITM) algorithm to share more partial terms in MCMs, which yields a significant logic and, consequently, chip area savings. The employment of the proposed algorithm results in efficient realizations of FIR filters with a fewer number of adders compared to the conventional CSE algorithms. Experimental results demonstrate a reduction up to 22% in the complexity of FIR filters over some conventional CSE algorithms. The proposed algorithm also addresses challenges encountered in resource-constrained applications, which require banks of high-order filters, such as in real-time distributed optical fiber sensor.
{"title":"A new algorithm for realization of FIR filters using multiple constant multiplications","authors":"M. Farahani, Eduardo Castillo Guerra, B. Colpitts","doi":"10.1109/DASIP.2011.6136891","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136891","url":null,"abstract":"This paper presents a new common subexpression elimination (CSE) algorithm to realize FIR filters based on multiple constant multiplications (MCMs). This algorithm shares the maximum number of partial terms amongst minimal signed digit (MSD)-represented coefficients. It modifies the iterated matching (ITM) algorithm to share more partial terms in MCMs, which yields a significant logic and, consequently, chip area savings. The employment of the proposed algorithm results in efficient realizations of FIR filters with a fewer number of adders compared to the conventional CSE algorithms. Experimental results demonstrate a reduction up to 22% in the complexity of FIR filters over some conventional CSE algorithms. The proposed algorithm also addresses challenges encountered in resource-constrained applications, which require banks of high-order filters, such as in real-time distributed optical fiber sensor.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121997357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136886
Andreas Dahlin, F. Jokhio, J. Lilius, J. Gorin, M. Raulet
The need for understanding how to distribute computations across multiple cores, have obviously increased in the multi-core era. Scheduling the functional blocks of an application for concurrent execution requires not only a good understanding of data dependencies, but also a structured way to describe the intended scheduling. In this paper we describe how the Canals language and its scheduling framework can be used for the purpose of scheduling and executing legacy code. Additionally a set of translation guidelines for translating RVC-CAL applications into Canals are presented. The proposed approaches are applied to an existing MPEG-4 Simple Profile decoder for evaluation purposes. The inverse discrete cosine transform (IDCT) is accelerated by the means of OpenCL.
{"title":"Interfacing and scheduling legacy code within the Canals framework","authors":"Andreas Dahlin, F. Jokhio, J. Lilius, J. Gorin, M. Raulet","doi":"10.1109/DASIP.2011.6136886","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136886","url":null,"abstract":"The need for understanding how to distribute computations across multiple cores, have obviously increased in the multi-core era. Scheduling the functional blocks of an application for concurrent execution requires not only a good understanding of data dependencies, but also a structured way to describe the intended scheduling. In this paper we describe how the Canals language and its scheduling framework can be used for the purpose of scheduling and executing legacy code. Additionally a set of translation guidelines for translating RVC-CAL applications into Canals are presented. The proposed approaches are applied to an existing MPEG-4 Simple Profile decoder for evaluation purposes. The inverse discrete cosine transform (IDCT) is accelerated by the means of OpenCL.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127922270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136856
M. Birk, Alexander Guth, M. Zapf, M. Balzer, N. Ruiter, M. Hübner, J. Becker
As today's standard screening methods frequently fail to diagnose breast cancer before metastases have developed, earlier breast cancer diagnosis is still a major challenge. Three-dimensional ultrasound computer tomography promises high-quality images of the breast, but is currently limited by a time-consuming synthetic aperture focusing technique based image reconstruction. In this work, we investigate the acceleration of the image reconstruction by a GPU, and by the FPGAs embedded in our custom data acquisition system. We compare the obtained performance results with a recent multi-core CPU and show that both platforms are able to accelerate processing. The GPU reaches the highest performance. Furthermore, we draw conclusions in terms of applicability of the accelerated reconstructions in future clinical application and highlight general principles for speed-up on GPUs and FPGAs.
{"title":"Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing","authors":"M. Birk, Alexander Guth, M. Zapf, M. Balzer, N. Ruiter, M. Hübner, J. Becker","doi":"10.1109/DASIP.2011.6136856","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136856","url":null,"abstract":"As today's standard screening methods frequently fail to diagnose breast cancer before metastases have developed, earlier breast cancer diagnosis is still a major challenge. Three-dimensional ultrasound computer tomography promises high-quality images of the breast, but is currently limited by a time-consuming synthetic aperture focusing technique based image reconstruction. In this work, we investigate the acceleration of the image reconstruction by a GPU, and by the FPGAs embedded in our custom data acquisition system. We compare the obtained performance results with a recent multi-core CPU and show that both platforms are able to accelerate processing. The GPU reaches the highest performance. Furthermore, we draw conclusions in terms of applicability of the accelerated reconstructions in future clinical application and highlight general principles for speed-up on GPUs and FPGAs.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122217798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136894
M. Hänninen, J. Suhonen, T. Hämäläinen, Marko Hännikäinen
Wireless Sensor Networks (WSN) comprise autonomous embedded nodes that combine sensing, actuation, and distributed computing with small size and low energy. Testing of WSNs is challenging due to distributed functionality, lack of test and debug interfaces, and limited communication, computation and memory resources. This paper presents the design and implementation of a practical network monitoring and analysis tool for identifying the causes of misbehavior. The tool consists of a sniffer node that passively captures WSN traffic, and multiple user interfaces that can run e.g. on a PC or mobile phone. Unlike the related proposals, our tool neither needs setting up an additional monitoring network alongside the actual WSN nor uses any node resources. Practical testing experiences with mul-tihop mesh WSN deployments show that the tool reveals design and implementation defects that are hard to discover with other testing methods such as in-network monitoring systems or debug prints.
{"title":"Practical monitoring and analysis tool for WSN testing","authors":"M. Hänninen, J. Suhonen, T. Hämäläinen, Marko Hännikäinen","doi":"10.1109/DASIP.2011.6136894","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136894","url":null,"abstract":"Wireless Sensor Networks (WSN) comprise autonomous embedded nodes that combine sensing, actuation, and distributed computing with small size and low energy. Testing of WSNs is challenging due to distributed functionality, lack of test and debug interfaces, and limited communication, computation and memory resources. This paper presents the design and implementation of a practical network monitoring and analysis tool for identifying the causes of misbehavior. The tool consists of a sniffer node that passively captures WSN traffic, and multiple user interfaces that can run e.g. on a PC or mobile phone. Unlike the related proposals, our tool neither needs setting up an additional monitoring network alongside the actual WSN nor uses any node resources. Practical testing experiences with mul-tihop mesh WSN deployments show that the tool reveals design and implementation defects that are hard to discover with other testing methods such as in-network monitoring systems or debug prints.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133203558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136892
Daniela Genius, Nicolas Pouillon
The task graph of telecommunication applications often exhibits massive coarse grained parallelism, which can be exploited by an on-chip multiprocessor. In many cases it can be organized into several subsequent stages, each containing dozens or even hundreds of identical tasks. We implement communications between tasks via software channels mapped to on-chip memory, allowing for multiple readers and writers to access them in arbitrary order. Our architecture is based on the shared memory paradigm. The interconnection network is hierarchical, so that communication latencies vary with the distance between the cluster where the task is located and the cluster on which the channel is placed. Moreover, packet sizes and arrival rates are subject to strong variations. An analytical approach to dimensioning the channels is thus near impossible. Within a purely simulation based approach, we gain insight into the performance of such software channels.
{"title":"Analyzing software inter-task communication channels on a clustered shared memory multi processor system-on-chip","authors":"Daniela Genius, Nicolas Pouillon","doi":"10.1109/DASIP.2011.6136892","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136892","url":null,"abstract":"The task graph of telecommunication applications often exhibits massive coarse grained parallelism, which can be exploited by an on-chip multiprocessor. In many cases it can be organized into several subsequent stages, each containing dozens or even hundreds of identical tasks. We implement communications between tasks via software channels mapped to on-chip memory, allowing for multiple readers and writers to access them in arbitrary order. Our architecture is based on the shared memory paradigm. The interconnection network is hierarchical, so that communication latencies vary with the distance between the cluster where the task is located and the cluster on which the channel is placed. Moreover, packet sizes and arrival rates are subject to strong variations. An analytical approach to dimensioning the channels is thus near impossible. Within a purely simulation based approach, we gain insight into the performance of such software channels.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130293445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136885
Youssef Souissi, J. Danger, S. Guilley, S. Bhasin, Maxime Nassar
One of the most redoubtable attacks on modern embedded systems are Side-Channel Analysis. In this paper, we propose a security evaluation framework which aims at organizing the work of the evaluator to reliably assess the robustness of embedded systems against such attacks. Moreover, we highlight common errors made by evaluators and solutions to avoid them.
{"title":"Embedded systems security: An evaluation methodology against Side Channel Attacks","authors":"Youssef Souissi, J. Danger, S. Guilley, S. Bhasin, Maxime Nassar","doi":"10.1109/DASIP.2011.6136885","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136885","url":null,"abstract":"One of the most redoubtable attacks on modern embedded systems are Side-Channel Analysis. In this paper, we propose a security evaluation framework which aims at organizing the work of the evaluator to reliably assess the robustness of embedded systems against such attacks. Moreover, we highlight common errors made by evaluators and solutions to avoid them.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124179164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136864
Matthieu Texier, R. David, K. B. Chehida, O. Sentieys
This paper describes the implementation of a graphic rendering pipeline on an MPSoC architecture devoted to the dynamic management of static task graphs. It exhibits the highly non stationary workloads of this application domain and provides first useful feedbacks motivating the design of innovative embedded architectures that have to face heterogeneous computation domains such as graphics and telecommunications. Especially these experiments stress the needs for data dependent resource allocation strategies.
{"title":"Graphic rendering application profiling on a shared memory MPSOC architecture","authors":"Matthieu Texier, R. David, K. B. Chehida, O. Sentieys","doi":"10.1109/DASIP.2011.6136864","DOIUrl":"https://doi.org/10.1109/DASIP.2011.6136864","url":null,"abstract":"This paper describes the implementation of a graphic rendering pipeline on an MPSoC architecture devoted to the dynamic management of static task graphs. It exhibits the highly non stationary workloads of this application domain and provides first useful feedbacks motivating the design of innovative embedded architectures that have to face heterogeneous computation domains such as graphics and telecommunications. Especially these experiments stress the needs for data dependent resource allocation strategies.","PeriodicalId":199500,"journal":{"name":"Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131824110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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