Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136873
Fabio Cenni, S. Scotti, E. Simeu
This work presents how an image acquisition system based on a CMOS image sensor (CIS) has been modeled by means of the recently standardized analog and mixed-signal (AMS) extension to the SystemC 1666 IEEE standard. Many optical and electrical effects at a high level of abstraction are described by the model while limiting the model complexity for making the model suitable to top-level simulations and performance analysis. A comparison among SystemC AMS models developed at different levels of abstraction is shown. The Sys-temC AMS model of the image sensor is supplied with input scenarios that mimic the scene captured by an image sensor inserted in a dark-box for tuning purposes. The model is integrated in a SystemC TLM platform that contains also the image signal processor (ISP) algorithms and a comparator between the detected image and the processed one. The resulting SystemC AMS/TLM platform demonstrates how the tight interaction between the SystemC AMS image sensor model and the SystemC TLM ISP model allows an early development/validation of the embedded software. Simulation results are shown and future related works discussed.
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Pub Date : 2011-11-01DOI: 10.1109/DASIP.2011.6136890
M. Elhaji, Brahim Attia, A. Zitouni, R. Tourki, S. Meftali, J. Dekeyser
Networks on Chip (NoCs) can improve a set of performances criteria, in complex SoCs, such as scalability, flexibility and adaptability. However, performances of a NoC are closely related to its topology. The diameter and average distance represent an important factor in term of performances and implementation. The proposed diagonal mesh topology is designed to offer a good tradeoff between hardware cost and theoretical quality of service (QoS). It can contain a large number of nodes without changing the maximum diameter which is equal to 2. In this paper, we present a new router architecture called FeRoNoC (Flexible, extensible Router NoC) and its Register Transfer Level (RTL) hardware implementation for the diagonal mesh topology. The architecture of our NoC is based on a flexible and extensible router which consists of a packet switching technique and deterministic routing algorithm. Effectiveness and performances of the proposed topology have been shown using a virtex5 FPGA implementation. A comparative performances study of the proposed NoC architecture with others topology is performed.
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