Pub Date : 2020-10-01DOI: 10.1109/ISSREW51248.2020.00093
Javier Alonso, K. Vaidyanathan, R. Pietrantuono
This paper summarizes the main methods adopted for the analysis and detection of software aging phenomena based on measurements (measurements-based aging analysis) as well as the metrics more commonly used as aging indicators.
本文总结了基于测量的软件老化现象分析和检测的主要方法(基于测量的老化分析)以及常用的老化指标。
{"title":"SAR Handbook Chapter: Measurements-based aging analysis","authors":"Javier Alonso, K. Vaidyanathan, R. Pietrantuono","doi":"10.1109/ISSREW51248.2020.00093","DOIUrl":"https://doi.org/10.1109/ISSREW51248.2020.00093","url":null,"abstract":"This paper summarizes the main methods adopted for the analysis and detection of software aging phenomena based on measurements (measurements-based aging analysis) as well as the metrics more commonly used as aging indicators.","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128516889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISSREW51248.2020.00039
Claudius V. Jordan, Florian Hauer, Philipp Foth, A. Pretschner
Testing is an important cost driver in development projects. Especially in the automotive industry, immense efforts are spent to carry out validation facing increasingly complex systems. Hardware-in-the-Loop test benches are essential elements for (functional) validation. Naturally, failures commonly occur, whose analysis is challenging, time-consuming and oftentimes performed manually, making the diagnosis process one decisive cost-driving factor. By experience, many failures happen due to few underlying faults. We discuss our lessons learned when performing similarity-based clustering to identify representative tests for each fault for system-level testing where test execution times are high and the complexity of the system-under-test and also the test setup leads to complicated failure conditions. Results from an industrial automotive case study–a drive train system dataset consisting of 57 test runs–show that utilizing our general, project-agnostic approach can effectively reduce failure analysis time even with a limited set of data points.
{"title":"Time-Series-Based Clustering for Failure Analysis in Hardware-in-the-Loop Setups: An Automotive Case Study","authors":"Claudius V. Jordan, Florian Hauer, Philipp Foth, A. Pretschner","doi":"10.1109/ISSREW51248.2020.00039","DOIUrl":"https://doi.org/10.1109/ISSREW51248.2020.00039","url":null,"abstract":"Testing is an important cost driver in development projects. Especially in the automotive industry, immense efforts are spent to carry out validation facing increasingly complex systems. Hardware-in-the-Loop test benches are essential elements for (functional) validation. Naturally, failures commonly occur, whose analysis is challenging, time-consuming and oftentimes performed manually, making the diagnosis process one decisive cost-driving factor. By experience, many failures happen due to few underlying faults. We discuss our lessons learned when performing similarity-based clustering to identify representative tests for each fault for system-level testing where test execution times are high and the complexity of the system-under-test and also the test setup leads to complicated failure conditions. Results from an industrial automotive case study–a drive train system dataset consisting of 57 test runs–show that utilizing our general, project-agnostic approach can effectively reduce failure analysis time even with a limited set of data points.","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126061447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISSREW51248.2020.00035
Maninder Singh, G. Walia
Software requirement specification (SRS) documents are written in natural language (NL) and are prone to contain faults due to the inherently ambiguous nature of NL. Inspections are employed to find and fix these faults during the early phases of development, where these are the most cost-effective to fix. Inspections being too manual are very tedious and time consuming to perform. After fixing a fault, the SRS author has to manually re-inspect the document to make sure if there are other similar requirements that need a fix, and also if fixing a fault does not reintroduce another fault in the document (i.e., change impact analysis). The proposed approach in this paper employs NL processing, machine learning, semantic analysis, and graph mining approaches to generate a graph of inter-related requirements (IRR) based on semantic similarity score. The IRR graph is next mined using graph mining approaches to analyze the impact of a change. Our approach when applied using a real SRS generated IRR and yielded promising results. Graph mining approaches resulted in a G-mean of more than 90% to accurately identify the highly similar requirements to support the CIA.
{"title":"Using Semantic Analysis and Graph Mining Approaches to Support Software Fault Fixation","authors":"Maninder Singh, G. Walia","doi":"10.1109/ISSREW51248.2020.00035","DOIUrl":"https://doi.org/10.1109/ISSREW51248.2020.00035","url":null,"abstract":"Software requirement specification (SRS) documents are written in natural language (NL) and are prone to contain faults due to the inherently ambiguous nature of NL. Inspections are employed to find and fix these faults during the early phases of development, where these are the most cost-effective to fix. Inspections being too manual are very tedious and time consuming to perform. After fixing a fault, the SRS author has to manually re-inspect the document to make sure if there are other similar requirements that need a fix, and also if fixing a fault does not reintroduce another fault in the document (i.e., change impact analysis). The proposed approach in this paper employs NL processing, machine learning, semantic analysis, and graph mining approaches to generate a graph of inter-related requirements (IRR) based on semantic similarity score. The IRR graph is next mined using graph mining approaches to analyze the impact of a change. Our approach when applied using a real SRS generated IRR and yielded promising results. Graph mining approaches resulted in a G-mean of more than 90% to accurately identify the highly similar requirements to support the CIA.","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116219644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISSREW51248.2020.00031
L. Jagadeesan, V. Mendiratta
Modern application development and deployment is rapidly evolving to microservices based architectures, in which thousands of microservices communicate with one another and can be independently scaled and updated. While these architectures enable flexibility of deployment and frequency of upgrades, the naive use of thousands of communicating and frequently updated microservices can significantly impact the reliability of applications. To address these challenges, service meshes are used to rapidly detect and respond to microservices failures without necessitating changes to the microservices themselves. However, there are inherent tradeoffs that service meshes must make with regards to how quickly they assume a microservice has failed and the subsequent impact on overall application reliability. We present in this paper a modeling framework for microservices and service mesh reliability that takes these tradeoffs into account. Index Terms–microservices, service mesh, sidecars, circuit breakers, reliability, availability, resilience, reliability models, probabilistic model checking, PRISM.
{"title":"When Failure is (Not) an Option: Reliability Models for Microservices Architectures","authors":"L. Jagadeesan, V. Mendiratta","doi":"10.1109/ISSREW51248.2020.00031","DOIUrl":"https://doi.org/10.1109/ISSREW51248.2020.00031","url":null,"abstract":"Modern application development and deployment is rapidly evolving to microservices based architectures, in which thousands of microservices communicate with one another and can be independently scaled and updated. While these architectures enable flexibility of deployment and frequency of upgrades, the naive use of thousands of communicating and frequently updated microservices can significantly impact the reliability of applications. To address these challenges, service meshes are used to rapidly detect and respond to microservices failures without necessitating changes to the microservices themselves. However, there are inherent tradeoffs that service meshes must make with regards to how quickly they assume a microservice has failed and the subsequent impact on overall application reliability. We present in this paper a modeling framework for microservices and service mesh reliability that takes these tradeoffs into account. Index Terms–microservices, service mesh, sidecars, circuit breakers, reliability, availability, resilience, reliability models, probabilistic model checking, PRISM.","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"790 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116135290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/issrew51248.2020.00016
{"title":"Message from the WoSAR 2020 Workshop Chairs","authors":"","doi":"10.1109/issrew51248.2020.00016","DOIUrl":"https://doi.org/10.1109/issrew51248.2020.00016","url":null,"abstract":"","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125039225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISSREW51248.2020.00062
N. Yakymets, Morayo Adedjouma
Fault tree analysis is a commonly used technique to assess the reliability of critical systems. The method requires modeling the propagation path of basic events that may cause a feared event, and define their probabilities. In this paper, we present a model-based approach to construct fault tree from SysML models and to perform quantitative analysis of the tree using FIDES reliability prediction standard. We exemplify the approach on a power interface unit system.
{"title":"Model-based Quantitative Fault Tree Analysis based on FIDES Reliability Prediction","authors":"N. Yakymets, Morayo Adedjouma","doi":"10.1109/ISSREW51248.2020.00062","DOIUrl":"https://doi.org/10.1109/ISSREW51248.2020.00062","url":null,"abstract":"Fault tree analysis is a commonly used technique to assess the reliability of critical systems. The method requires modeling the propagation path of basic events that may cause a feared event, and define their probabilities. In this paper, we present a model-based approach to construct fault tree from SysML models and to perform quantitative analysis of the tree using FIDES reliability prediction standard. We exemplify the approach on a power interface unit system.","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126172139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISSREW51248.2020.00041
Jean Guyomarc'h, Jean-Baptiste Hervé
Multitasking enables multiple tasks to be executed on the same hardware, and spatial partitioning aims at enforcing a strong isolation between them: tasks must not access memory regions for which they were not granted permission. This behavior is enforced at run-time by memory protection schemes enabled by dedicated hardware components. Today, memory protection is widely implemented on a great diversity of systems, mostly with dynamic requirements (e.g. variable number of tasks). Safety-critical systems must comply with high level of certification to ensure minimal probability of failure and are subject to stringent requirements on the embedded executable, which makes memory protection mandatory, but requires important certification efforts. This paper presents a method for the generation of static and verifiable memory partitioning schemes towards safety-critical systems, aiming at reducing certification costs without compromising safety properties.
{"title":"Static and Verifiable Memory Partitioning for Safety-Critical Systems","authors":"Jean Guyomarc'h, Jean-Baptiste Hervé","doi":"10.1109/ISSREW51248.2020.00041","DOIUrl":"https://doi.org/10.1109/ISSREW51248.2020.00041","url":null,"abstract":"Multitasking enables multiple tasks to be executed on the same hardware, and spatial partitioning aims at enforcing a strong isolation between them: tasks must not access memory regions for which they were not granted permission. This behavior is enforced at run-time by memory protection schemes enabled by dedicated hardware components. Today, memory protection is widely implemented on a great diversity of systems, mostly with dynamic requirements (e.g. variable number of tasks). Safety-critical systems must comply with high level of certification to ensure minimal probability of failure and are subject to stringent requirements on the embedded executable, which makes memory protection mandatory, but requires important certification efforts. This paper presents a method for the generation of static and verifiable memory partitioning schemes towards safety-critical systems, aiming at reducing certification costs without compromising safety properties.","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128884227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-01DOI: 10.1109/ISSREW51248.2020.00053
Thomas Hirsch
Fault localization has been determined as a major resource factor in the software development life cycle. Academic fault localization techniques are mostly unknown and unused in professional environments. Although manual debugging approaches can vary significantly depending on bug type (e.g. memory bugs or semantic bugs), these differences are not reflected in most existing fault localization tools. Little research has gone into automated identification of bug types to optimize the fault localization process. Further, existing fault localization techniques leverage on historical data only for augmentation of suspiciousness rankings. This thesis aims to provide a fault localization framework by combining data from various sources to help developers in the fault localization process. To achieve this, a bug classification schema is introduced, benchmarks are created, and a novel fault localization method based on historical data is proposed.
{"title":"A Fault Localization and Debugging Support Framework driven by Bug Tracking Data","authors":"Thomas Hirsch","doi":"10.1109/ISSREW51248.2020.00053","DOIUrl":"https://doi.org/10.1109/ISSREW51248.2020.00053","url":null,"abstract":"Fault localization has been determined as a major resource factor in the software development life cycle. Academic fault localization techniques are mostly unknown and unused in professional environments. Although manual debugging approaches can vary significantly depending on bug type (e.g. memory bugs or semantic bugs), these differences are not reflected in most existing fault localization tools. Little research has gone into automated identification of bug types to optimize the fault localization process. Further, existing fault localization techniques leverage on historical data only for augmentation of suspiciousness rankings. This thesis aims to provide a fault localization framework by combining data from various sources to help developers in the fault localization process. To achieve this, a bug classification schema is introduced, benchmarks are created, and a novel fault localization method based on historical data is proposed.","PeriodicalId":202247,"journal":{"name":"2020 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121928064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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