Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937679
N. Hadjigeorgiou, E. Hristoforou, P. Sotiriadis
Over the past twenty years' magnetic sensors have emerged as a preferred choice in many sensory systems due to their high accuracy, reliability and mechanical robustness. This has sparked the development of different types of magnetic sensors for magnetic field measurements as well as for measuring other quantities indirectly. Sensitivity, linearity, signal-to-noise ratio, measurement range and cross-talk between sensors in multi-axis / multi-sensor applications are only some of the magnetic sensor's characteristics that have been studied in the past. The aim of this paper is to present a fully analog current-feedback closed loop system for AMR (Anisotropic Magnetic Resistance) magnetic sensors. The calibration and testing were conducted in a 3D Helmholtz coil setup capable of controlling the magnetic field amplitude and direction in the AMR sensor area. The noise characterization was realized in a multilayer tube of soft magnetic material. Thorough experimental characterization and testing indicates that the proposed close loop architecture improves sensor's linearity while maintaining low noise level.
{"title":"Closed-loop current-feedback, signal-chopped, low noise AMR sensor with high linearity","authors":"N. Hadjigeorgiou, E. Hristoforou, P. Sotiriadis","doi":"10.1109/MOCAST.2017.7937679","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937679","url":null,"abstract":"Over the past twenty years' magnetic sensors have emerged as a preferred choice in many sensory systems due to their high accuracy, reliability and mechanical robustness. This has sparked the development of different types of magnetic sensors for magnetic field measurements as well as for measuring other quantities indirectly. Sensitivity, linearity, signal-to-noise ratio, measurement range and cross-talk between sensors in multi-axis / multi-sensor applications are only some of the magnetic sensor's characteristics that have been studied in the past. The aim of this paper is to present a fully analog current-feedback closed loop system for AMR (Anisotropic Magnetic Resistance) magnetic sensors. The calibration and testing were conducted in a 3D Helmholtz coil setup capable of controlling the magnetic field amplitude and direction in the AMR sensor area. The noise characterization was realized in a multilayer tube of soft magnetic material. Thorough experimental characterization and testing indicates that the proposed close loop architecture improves sensor's linearity while maintaining low noise level.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125159761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937643
Samar M. Ismail, L. Said, A. Rezk, A. Radwan, A. Madian, M. F. A. El-Yazeed, A. Soliman
This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the one dimensional double humped logistic map as well as the two-dimensional delayed logistic map. Different analyses are introduced to measure the performance of the proposed encryption system such as: histogram analysis, correlation coefficients, MAE, NPCR as well as UACI measurements. The encryption system is proven to be highly sensitive to ±0.001% perturbation of the logistic maps parameters. The system is tested on medical images of palm print as well as Parkinson disease MRI images.
{"title":"Image encryption based on double-humped and delayed logistic maps for biomedical applications","authors":"Samar M. Ismail, L. Said, A. Rezk, A. Radwan, A. Madian, M. F. A. El-Yazeed, A. Soliman","doi":"10.1109/MOCAST.2017.7937643","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937643","url":null,"abstract":"This paper presents a secured highly sensitive image encryption system suitable for biomedical applications. The pseudo random number generator of the presented system is based on two discrete logistic maps. The employed maps are: the one dimensional double humped logistic map as well as the two-dimensional delayed logistic map. Different analyses are introduced to measure the performance of the proposed encryption system such as: histogram analysis, correlation coefficients, MAE, NPCR as well as UACI measurements. The encryption system is proven to be highly sensitive to ±0.001% perturbation of the logistic maps parameters. The system is tested on medical images of palm print as well as Parkinson disease MRI images.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"71 1-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123469576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937668
Michalis P. Ninos, H. Nistazakis, G. Latsas, G. Tombras, Nikos Konofaos
Radio on Free-space optical communication systems have been gaining much attention due to their high bandwidth capabilities, addressing the emerging high demands for massive data transfers in wireless communication networks without the need for optical fibers. Thus in this work, we present a single-input multiple-output orthogonal frequency division multiplexing wireless optical communication system with phase shift keying and maximum ratio combining on the receivers' side. Analytical closed-form expressions are extracted for the estimation of the system's average BER, taking into account the atmospheric turbulence and pointing errors effects. The latter is modeled by the gamma-gamma distribution. Finally, numerical results are presented for various realistic turbulence conditions, spatial jitter influence and diversity options.
{"title":"PSK OFDM optical wireless communication systems with receiver's diversity over gamma-gamma turbulence channels and spatial jitter","authors":"Michalis P. Ninos, H. Nistazakis, G. Latsas, G. Tombras, Nikos Konofaos","doi":"10.1109/MOCAST.2017.7937668","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937668","url":null,"abstract":"Radio on Free-space optical communication systems have been gaining much attention due to their high bandwidth capabilities, addressing the emerging high demands for massive data transfers in wireless communication networks without the need for optical fibers. Thus in this work, we present a single-input multiple-output orthogonal frequency division multiplexing wireless optical communication system with phase shift keying and maximum ratio combining on the receivers' side. Analytical closed-form expressions are extracted for the estimation of the system's average BER, taking into account the atmospheric turbulence and pointing errors effects. The latter is modeled by the gamma-gamma distribution. Finally, numerical results are presented for various realistic turbulence conditions, spatial jitter influence and diversity options.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115228507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937619
C. Mourtzios, K. Siakavara
In this work a 2×2 multiband, non-uniform Electromagnetic Band Gap (EBG) antenna array is proposed for the realization of a MIMO (Multiple Input-Multiple Output) wireless communication system. It is proved that the strong reduction of mutual coupling among the array's elements, ensured by this EBG lattice type, is capable of enhancing the MIMO channel capacity. The channel impulse response was estimated taking into account the spatial correlation and the antenna characteristics both into one step capacity calculation. Results for the capacity at all three bands of operation(1.99GHz, 4GHz, 5.1GHz) are presented, for various SNR levels, along with respective ones received from antenna arrays with classic Uniform EBG (Mushroom type) and also Perfect Electric Conductor (PEC). The comparison shows clearly the superiority of the proposed hybrid antenna array.
{"title":"MIMO channel capacity increase by hybrid non-uniform EBG antenna arrays","authors":"C. Mourtzios, K. Siakavara","doi":"10.1109/MOCAST.2017.7937619","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937619","url":null,"abstract":"In this work a 2×2 multiband, non-uniform Electromagnetic Band Gap (EBG) antenna array is proposed for the realization of a MIMO (Multiple Input-Multiple Output) wireless communication system. It is proved that the strong reduction of mutual coupling among the array's elements, ensured by this EBG lattice type, is capable of enhancing the MIMO channel capacity. The channel impulse response was estimated taking into account the spatial correlation and the antenna characteristics both into one step capacity calculation. Results for the capacity at all three bands of operation(1.99GHz, 4GHz, 5.1GHz) are presented, for various SNR levels, along with respective ones received from antenna arrays with classic Uniform EBG (Mushroom type) and also Perfect Electric Conductor (PEC). The comparison shows clearly the superiority of the proposed hybrid antenna array.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114971273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937612
Giannis Petrousov, M. Dasygenis
It is a known fact that an arithmetic function implemented in hardware has a higher throughput and calculation frequency than the one implemented in software, thus making the usage of hardware components imminent in applications where speed plays a crucial role. Sum of absolute difference (SAD) is an arithmetic operation most frequently used in motion estimation algorithms and video coding consequently. This operation can become very slow when applied on large inputs due to it's complexity and the series of additions it consists of. Electronic design automation tools can alleviate the burden of the design teams when creating new prototype hardware components. In this paper, we present an EDA tool which is able to generate the SAD component for arbitrary number of inputs.
{"title":"Realization of a hardware generator for the sum of absolute difference component","authors":"Giannis Petrousov, M. Dasygenis","doi":"10.1109/MOCAST.2017.7937612","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937612","url":null,"abstract":"It is a known fact that an arithmetic function implemented in hardware has a higher throughput and calculation frequency than the one implemented in software, thus making the usage of hardware components imminent in applications where speed plays a crucial role. Sum of absolute difference (SAD) is an arithmetic operation most frequently used in motion estimation algorithms and video coding consequently. This operation can become very slow when applied on large inputs due to it's complexity and the series of additions it consists of. Electronic design automation tools can alleviate the burden of the design teams when creating new prototype hardware components. In this paper, we present an EDA tool which is able to generate the SAD component for arbitrary number of inputs.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126250899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937685
A. El‐naggar, L. Said, A. Radwan, A. Madian, A. Soliman
This paper presents a generalization of Soliman's four-phase oscillator into the fractional-order domain. The extra degrees of freedom provided by the fractional-order parameters α and β add more flexibility to the design of the circuit. The design procedure and equations of the proposed oscillator are presented and verified using Matlab and PSPICE. Also, the stability analysis for fractional order systems is studied for different cases of α and β.
{"title":"Fractional order four-phase oscillator based on double integrator topology","authors":"A. El‐naggar, L. Said, A. Radwan, A. Madian, A. Soliman","doi":"10.1109/MOCAST.2017.7937685","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937685","url":null,"abstract":"This paper presents a generalization of Soliman's four-phase oscillator into the fractional-order domain. The extra degrees of freedom provided by the fractional-order parameters α and β add more flexibility to the design of the circuit. The design procedure and equations of the proposed oscillator are presented and verified using Matlab and PSPICE. Also, the stability analysis for fractional order systems is studied for different cases of α and β.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131837007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937633
L. Frontini, A. Stabile, V. Liberali
Associative memories are massively parallel circuits which perform a parallel comparison between stored data and input data. When operated in parallel comparison mode, they require high current spikes (in the order of few amperes) at every clock edge, and the voltage drop due to current spikes can seriously affect the circuit operation. This paper proposes a method to enhance the power integrity, both at package level and at chip level. This work aims at avoiding “bounce” effects on supply voltages, and at keeping the supply voltage ripple below one hundred millivolts during the comparison mode. A technique to mitigate the voltage ripple consists in placing decoupling capacitors on the Power Delivery Network (PDN). This technique can be applied both at the chip level and at the package level. We show that this technique allows us to keep the power network impedance below 0.1 Ω within the relevant bandwidth of the circuit.
{"title":"Power Distribution Network optimization for Associative Memories","authors":"L. Frontini, A. Stabile, V. Liberali","doi":"10.1109/MOCAST.2017.7937633","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937633","url":null,"abstract":"Associative memories are massively parallel circuits which perform a parallel comparison between stored data and input data. When operated in parallel comparison mode, they require high current spikes (in the order of few amperes) at every clock edge, and the voltage drop due to current spikes can seriously affect the circuit operation. This paper proposes a method to enhance the power integrity, both at package level and at chip level. This work aims at avoiding “bounce” effects on supply voltages, and at keeping the supply voltage ripple below one hundred millivolts during the comparison mode. A technique to mitigate the voltage ripple consists in placing decoupling capacitors on the Power Delivery Network (PDN). This technique can be applied both at the chip level and at the package level. We show that this technique allows us to keep the power network impedance below 0.1 Ω within the relevant bandwidth of the circuit.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125160581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937667
I. Mesolongitis, Achilleas Gkountis, E. Kyriakis-Bitzaros, K. Zachariadou, P. Gkountoumis, T. Alexopoulos
The Level-1 Data Driver Card (L1DDC) is designed to fulfill the needs of the New Small Wheel, which will be used in the upgraded ATLAS experiment detectors. L1DDC's function is to concentrate the data from multiple front-end boards and transmit them through a network interface, to the control room. The proper operation of the L1DDC is critical for the credibility of the ATLAS experiment, thus extensive testing of the prototype boards is required. To perform the debugging and testing of the L1DDC a number of additional boards and FPGAs with specially developed firmware are used. This paper describes the methodology followed for the testing of the L1DDC and presents the results of the experiments performed to determine data integrity for all data rates supported for the front-end cards, i.e., 80, 160 and 320 Mb/s.
{"title":"Testing the Level-1 Data Driver Card for the New Small Wheel of the ATLAS detector","authors":"I. Mesolongitis, Achilleas Gkountis, E. Kyriakis-Bitzaros, K. Zachariadou, P. Gkountoumis, T. Alexopoulos","doi":"10.1109/MOCAST.2017.7937667","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937667","url":null,"abstract":"The Level-1 Data Driver Card (L1DDC) is designed to fulfill the needs of the New Small Wheel, which will be used in the upgraded ATLAS experiment detectors. L1DDC's function is to concentrate the data from multiple front-end boards and transmit them through a network interface, to the control room. The proper operation of the L1DDC is critical for the credibility of the ATLAS experiment, thus extensive testing of the prototype boards is required. To perform the debugging and testing of the L1DDC a number of additional boards and FPGAs with specially developed firmware are used. This paper describes the methodology followed for the testing of the L1DDC and presents the results of the experiments performed to determine data integrity for all data rates supported for the front-end cards, i.e., 80, 160 and 320 Mb/s.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115511446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937684
N. Soliman, L. Said, A. Azar, A. Madian, A. Ouannas, A. Radwan
This paper is an extension of V-shape multi-scroll butterfly attractor in the fractional-order domain. The system complexity is increased by the new dynamics introduced by the fractional operator which make it more suitable for random signal generator. The effect of system parameters on controlling the attractor shape is investigated and compared with the integer order attractor. Maximum Lyapunov exponent is calculated for both integer and fractional orders attractors to prove the complexity of fractional chaotic system using time series.
{"title":"Fractional controllable multi-scroll V-shape attractor with parameters effect","authors":"N. Soliman, L. Said, A. Azar, A. Madian, A. Ouannas, A. Radwan","doi":"10.1109/MOCAST.2017.7937684","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937684","url":null,"abstract":"This paper is an extension of V-shape multi-scroll butterfly attractor in the fractional-order domain. The system complexity is increased by the new dynamics introduced by the fractional operator which make it more suitable for random signal generator. The effect of system parameters on controlling the attractor shape is investigated and compared with the integer order attractor. Maximum Lyapunov exponent is calculated for both integer and fractional orders attractors to prove the complexity of fractional chaotic system using time series.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124849884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-05-01DOI: 10.1109/MOCAST.2017.7937691
Thomas Makryniotis, M. Dasygenis
The new trends in multimedia and especially in video applications demand the best possible quality, among with low bandwidth and memory usage. While video compression has been used for many decades, now is of even greater significance, particularly in the 4K and 8K UHD standards. In addition, the most time consuming and computationally expensive part of video compression, is the calculation of the objects' movement between successive frames, a procedure known as Motion Estimation. Our purpose in this paper was to create an embedded system which implements a Motion Estimation unit that is being controlled and fed by an ARM CPU. For that reason we used the Xilinx Zynq platform, which provides great flexibility and can be used to effectively evaluate an embedded system prototype. Our experimental results illustrate that it is perfectly feasible to implement fast and reliable accelerators, especially for multimedia applications, in a platform such as Xilinx Zynq.
{"title":"Implementation of a motion estimation hardware accelerator on Zynq SoC","authors":"Thomas Makryniotis, M. Dasygenis","doi":"10.1109/MOCAST.2017.7937691","DOIUrl":"https://doi.org/10.1109/MOCAST.2017.7937691","url":null,"abstract":"The new trends in multimedia and especially in video applications demand the best possible quality, among with low bandwidth and memory usage. While video compression has been used for many decades, now is of even greater significance, particularly in the 4K and 8K UHD standards. In addition, the most time consuming and computationally expensive part of video compression, is the calculation of the objects' movement between successive frames, a procedure known as Motion Estimation. Our purpose in this paper was to create an embedded system which implements a Motion Estimation unit that is being controlled and fed by an ARM CPU. For that reason we used the Xilinx Zynq platform, which provides great flexibility and can be used to effectively evaluate an embedded system prototype. Our experimental results illustrate that it is perfectly feasible to implement fast and reliable accelerators, especially for multimedia applications, in a platform such as Xilinx Zynq.","PeriodicalId":202381,"journal":{"name":"2017 6th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130670819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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