Neural networks have achieved remarkable success across various fields. However, the lack of interpretability limits their practical use, particularly in critical decision-making scenarios. Posthoc interpretability, which provides explanations for pretrained models, is often at risk of fidelity and robustness. This has inspired a rising interest in self-interpretable neural networks (SINNs), which inherently reveal the prediction rationale through model structures. Despite this progress, existing research remains fragmented, relying on intuitive designs tailored to specific tasks. To bridge these efforts and foster a unified framework, we first collect and review existing works on SINNs and provide a structured summary of their methodologies from five key perspectives: attribution-based, function-based, concept-based, prototype-based, and rule-based self-interpretation. We also present concrete, visualized examples of model explanations and discuss their applicability across diverse scenarios, including image, text, graph data, and deep reinforcement learning (DRL). Additionally, we summarize existing evaluation metrics for self-interpretation and identify open challenges in this field, offering insights for future research. To support ongoing developments, we present a publicly accessible resource to track advancements in this domain: https://github.com/yangji721/Awesome-Self-Interpretable-Neural-Network
{"title":"A Comprehensive Survey on Self-Interpretable Neural Networks","authors":"Yang Ji;Ying Sun;Yuting Zhang;Zhigaoyuan Wang;Yuanxin Zhuang;Zheng Gong;Dazhong Shen;Chuan Qin;Hengshu Zhu;Hui Xiong","doi":"10.1109/JPROC.2025.3635153","DOIUrl":"10.1109/JPROC.2025.3635153","url":null,"abstract":"Neural networks have achieved remarkable success across various fields. However, the lack of interpretability limits their practical use, particularly in critical decision-making scenarios. Posthoc interpretability, which provides explanations for pretrained models, is often at risk of fidelity and robustness. This has inspired a rising interest in self-interpretable neural networks (SINNs), which inherently reveal the prediction rationale through model structures. Despite this progress, existing research remains fragmented, relying on intuitive designs tailored to specific tasks. To bridge these efforts and foster a unified framework, we first collect and review existing works on SINNs and provide a structured summary of their methodologies from five key perspectives: attribution-based, function-based, concept-based, prototype-based, and rule-based self-interpretation. We also present concrete, visualized examples of model explanations and discuss their applicability across diverse scenarios, including image, text, graph data, and deep reinforcement learning (DRL). Additionally, we summarize existing evaluation metrics for self-interpretation and identify open challenges in this field, offering insights for future research. To support ongoing developments, we present a publicly accessible resource to track advancements in this domain: <uri>https://github.com/yangji721/Awesome-Self-Interpretable-Neural-Network</uri>","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 8","pages":"783-813"},"PeriodicalIF":25.9,"publicationDate":"2025-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145664821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Deformation of flexible robots can be practically assessed using extension/compression, shear, curvature, and torsion. Sensing based on one or more of the above characteristics enables closed-loop control for delicate tasks that require precision and dexterity. Due to the increasing popularity of flexible robotics in recent years, significant research effort has been directed to this burgeoning field. Although numerous studies have addressed soft sensing technologies, their successful integration into flexible robotic systems remains limited. This article provides a comprehensive review of sensing methods, from multidimensional deformation to the underlying principles of deriving hard-to-measure deformation from surrogate parameters. It focuses on sensing modalities such as strain measurement via piezoelectric, capacitive, resistive, and optical techniques. The applications of deformation sensing in industrial and service robotics are described. Future challenges and potential research issues including resolution, conformability, multifunctionality, crosstalk, and miniaturization are discussed. The need for a synergistic approach across disciplines is highlighted, emphasizing the integration of new materials, microstructures, advanced manufacturing technologies, and state-of-the-art signal processing techniques.
{"title":"Progress in Deformation Sensing for Flexible Robots","authors":"Zecai Lin;Cheng Zhou;Shaoping Huang;Weidong Chen;Guang-Zhong Yang;Anzhu Gao","doi":"10.1109/JPROC.2025.3633933","DOIUrl":"10.1109/JPROC.2025.3633933","url":null,"abstract":"Deformation of flexible robots can be practically assessed using extension/compression, shear, curvature, and torsion. Sensing based on one or more of the above characteristics enables closed-loop control for delicate tasks that require precision and dexterity. Due to the increasing popularity of flexible robotics in recent years, significant research effort has been directed to this burgeoning field. Although numerous studies have addressed soft sensing technologies, their successful integration into flexible robotic systems remains limited. This article provides a comprehensive review of sensing methods, from multidimensional deformation to the underlying principles of deriving hard-to-measure deformation from surrogate parameters. It focuses on sensing modalities such as strain measurement via piezoelectric, capacitive, resistive, and optical techniques. The applications of deformation sensing in industrial and service robotics are described. Future challenges and potential research issues including resolution, conformability, multifunctionality, crosstalk, and miniaturization are discussed. The need for a synergistic approach across disciplines is highlighted, emphasizing the integration of new materials, microstructures, advanced manufacturing technologies, and state-of-the-art signal processing techniques.","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 8","pages":"752-782"},"PeriodicalIF":25.9,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145599489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-20DOI: 10.1109/JPROC.2025.3630989
Swaroop Ghosh;Suryansh Upadhyay;Abdullah Ash Saki
Quantum computing (QC) is an emerging paradigm with the potential to transform numerous application domains by addressing classically intractable problems. However, its growing presence in cyberspace has introduced new security and privacy challenges. Similar to classical computing systems, the QC stack including software and hardware relies extensively on third parties, many of which are emerging and trust-seeking or less-trusted. This stack often contains sensitive intellectual property (IP) that demands protection. Unique features of quantum systems can enable classical-style attacks: for instance, crosstalk in multitenant settings can facilitate fault-injection attacks, while malicious calibration services can misreport error rates or miscalibrate qubits to induce denial-of-service (DoS) conditions. Given the high cost and limited availability of likely trustworthy quantum hardware, users may be enticed to explore emerging and trust-seeking but cheaper and readily available quantum hardware, which can enable the stealth of IP and tampering of quantum programs and/or computation outcomes. Similarly, emerging compilation services may compromise circuit confidentiality or insert Trojans. Despite the strategic significance of QC and its potential to process sensitive information, its security and privacy concerns remain underexplored. This article presents a comprehensive overview of QC fundamentals, key vulnerabilities, recent attack vectors, and corresponding defenses, and concludes with directions for future research to strengthen the quantum security community.
{"title":"A Primer on Security of Quantum Computing Hardware","authors":"Swaroop Ghosh;Suryansh Upadhyay;Abdullah Ash Saki","doi":"10.1109/JPROC.2025.3630989","DOIUrl":"10.1109/JPROC.2025.3630989","url":null,"abstract":"Quantum computing (QC) is an emerging paradigm with the potential to transform numerous application domains by addressing classically intractable problems. However, its growing presence in cyberspace has introduced new security and privacy challenges. Similar to classical computing systems, the QC stack including software and hardware relies extensively on third parties, many of which are emerging and trust-seeking or less-trusted. This stack often contains sensitive intellectual property (IP) that demands protection. Unique features of quantum systems can enable classical-style attacks: for instance, crosstalk in multitenant settings can facilitate fault-injection attacks, while malicious calibration services can misreport error rates or miscalibrate qubits to induce denial-of-service (DoS) conditions. Given the high cost and limited availability of likely trustworthy quantum hardware, users may be enticed to explore emerging and trust-seeking but cheaper and readily available quantum hardware, which can enable the stealth of IP and tampering of quantum programs and/or computation outcomes. Similarly, emerging compilation services may compromise circuit confidentiality or insert Trojans. Despite the strategic significance of QC and its potential to process sensitive information, its security and privacy concerns remain underexplored. This article presents a comprehensive overview of QC fundamentals, key vulnerabilities, recent attack vectors, and corresponding defenses, and concludes with directions for future research to strengthen the quantum security community.","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 7","pages":"640-667"},"PeriodicalIF":25.9,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145559593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-19DOI: 10.1109/JPROC.2025.3632102
Tom Bäckström
Speech technology for communication, accessing information, and services has rapidly improved in quality. It is convenient and appealing because speech is the primary mode of communication for humans. Such technology, however, also presents proven threats to privacy. Speech is a tool for communication, and thus, it will inherently contain private information. Importantly, it also contains a wealth of side information, including details about health, emotions, affiliations, and relationships, all of which are private. Exposing such private information can lead to serious threats such as price gouging, harassment, extortion, and stalking. This article is a tutorial on privacy issues related to speech technology, modeling their threats, approaches for protecting users’ privacy, measuring the performance of privacy-protecting methods, perception of privacy, as well as societal and legal consequences. In addition to a tutorial overview, it also presents lines for further development where improvements are most urgently needed.
{"title":"Privacy in Speech Technology","authors":"Tom Bäckström","doi":"10.1109/JPROC.2025.3632102","DOIUrl":"10.1109/JPROC.2025.3632102","url":null,"abstract":"Speech technology for communication, accessing information, and services has rapidly improved in quality. It is convenient and appealing because speech is the primary mode of communication for humans. Such technology, however, also presents proven threats to privacy. Speech is a tool for communication, and thus, it will inherently contain private information. Importantly, it also contains a wealth of side information, including details about health, emotions, affiliations, and relationships, all of which are private. Exposing such private information can lead to serious threats such as price gouging, harassment, extortion, and stalking. This article is a tutorial on privacy issues related to speech technology, modeling their threats, approaches for protecting users’ privacy, measuring the performance of privacy-protecting methods, perception of privacy, as well as societal and legal consequences. In addition to a tutorial overview, it also presents lines for further development where improvements are most urgently needed.","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 7","pages":"668-692"},"PeriodicalIF":25.9,"publicationDate":"2025-11-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11261339","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145553527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-18DOI: 10.1109/JPROC.2025.3627402
Peter M. Grant;John S. Thompson;Simon Watts
{"title":"The Cavity Magnetron Developments Which Enabled the Rapid Deployment of Airborne Radar Systems in World War II","authors":"Peter M. Grant;John S. Thompson;Simon Watts","doi":"10.1109/JPROC.2025.3627402","DOIUrl":"10.1109/JPROC.2025.3627402","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 7","pages":"693-706"},"PeriodicalIF":25.9,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145545627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/jproc.2025.3617487
Raunak Bhattacharyya, Kyle J. Brown, Juanran Wang, Katherine Driggs-Campbell, Mykel J. Kochenderfer
{"title":"A Taxonomy and Review of Algorithms for Modeling and Predicting Human Driver Behavior","authors":"Raunak Bhattacharyya, Kyle J. Brown, Juanran Wang, Katherine Driggs-Campbell, Mykel J. Kochenderfer","doi":"10.1109/jproc.2025.3617487","DOIUrl":"https://doi.org/10.1109/jproc.2025.3617487","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"78 1","pages":""},"PeriodicalIF":20.6,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145447508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/JPROC.2025.3623023
Andrew Boutros;Aman Arora;Vaughn Betz
Deep learning (DL) is becoming the cornerstone of numerous applications both in large-scale datacenters and at the edge. Specialized hardware is often necessary to meet the performance requirements of state-of-the-art DL models, but the rapid pace of change in DL models and the wide variety of systems integrating DL make it impossible to create custom computer chips for all but the largest markets. Field-programmable gate arrays (FPGAs) present a unique blend of reprogrammability and direct hardware execution that make them suitable for accelerating DL inference. They offer the ability to customize processing pipelines and memory hierarchies to achieve lower latency and higher energy efficiency compared to general-purpose central processing units (CPUs) and graphics processing units (GPUs), at a fraction of the development time and cost of custom chips. Their diverse and high-speed inputs/outputs (IOs) also enable directly interfacing the FPGA to the network and/or a variety of external sensors, making them suitable for both datacenter and edge use cases. As DL has become an ever more important workload, FPGA architectures are evolving to enable higher DL performance. In this article, we survey both academic and industrial FPGA chip architecture enhancements for DL. First, we give a brief introduction on the basics of FPGA architecture and how its components lead to strengths and weaknesses for DL applications. Next, we discuss different design styles of DL inference accelerators implemented on FPGAs that achieve state-of-the-art performance and productive development flows, ranging from model-specific dataflow styles to software-programmable overlay styles. We survey DL-specific enhancements to traditional FPGA building blocks including the logic blocks (LBs), arithmetic circuitry, and on-chip memories, as well as new DL-specialized blocks that integrate into the FPGA fabric to accelerate tensor computations. Finally, we discuss hybrid devices that combine processors and coarse-grained accelerator blocks with FPGA-like interconnect and networks-on-chip (NoCs), and highlight promising future research directions.
{"title":"Field-Programmable Gate Array Architecture for Deep Learning: Survey and Future Directions","authors":"Andrew Boutros;Aman Arora;Vaughn Betz","doi":"10.1109/JPROC.2025.3623023","DOIUrl":"10.1109/JPROC.2025.3623023","url":null,"abstract":"Deep learning (DL) is becoming the cornerstone of numerous applications both in large-scale datacenters and at the edge. Specialized hardware is often necessary to meet the performance requirements of state-of-the-art DL models, but the rapid pace of change in DL models and the wide variety of systems integrating DL make it impossible to create custom computer chips for all but the largest markets. Field-programmable gate arrays (FPGAs) present a unique blend of reprogrammability and direct hardware execution that make them suitable for accelerating DL inference. They offer the ability to customize processing pipelines and memory hierarchies to achieve lower latency and higher energy efficiency compared to general-purpose central processing units (CPUs) and graphics processing units (GPUs), at a fraction of the development time and cost of custom chips. Their diverse and high-speed inputs/outputs (IOs) also enable directly interfacing the FPGA to the network and/or a variety of external sensors, making them suitable for both datacenter and edge use cases. As DL has become an ever more important workload, FPGA architectures are evolving to enable higher DL performance. In this article, we survey both academic and industrial FPGA chip architecture enhancements for DL. First, we give a brief introduction on the basics of FPGA architecture and how its components lead to strengths and weaknesses for DL applications. Next, we discuss different design styles of DL inference accelerators implemented on FPGAs that achieve state-of-the-art performance and productive development flows, ranging from model-specific dataflow styles to software-programmable overlay styles. We survey DL-specific enhancements to traditional FPGA building blocks including the logic blocks (LBs), arithmetic circuitry, and on-chip memories, as well as new DL-specialized blocks that integrate into the FPGA fabric to accelerate tensor computations. Finally, we discuss hybrid devices that combine processors and coarse-grained accelerator blocks with FPGA-like interconnect and networks-on-chip (NoCs), and highlight promising future research directions.","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 7","pages":"613-639"},"PeriodicalIF":25.9,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222684","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145404263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/jproc.2025.3616531
{"title":"TechRxiv","authors":"","doi":"10.1109/jproc.2025.3616531","DOIUrl":"https://doi.org/10.1109/jproc.2025.3616531","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"38 1","pages":""},"PeriodicalIF":20.6,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/jproc.2025.3610964
{"title":"Future Special Issues/Special Sections of the Proceedings","authors":"","doi":"10.1109/jproc.2025.3610964","DOIUrl":"https://doi.org/10.1109/jproc.2025.3610964","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"11 1","pages":""},"PeriodicalIF":20.6,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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