Pub Date : 2025-11-18DOI: 10.1109/JPROC.2025.3627402
Peter M. Grant;John S. Thompson;Simon Watts
{"title":"The Cavity Magnetron Developments Which Enabled the Rapid Deployment of Airborne Radar Systems in World War II","authors":"Peter M. Grant;John S. Thompson;Simon Watts","doi":"10.1109/JPROC.2025.3627402","DOIUrl":"10.1109/JPROC.2025.3627402","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 7","pages":"693-706"},"PeriodicalIF":25.9,"publicationDate":"2025-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145545627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-05DOI: 10.1109/jproc.2025.3617487
Raunak Bhattacharyya, Kyle J. Brown, Juanran Wang, Katherine Driggs-Campbell, Mykel J. Kochenderfer
{"title":"A Taxonomy and Review of Algorithms for Modeling and Predicting Human Driver Behavior","authors":"Raunak Bhattacharyya, Kyle J. Brown, Juanran Wang, Katherine Driggs-Campbell, Mykel J. Kochenderfer","doi":"10.1109/jproc.2025.3617487","DOIUrl":"https://doi.org/10.1109/jproc.2025.3617487","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"78 1","pages":""},"PeriodicalIF":20.6,"publicationDate":"2025-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145447508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-30DOI: 10.1109/JPROC.2025.3623023
Andrew Boutros;Aman Arora;Vaughn Betz
Deep learning (DL) is becoming the cornerstone of numerous applications both in large-scale datacenters and at the edge. Specialized hardware is often necessary to meet the performance requirements of state-of-the-art DL models, but the rapid pace of change in DL models and the wide variety of systems integrating DL make it impossible to create custom computer chips for all but the largest markets. Field-programmable gate arrays (FPGAs) present a unique blend of reprogrammability and direct hardware execution that make them suitable for accelerating DL inference. They offer the ability to customize processing pipelines and memory hierarchies to achieve lower latency and higher energy efficiency compared to general-purpose central processing units (CPUs) and graphics processing units (GPUs), at a fraction of the development time and cost of custom chips. Their diverse and high-speed inputs/outputs (IOs) also enable directly interfacing the FPGA to the network and/or a variety of external sensors, making them suitable for both datacenter and edge use cases. As DL has become an ever more important workload, FPGA architectures are evolving to enable higher DL performance. In this article, we survey both academic and industrial FPGA chip architecture enhancements for DL. First, we give a brief introduction on the basics of FPGA architecture and how its components lead to strengths and weaknesses for DL applications. Next, we discuss different design styles of DL inference accelerators implemented on FPGAs that achieve state-of-the-art performance and productive development flows, ranging from model-specific dataflow styles to software-programmable overlay styles. We survey DL-specific enhancements to traditional FPGA building blocks including the logic blocks (LBs), arithmetic circuitry, and on-chip memories, as well as new DL-specialized blocks that integrate into the FPGA fabric to accelerate tensor computations. Finally, we discuss hybrid devices that combine processors and coarse-grained accelerator blocks with FPGA-like interconnect and networks-on-chip (NoCs), and highlight promising future research directions.
{"title":"Field-Programmable Gate Array Architecture for Deep Learning: Survey and Future Directions","authors":"Andrew Boutros;Aman Arora;Vaughn Betz","doi":"10.1109/JPROC.2025.3623023","DOIUrl":"10.1109/JPROC.2025.3623023","url":null,"abstract":"Deep learning (DL) is becoming the cornerstone of numerous applications both in large-scale datacenters and at the edge. Specialized hardware is often necessary to meet the performance requirements of state-of-the-art DL models, but the rapid pace of change in DL models and the wide variety of systems integrating DL make it impossible to create custom computer chips for all but the largest markets. Field-programmable gate arrays (FPGAs) present a unique blend of reprogrammability and direct hardware execution that make them suitable for accelerating DL inference. They offer the ability to customize processing pipelines and memory hierarchies to achieve lower latency and higher energy efficiency compared to general-purpose central processing units (CPUs) and graphics processing units (GPUs), at a fraction of the development time and cost of custom chips. Their diverse and high-speed inputs/outputs (IOs) also enable directly interfacing the FPGA to the network and/or a variety of external sensors, making them suitable for both datacenter and edge use cases. As DL has become an ever more important workload, FPGA architectures are evolving to enable higher DL performance. In this article, we survey both academic and industrial FPGA chip architecture enhancements for DL. First, we give a brief introduction on the basics of FPGA architecture and how its components lead to strengths and weaknesses for DL applications. Next, we discuss different design styles of DL inference accelerators implemented on FPGAs that achieve state-of-the-art performance and productive development flows, ranging from model-specific dataflow styles to software-programmable overlay styles. We survey DL-specific enhancements to traditional FPGA building blocks including the logic blocks (LBs), arithmetic circuitry, and on-chip memories, as well as new DL-specialized blocks that integrate into the FPGA fabric to accelerate tensor computations. Finally, we discuss hybrid devices that combine processors and coarse-grained accelerator blocks with FPGA-like interconnect and networks-on-chip (NoCs), and highlight promising future research directions.","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 7","pages":"613-639"},"PeriodicalIF":25.9,"publicationDate":"2025-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11222684","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145404263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/jproc.2025.3616531
{"title":"TechRxiv","authors":"","doi":"10.1109/jproc.2025.3616531","DOIUrl":"https://doi.org/10.1109/jproc.2025.3616531","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"38 1","pages":""},"PeriodicalIF":20.6,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/jproc.2025.3610964
{"title":"Future Special Issues/Special Sections of the Proceedings","authors":"","doi":"10.1109/jproc.2025.3610964","DOIUrl":"https://doi.org/10.1109/jproc.2025.3610964","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"11 1","pages":""},"PeriodicalIF":20.6,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/JPROC.2025.3610940
{"title":"Proceedings of the IEEE Publication Information","authors":"","doi":"10.1109/JPROC.2025.3610940","DOIUrl":"10.1109/JPROC.2025.3610940","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 6","pages":"C2-C2"},"PeriodicalIF":25.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11207089","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/JPROC.2025.3616533
{"title":"IEEE Foundation","authors":"","doi":"10.1109/JPROC.2025.3616533","DOIUrl":"10.1109/JPROC.2025.3616533","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 6","pages":"608-608"},"PeriodicalIF":25.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11207082","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/JPROC.2025.3614274
Summary form only: Abstracts of articles presented in this issue of the publication.
仅以摘要形式提供：本刊发表的文章摘要。
{"title":"Scanning the Issue","authors":"","doi":"10.1109/JPROC.2025.3614274","DOIUrl":"10.1109/JPROC.2025.3614274","url":null,"abstract":"Summary form only: Abstracts of articles presented in this issue of the publication.","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 6","pages":"514-515"},"PeriodicalIF":25.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11207084","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/JPROC.2025.3616529
{"title":"IEEE Connects You to a Universe of Information","authors":"","doi":"10.1109/JPROC.2025.3616529","DOIUrl":"10.1109/JPROC.2025.3616529","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 6","pages":"606-606"},"PeriodicalIF":25.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11207092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-17DOI: 10.1109/JPROC.2025.3610968
{"title":"Proceedings of the IEEE: Stay Informed. Become Inspired.","authors":"","doi":"10.1109/JPROC.2025.3610968","DOIUrl":"10.1109/JPROC.2025.3610968","url":null,"abstract":"","PeriodicalId":20556,"journal":{"name":"Proceedings of the IEEE","volume":"113 6","pages":"C4-C4"},"PeriodicalIF":25.9,"publicationDate":"2025-10-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11207088","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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