Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357289
M. Golanbari, S. Kiamehr, R. Bishnoi, M. Tahoori
This paper presents a reliable memory-based Physical Unclonable Function (PUF) design for operating at low supply voltages, which is typically demanded in emerging Internet of Things (IoT) applications with stringent energy constraints. PUF is a promising approach for generating unique and secure IDs based on the intrinsic uncontrollable manufacturing process variation. A common approach is to use the power-up values of SRAM memory arrays as the PUF response. However, reliability of the PUF response is a major concern for such designs, in particular, at low supply voltage values where the impact of noisy operating environment becomes significant. As a result, a noisy PUF response due to the non-ideal reliability at low supply voltages, has to be transformed into a stable high-entropy key by a key extractor circuitry, which imposes significant area and power overhead. The proposed PUF design in this paper has the advantage of being highly reliable at low supply voltages allowing aggressive supply voltage reduction for lower power consumption and better energy efficiency with lower area and overhead of key extractor. In this paper, we first evaluate the reliability of the SRAM-based PUFs over a wide range of supply voltages from the super-threshold voltage regime down to the Near-Threshold Voltage (NTV) regime. Based on this analysis, we propose a new memory-based PUF design which provides higher reliability (2.6× improvement) while consuming less power (∼ 2×) compared to the traditional SRAM PUF designs in the NTV region.
{"title":"Reliable memory PUF design for low-power applications","authors":"M. Golanbari, S. Kiamehr, R. Bishnoi, M. Tahoori","doi":"10.1109/ISQED.2018.8357289","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357289","url":null,"abstract":"This paper presents a reliable memory-based Physical Unclonable Function (PUF) design for operating at low supply voltages, which is typically demanded in emerging Internet of Things (IoT) applications with stringent energy constraints. PUF is a promising approach for generating unique and secure IDs based on the intrinsic uncontrollable manufacturing process variation. A common approach is to use the power-up values of SRAM memory arrays as the PUF response. However, reliability of the PUF response is a major concern for such designs, in particular, at low supply voltage values where the impact of noisy operating environment becomes significant. As a result, a noisy PUF response due to the non-ideal reliability at low supply voltages, has to be transformed into a stable high-entropy key by a key extractor circuitry, which imposes significant area and power overhead. The proposed PUF design in this paper has the advantage of being highly reliable at low supply voltages allowing aggressive supply voltage reduction for lower power consumption and better energy efficiency with lower area and overhead of key extractor. In this paper, we first evaluate the reliability of the SRAM-based PUFs over a wide range of supply voltages from the super-threshold voltage regime down to the Near-Threshold Voltage (NTV) regime. Based on this analysis, we propose a new memory-based PUF design which provides higher reliability (2.6× improvement) while consuming less power (∼ 2×) compared to the traditional SRAM PUF designs in the NTV region.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127305873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357323
Ahmet Turan Erozan, M. Golanbari, R. Bishnoi, J. Aghassi‐Hagmann, M. Tahoori
Printed Electronics (PE) is a promising technology that provides mechanical flexibility and low-cost fabrication. These features make PE the key enabler for emerging applications, such as smart sensors, wearables, and Internet of Things (IoTs). Since these applications need secure communication and/or authentication, it is vital to utilize security primitives for cryptographic key and identification. Physical Unclonable Functions (PUF) have been adopted widely to provide the secure keys. In this work, we present a weak PUF based on Electrolyte-gated FETs using inorganic inkjet printed electronics. A comprehensive analysis framework including Monte Carlo simulations based on real device measurements is developed to evaluate the proposed PE-PUF. Moreover, a multi-bit PE-PUF design is proposed to optimize area usage. The analysis results show that the PE-PUF has ideal uniqueness, good reliability, and can operates at low voltage which is critical for low-power PE applications. In addition, the proposed multi-bit PE-PUF reduces the area usage around 30%.
{"title":"Design and evaluation of physical unclonable function for inorganic printed electronics","authors":"Ahmet Turan Erozan, M. Golanbari, R. Bishnoi, J. Aghassi‐Hagmann, M. Tahoori","doi":"10.1109/ISQED.2018.8357323","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357323","url":null,"abstract":"Printed Electronics (PE) is a promising technology that provides mechanical flexibility and low-cost fabrication. These features make PE the key enabler for emerging applications, such as smart sensors, wearables, and Internet of Things (IoTs). Since these applications need secure communication and/or authentication, it is vital to utilize security primitives for cryptographic key and identification. Physical Unclonable Functions (PUF) have been adopted widely to provide the secure keys. In this work, we present a weak PUF based on Electrolyte-gated FETs using inorganic inkjet printed electronics. A comprehensive analysis framework including Monte Carlo simulations based on real device measurements is developed to evaluate the proposed PE-PUF. Moreover, a multi-bit PE-PUF design is proposed to optimize area usage. The analysis results show that the PE-PUF has ideal uniqueness, good reliability, and can operates at low voltage which is critical for low-power PE applications. In addition, the proposed multi-bit PE-PUF reduces the area usage around 30%.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115415093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357278
Boris Vaisband, A. Bajwa, S. Iyer
Silicon interconnect fabric (Si-IF) supports integration of bare dies using thermal compression bonding on a Si wafer substrate. Fine pitch (2 to 10 μm) horizontal and vertical inter-connects are feasible within the Si-IF using standard Si processing techniques. A network on interconnect fabric (NoIF) is proposed in this paper. The NoIF enables integration of ultra large scale heterogeneous systems within the technologically mature Si-IF platform. NoIF is based on utility dies which serve as intelligent nodes within the network. NoIF enables global communication, power conversion and management, synchronization, processing and memory capabilities, redundancy allocation, and test of the Si-IF, and the utility and functional dies.
{"title":"Network on interconnect fabric","authors":"Boris Vaisband, A. Bajwa, S. Iyer","doi":"10.1109/ISQED.2018.8357278","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357278","url":null,"abstract":"Silicon interconnect fabric (Si-IF) supports integration of bare dies using thermal compression bonding on a Si wafer substrate. Fine pitch (2 to 10 μm) horizontal and vertical inter-connects are feasible within the Si-IF using standard Si processing techniques. A network on interconnect fabric (NoIF) is proposed in this paper. The NoIF enables integration of ultra large scale heterogeneous systems within the technologically mature Si-IF platform. NoIF is based on utility dies which serve as intelligent nodes within the network. NoIF enables global communication, power conversion and management, synchronization, processing and memory capabilities, redundancy allocation, and test of the Si-IF, and the utility and functional dies.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131871101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357282
Sarmad Tanwir, M. Hsiao, L. Lingappan
We propose a novel and effective online method for performing diagnosis of scan chains with the physical defective circuits in the loop. We first apply flush tests to determine the faulty chains and their corresponding fault types. Then, we generate new patterns using an evolutionary algorithm and quickly analyze the responses to perform diagnosis. We are able to achieve an average of 70% and 37% improvement in the diagnosis quality for the segmented and non-segmented scan chains respectively, as compared to a state-of-the-art offline industry tool, when 0 to 7 faults were randomly inserted in each scan chain. Our method does require additional tester time, which may be preferred to the computational, setup and overhead costs of the offline diagnosis, especially during the yield learning process.
{"title":"An online framework for diagnosis of multiple defects in scan chains","authors":"Sarmad Tanwir, M. Hsiao, L. Lingappan","doi":"10.1109/ISQED.2018.8357282","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357282","url":null,"abstract":"We propose a novel and effective online method for performing diagnosis of scan chains with the physical defective circuits in the loop. We first apply flush tests to determine the faulty chains and their corresponding fault types. Then, we generate new patterns using an evolutionary algorithm and quickly analyze the responses to perform diagnosis. We are able to achieve an average of 70% and 37% improvement in the diagnosis quality for the segmented and non-segmented scan chains respectively, as compared to a state-of-the-art offline industry tool, when 0 to 7 faults were randomly inserted in each scan chain. Our method does require additional tester time, which may be preferred to the computational, setup and overhead costs of the offline diagnosis, especially during the yield learning process.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131512516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357270
S. Nishizawa, H. Onodera
This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equations for transistor widths tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.
{"title":"Process variation aware D-Flip-Flop design using regression analysis","authors":"S. Nishizawa, H. Onodera","doi":"10.1109/ISQED.2018.8357270","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357270","url":null,"abstract":"This paper describes a design methodology for process variation aware D-Flip-Flop (DFF) using regression analysis. We propose to use a regression analysis to model the worst-case delay characteristics of a DFF under process variation. We utilize the regression equations for transistor widths tuning of the DFF to improve its worst-case delay performance. Regression analysis can not only identify the performance-critical transistors inside the DFF, but also shows these impacts on DFF delay performance in quantitative form. Proposed design methodology is verified using Monte-Carlo simulation. The result shows the proposed method achieves to design a DFF which has similar or better delay characteristics in comparison with the DFF designed by an experienced cell designer.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131555512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357302
G. Qian, Yuhua Cheng, Guoxiong Chen, Gaofeng Wang
Wireless power transfer (WPT) is a promising technique for powering the Internet-of-Things devices. Printed spiral coils (PSCs) are commonly used in WPT because of their advantages of compact size and standardized fabrication. Under the demand of analytically optimizing the WPT system, like power transfer efficiency or power delivered to the load, an analytical resistance model is required. In this paper, the proximity-effect resistance is focused on. A formula is curve-fitted based on the data simulated from COMSOL Multiphysics and magnetic field calculation. The total AC resistance model which is the sum of skin-effect resistance and proximity-effect resistance is verified by HFSS simulation and measurement. Under the impact of inductance and parasitic capacitance, the comparison of the calculated, simulated, and measured real parts of Z-impedance shows that the difference between them is increased quickly when the operating frequency is higher than the frequency corresponding to the maximal quality factor of a PSC. A more accurate self-resonant frequency or capacitance model should be developed in the future work.
{"title":"New AC resistance calculation of printed spiral coils for wireless power transfer","authors":"G. Qian, Yuhua Cheng, Guoxiong Chen, Gaofeng Wang","doi":"10.1109/ISQED.2018.8357302","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357302","url":null,"abstract":"Wireless power transfer (WPT) is a promising technique for powering the Internet-of-Things devices. Printed spiral coils (PSCs) are commonly used in WPT because of their advantages of compact size and standardized fabrication. Under the demand of analytically optimizing the WPT system, like power transfer efficiency or power delivered to the load, an analytical resistance model is required. In this paper, the proximity-effect resistance is focused on. A formula is curve-fitted based on the data simulated from COMSOL Multiphysics and magnetic field calculation. The total AC resistance model which is the sum of skin-effect resistance and proximity-effect resistance is verified by HFSS simulation and measurement. Under the impact of inductance and parasitic capacitance, the comparison of the calculated, simulated, and measured real parts of Z-impedance shows that the difference between them is increased quickly when the operating frequency is higher than the frequency corresponding to the maximal quality factor of a PSC. A more accurate self-resonant frequency or capacitance model should be developed in the future work.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129641201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-03DOI: 10.1109/ISQED.2018.8357306
Xiaolong Ma, Yipeng Zhang, Geng Yuan, Ao Ren, Zhe Li, Jie Han, J. Hu, Yanzhi Wang
With recent trend of wearable devices and Internet of Things (IoTs), it becomes attractive to develop hardware-based deep convolutional neural networks (DCNNs) for embedded applications, which require low power/energy consumptions and small hardware footprints. Recent works demonstrated that the Stochastic Computing (SC) technique can radically simplify the hardware implementation of arithmetic units and has the potential to satisfy the stringent power requirements in embedded devices. However, in these works, the memory design optimization is neglected for weight storage, which will inevitably result in large hardware cost. Moreover, if conventional volatile SRAM or DRAM cells are utilized for weight storage, the weights need to be re-initialized whenever the DCNN platform is re-started. In order to overcome these limitations, in this work we adopt an emerging non-volatile Domain-Wall Memory (DWM), which can achieve ultra-high density, to replace SRAM for weight storage in SC-based DCNNs. We propose DW-CNN, the first comprehensive design optimization framework of DWM-based weight storage method. We derive the optimal memory type, precision, and organization, as well as whether to store binary or stochastic numbers. We present effective resource sharing scheme for DWM-based weight storage in the convolutional and fully-connected layers of SC-based DCNNs to achieve a desirable balance among area, power (energy) consumption, and application-level accuracy.
{"title":"An area and energy efficient design of domain-wall memory-based deep convolutional neural networks using stochastic computing","authors":"Xiaolong Ma, Yipeng Zhang, Geng Yuan, Ao Ren, Zhe Li, Jie Han, J. Hu, Yanzhi Wang","doi":"10.1109/ISQED.2018.8357306","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357306","url":null,"abstract":"With recent trend of wearable devices and Internet of Things (IoTs), it becomes attractive to develop hardware-based deep convolutional neural networks (DCNNs) for embedded applications, which require low power/energy consumptions and small hardware footprints. Recent works demonstrated that the Stochastic Computing (SC) technique can radically simplify the hardware implementation of arithmetic units and has the potential to satisfy the stringent power requirements in embedded devices. However, in these works, the memory design optimization is neglected for weight storage, which will inevitably result in large hardware cost. Moreover, if conventional volatile SRAM or DRAM cells are utilized for weight storage, the weights need to be re-initialized whenever the DCNN platform is re-started. In order to overcome these limitations, in this work we adopt an emerging non-volatile Domain-Wall Memory (DWM), which can achieve ultra-high density, to replace SRAM for weight storage in SC-based DCNNs. We propose DW-CNN, the first comprehensive design optimization framework of DWM-based weight storage method. We derive the optimal memory type, precision, and organization, as well as whether to store binary or stochastic numbers. We present effective resource sharing scheme for DWM-based weight storage in the convolutional and fully-connected layers of SC-based DCNNs to achieve a desirable balance among area, power (energy) consumption, and application-level accuracy.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131105875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-01-11DOI: 10.1109/ISQED.2018.8357319
M. Nazemi, Amir Erfan Eshratifar, Massoud Pedram
With ever-increasing application of machine learning models in various domains such as image classification, speech recognition and synthesis, and health care, designing efficient hardware for these models has gained a lot of popularity. While the majority of researches in this area focus on efficient deployment of machine learning models (a.k.a inference), this work concentrates on challenges of training these models in hardware. In particular, this paper presents a high-performance, scalable, reconfigurable solution for both training and deployment of different dimensionality reduction models in hardware by introducing a hardware-friendly algorithm. Compared to state-of-the-art implementations, our proposed algorithm and its hardware realization decrease resource consumption by 50% without any degradation in accuracy.
{"title":"A hardware-friendly algorithm for scalable training and deployment of dimensionality reduction models on FPGA","authors":"M. Nazemi, Amir Erfan Eshratifar, Massoud Pedram","doi":"10.1109/ISQED.2018.8357319","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357319","url":null,"abstract":"With ever-increasing application of machine learning models in various domains such as image classification, speech recognition and synthesis, and health care, designing efficient hardware for these models has gained a lot of popularity. While the majority of researches in this area focus on efficient deployment of machine learning models (a.k.a inference), this work concentrates on challenges of training these models in hardware. In particular, this paper presents a high-performance, scalable, reconfigurable solution for both training and deployment of different dimensionality reduction models in hardware by introducing a hardware-friendly algorithm. Compared to state-of-the-art implementations, our proposed algorithm and its hardware realization decrease resource consumption by 50% without any degradation in accuracy.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-01-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121405867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISQED.2018.8357312
Paul C.-P. Paul, Pei-Yu Chiang, D. Tarng, Chih-Yu Yang
Mathematical derivation of calculating blood flow volume (BFV) at arteriovenous fistula (AVF) using a newly-developed photoplethysmography (PPG) sensor is presented in this work. Also, the readout circuit of the PPG sensor intended to increase the signal-noise ratio (S/NR) is designed and presented in this work. The designed PPG sensor equipped with derived mathematical equations shows high correlation (R2 = 0.7563) and low error (RMSE = 212 ml/min) as compared to the gold standard.
{"title":"Mathematical derivation, circuits design and clinical experiments of measuring blood flow volume (BFV) at arteriovenous fistula (AVF) of hemodialysis (HD) patients using a newly-developed photoplethysmography (PPG) sensor","authors":"Paul C.-P. Paul, Pei-Yu Chiang, D. Tarng, Chih-Yu Yang","doi":"10.1109/ISQED.2018.8357312","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357312","url":null,"abstract":"Mathematical derivation of calculating blood flow volume (BFV) at arteriovenous fistula (AVF) using a newly-developed photoplethysmography (PPG) sensor is presented in this work. Also, the readout circuit of the PPG sensor intended to increase the signal-noise ratio (S/NR) is designed and presented in this work. The designed PPG sensor equipped with derived mathematical equations shows high correlation (R2 = 0.7563) and low error (RMSE = 212 ml/min) as compared to the gold standard.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132997896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ISQED.2018.8357324
Kuen-Wey Lin, M. Hashimoto, Yih-Lang Li
Because it is difficult to find empty space in a developed city to accommodate more transportation infrastructures, the development of an effective navigation system is a low cost option for mitigating traffic jam. Regarding a future world where automated driving technologies have become mature and most vehicles follow the pre-scheduled route suggested by a navigation system, it is likely to predict the traffic jam accurately if the navigation system can know the pre-scheduled route of each vehicle. Recently, a navigation algorithm is presented for automated driving vehicles with the assumption that all the navigating query requests are processed by a single system. However, the aforementioned algorithm does not consider any kind of uncertainty originating from accidents and destination change. To get close to the real world, we propose a navigation algorithm with near-future evaluation capability that also allows some kinds of uncertainties. We compare our algorithm with a dynamic-update based conventional navigation algorithm without near-future evaluation capability. We download some metropolitan maps from OpenStreetMap and utilize the data of traffic flow from official statistics to randomly generate many sets queries. Experimental results show that the total cruising time is improved for each case.
{"title":"Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties","authors":"Kuen-Wey Lin, M. Hashimoto, Yih-Lang Li","doi":"10.1109/ISQED.2018.8357324","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357324","url":null,"abstract":"Because it is difficult to find empty space in a developed city to accommodate more transportation infrastructures, the development of an effective navigation system is a low cost option for mitigating traffic jam. Regarding a future world where automated driving technologies have become mature and most vehicles follow the pre-scheduled route suggested by a navigation system, it is likely to predict the traffic jam accurately if the navigation system can know the pre-scheduled route of each vehicle. Recently, a navigation algorithm is presented for automated driving vehicles with the assumption that all the navigating query requests are processed by a single system. However, the aforementioned algorithm does not consider any kind of uncertainty originating from accidents and destination change. To get close to the real world, we propose a navigation algorithm with near-future evaluation capability that also allows some kinds of uncertainties. We compare our algorithm with a dynamic-update based conventional navigation algorithm without near-future evaluation capability. We download some metropolitan maps from OpenStreetMap and utilize the data of traffic flow from official statistics to randomly generate many sets queries. Experimental results show that the total cruising time is improved for each case.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"43 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124471593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：