Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357290
M. Elghazali, M. Sachdev, A. Opal
In this paper, a low-leakage PMOS based transient clamp with a thyristor as a delay element in 65 nm general-purpose (GP) CMOS technology is presented. Simulation results show that the proposed clamp is capable of protecting the circuit core against ±1.5 kV HBM and ±125 V CDM ESD stress by limiting the voltage across it to less than 5 V. The proposed clamp was characterized over PVT conditions with 2200 different combinations to investigate the selectivity to power-on ramp rates. Extensive analysis and measurements demonstrate that the clamp is robust against false triggering and transient induced latch-up. Measurement results show that the clamp is capable of handling 3.82 A, while its leakage is only 494 pA at room temperature. HBM and CDM measurement results show that the proposed clamp passed +3.25 kV and −1.75 kV HBM stresses and +800 V and −550 V CDM stresses.
本文提出了一种以可控硅作为延迟元件的低漏PMOS暂态箝位电路，采用65nm通用CMOS技术。仿真结果表明，所提出的箝位能够通过将其上的电压限制在5 V以下来保护电路铁芯免受±1.5 kV HBM和±125 V CDM ESD应力的影响。该夹具在2200种不同组合的PVT条件下进行了表征，以研究其对上电斜坡速率的选择性。广泛的分析和测量表明，该夹具具有抗误触发和瞬态诱发闭锁的鲁棒性。测量结果表明，该钳能够处理3.82 A，而其漏电流在室温下仅为494 pA。HBM和CDM测量结果表明，所提出的箝位可以通过+3.25 kV和- 1.75 kV HBM应力和+800 V和- 550 V CDM应力。
{"title":"An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology","authors":"M. Elghazali, M. Sachdev, A. Opal","doi":"10.1109/ISQED.2018.8357290","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357290","url":null,"abstract":"In this paper, a low-leakage PMOS based transient clamp with a thyristor as a delay element in 65 nm general-purpose (GP) CMOS technology is presented. Simulation results show that the proposed clamp is capable of protecting the circuit core against ±1.5 kV HBM and ±125 V CDM ESD stress by limiting the voltage across it to less than 5 V. The proposed clamp was characterized over PVT conditions with 2200 different combinations to investigate the selectivity to power-on ramp rates. Extensive analysis and measurements demonstrate that the clamp is robust against false triggering and transient induced latch-up. Measurement results show that the clamp is capable of handling 3.82 A, while its leakage is only 494 pA at room temperature. HBM and CDM measurement results show that the proposed clamp passed +3.25 kV and −1.75 kV HBM stresses and +800 V and −550 V CDM stresses.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116738917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357259
Horaira Abu, S. Abdennadher, B. Provost, H. Muljono
Based on technical and functional evaluation of high volume products returned from customers, Electrostatic Discharge (ESD) and Electrical Overstress (EOS) induced damages are the two significant causes of customer return in recent times. These customer returns are expected to rise as silicon scales down, as devices are becoming more susceptible to EOS. With ESD diodes ubiquitously being used as the protection device for IC Input/Output (I/O) pin, there is a lack of on-die test structures to validate these circuits automatically. Concerned by zero defect targets and high EOS failure rate from customers, there is an increasing need to define new test methods and techniques that are able to reproduce EOS failure, improve IC robustness against EOS events and isolate EOS and ESD failures. This paper proposes Design for Test (DFT) techniques that can be used to augment physical analysis used to screen EOS and ESD failures.
{"title":"Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT","authors":"Horaira Abu, S. Abdennadher, B. Provost, H. Muljono","doi":"10.1109/ISQED.2018.8357259","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357259","url":null,"abstract":"Based on technical and functional evaluation of high volume products returned from customers, Electrostatic Discharge (ESD) and Electrical Overstress (EOS) induced damages are the two significant causes of customer return in recent times. These customer returns are expected to rise as silicon scales down, as devices are becoming more susceptible to EOS. With ESD diodes ubiquitously being used as the protection device for IC Input/Output (I/O) pin, there is a lack of on-die test structures to validate these circuits automatically. Concerned by zero defect targets and high EOS failure rate from customers, there is an increasing need to define new test methods and techniques that are able to reproduce EOS failure, improve IC robustness against EOS events and isolate EOS and ESD failures. This paper proposes Design for Test (DFT) techniques that can be used to augment physical analysis used to screen EOS and ESD failures.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129395914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357285
A. Ciprut, E. Friedman
Crossbar arrays based on non-volatile resistive devices such as resistive RAM and phase change memory have become an important technology due to the applications to memory systems. The energy consumption of integrated circuits has become a primary issue due to thermal constraints in high performance systems and limited battery time in mobile and IoT applications. In this paper, the energy efficiency of a crossbar array of a one-selector-one-resistor (1S1R) configuration during a write operation is explored for the V/2 and V/3 bias schemes. The characteristics that affect the most energy efficient bias scheme are demystified. The write energy of a crossbar array is modeled in terms of the array size, number of selected cells, and the nonlinearity factor. For a specific array size and selector technology, the number of selected cells during a write operation can affect the choice of bias scheme. Moreover, the effect of leakage current due to partially biased unselected cells is explored.
{"title":"On the write energy of non-volatile resistive crossbar arrays with selectors","authors":"A. Ciprut, E. Friedman","doi":"10.1109/ISQED.2018.8357285","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357285","url":null,"abstract":"Crossbar arrays based on non-volatile resistive devices such as resistive RAM and phase change memory have become an important technology due to the applications to memory systems. The energy consumption of integrated circuits has become a primary issue due to thermal constraints in high performance systems and limited battery time in mobile and IoT applications. In this paper, the energy efficiency of a crossbar array of a one-selector-one-resistor (1S1R) configuration during a write operation is explored for the V/2 and V/3 bias schemes. The characteristics that affect the most energy efficient bias scheme are demystified. The write energy of a crossbar array is modeled in terms of the array size, number of selected cells, and the nonlinearity factor. For a specific array size and selector technology, the number of selected cells during a write operation can affect the choice of bias scheme. Moreover, the effect of leakage current due to partially biased unselected cells is explored.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133390687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357326
Xiaowei Xu, Tianchen Wang, Q. Lu, Yiyu Shi
Due to the fast growing industry of smart cars and autonomous driving, advanced driver assistance systems (ADAS) with its applications have attracted a lot of attention. As a crucial part of ADAS, obstacle detection has been challenge due to the real-tme and resource-constraint requirements. Cellular neural network (CeNN) has been popular for obstacle detection, however suffers from high computation complexity. In this paper we propose a compressed CeNN framework for real-time ADAS obstacle detection in embedded FPGAs. Particularly, parameter quantizaion is adopted. Parameter quantization quantizes the numbers in CeNN templates to powers of two, so that complex and expensive multiplications can be converted to simple and cheap shift operations, which only require a minimum number of registers and LEs. Experimental results on FPGAs show that our approach can significantly improve the resource utilization, and as a direct consequence a speedup up to 7.8x can be achieved with no performance loss compared with the state-of-the-art implementations.
{"title":"Resource constrained cellular neural networks for real-time obstacle detection using FPGAs","authors":"Xiaowei Xu, Tianchen Wang, Q. Lu, Yiyu Shi","doi":"10.1109/ISQED.2018.8357326","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357326","url":null,"abstract":"Due to the fast growing industry of smart cars and autonomous driving, advanced driver assistance systems (ADAS) with its applications have attracted a lot of attention. As a crucial part of ADAS, obstacle detection has been challenge due to the real-tme and resource-constraint requirements. Cellular neural network (CeNN) has been popular for obstacle detection, however suffers from high computation complexity. In this paper we propose a compressed CeNN framework for real-time ADAS obstacle detection in embedded FPGAs. Particularly, parameter quantizaion is adopted. Parameter quantization quantizes the numbers in CeNN templates to powers of two, so that complex and expensive multiplications can be converted to simple and cheap shift operations, which only require a minimum number of registers and LEs. Experimental results on FPGAs show that our approach can significantly improve the resource utilization, and as a direct consequence a speedup up to 7.8x can be achieved with no performance loss compared with the state-of-the-art implementations.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131518922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357293
Sidhartha Sankar Rout, H. Mondal, Rohan Juneja, G. Harsha, Sujay Deb
Many-core processing platforms are gaining significant interest for a wide range of applications, viz., Internet of Things (IoT), consumer electronics, single-chip cloud computers, supercomputers, defense applications etc. Networks-on-Chip (NoCs) are accepted as the communication backbone for these many-core platforms. However, energy consumption in NoC components still remains considerably high. Specifically for large systems with many nodes in the network, a significant amount of energy is consumed by the communication infrastructure. The usage of the routers and resources associated with it are application dependent and for most applications performance requirements can be met without operating the whole communication infrastructure to its maximum limit. Dynamic reconfigurable system that can switch between both high performance and low power modes will be able to exploit the variable workload conditions provided by different applications. Among all the NoC components, Virtual Channels (VCs) are the most power hungry modules. This paper proposes a dynamic NoC platform (DNoC) that optimizes VC utilization for different applications using a smart router architecture. Power Management Controller (PMC) along with Utilization Computation Unit (UCU) controls and predicts the number of active VCs to achieve the required performance with minimum overhead. In our experiments the proposed solution provides 83.3% power benefit (best case scenario) with negligible throughput penalty compared to a baseline mesh router.
{"title":"Dynamic NoC platform for varied application needs","authors":"Sidhartha Sankar Rout, H. Mondal, Rohan Juneja, G. Harsha, Sujay Deb","doi":"10.1109/ISQED.2018.8357293","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357293","url":null,"abstract":"Many-core processing platforms are gaining significant interest for a wide range of applications, viz., Internet of Things (IoT), consumer electronics, single-chip cloud computers, supercomputers, defense applications etc. Networks-on-Chip (NoCs) are accepted as the communication backbone for these many-core platforms. However, energy consumption in NoC components still remains considerably high. Specifically for large systems with many nodes in the network, a significant amount of energy is consumed by the communication infrastructure. The usage of the routers and resources associated with it are application dependent and for most applications performance requirements can be met without operating the whole communication infrastructure to its maximum limit. Dynamic reconfigurable system that can switch between both high performance and low power modes will be able to exploit the variable workload conditions provided by different applications. Among all the NoC components, Virtual Channels (VCs) are the most power hungry modules. This paper proposes a dynamic NoC platform (DNoC) that optimizes VC utilization for different applications using a smart router architecture. Power Management Controller (PMC) along with Utilization Computation Unit (UCU) controls and predicts the number of active VCs to achieve the required performance with minimum overhead. In our experiments the proposed solution provides 83.3% power benefit (best case scenario) with negligible throughput penalty compared to a baseline mesh router.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131684101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357288
Huan Wang, J. Millithaler, R. Knepper, M. Margala
In this paper, we present a Terahertz (THz) Travelling-Wave-Amplifier (TWA) design using a Ballistic Deflection Transistor (BDT). The BDT is an emerging functional device based on InGaAs/InAlAs/InP, which can operate at THz frequencies. A transistor model is proposed, based on data provided by Monte Carlo simulation. We have developed a new nearly lossless THz transmission line (0.46dB/mm over 0.8–1.5THz simulated in ANSYS HFSS), called Parallel Plate Dielectric Waveguide with Signal line (PPDWS), and we are able to design a 24-stage BDT TWA with an ADS simulated gain over 10dB at 1–1.5THz. This THz BDT amplifier design opens up new possibilities by increasing the speed by 100 times compared to existing technologies.
{"title":"Terahertz travelling wave amplifier design using Ballistic Deflection Transistor","authors":"Huan Wang, J. Millithaler, R. Knepper, M. Margala","doi":"10.1109/ISQED.2018.8357288","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357288","url":null,"abstract":"In this paper, we present a Terahertz (THz) Travelling-Wave-Amplifier (TWA) design using a Ballistic Deflection Transistor (BDT). The BDT is an emerging functional device based on InGaAs/InAlAs/InP, which can operate at THz frequencies. A transistor model is proposed, based on data provided by Monte Carlo simulation. We have developed a new nearly lossless THz transmission line (0.46dB/mm over 0.8–1.5THz simulated in ANSYS HFSS), called Parallel Plate Dielectric Waveguide with Signal line (PPDWS), and we are able to design a 24-stage BDT TWA with an ADS simulated gain over 10dB at 1–1.5THz. This THz BDT amplifier design opens up new possibilities by increasing the speed by 100 times compared to existing technologies.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125341117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357258
Pavan Kumar Javvaji, Basim Shanyour, S. Tragoudas
Due to statistical gate delays, the critical probability of a testable path varies among its test patterns. Thus, the delay defect coverage of a selected set of critical paths depends on the selected test set. A new framework to select a test set for improved delay defect coverage is presented. It uses an algorithm that computes the critical probability of a path by a test pattern and machine learning to identify a small test set that maximizes the combined delay defect coverage. Experimental results show a significant improvement in delay defect coverage over existing static critical path approach.
{"title":"Test set identification for improved delay defect coverage in the presence of statistical delays","authors":"Pavan Kumar Javvaji, Basim Shanyour, S. Tragoudas","doi":"10.1109/ISQED.2018.8357258","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357258","url":null,"abstract":"Due to statistical gate delays, the critical probability of a testable path varies among its test patterns. Thus, the delay defect coverage of a selected set of critical paths depends on the selected test set. A new framework to select a test set for improved delay defect coverage is presented. It uses an algorithm that computes the critical probability of a path by a test pattern and machine learning to identify a small test set that maximizes the combined delay defect coverage. Experimental results show a significant improvement in delay defect coverage over existing static critical path approach.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121638608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357269
P. Chawda
Analog layout design automation has been evolving constantly and several attempts have been made to find a solution for analog synthesis. Due to the complexity of analog design problem it is difficult to find a single approach which can be readily accepted by the industry. The optimization based full analog synthesis tools are quick but does not capture layout engineers' expertise and therefore produce sub optimal layout. The semi-automated layout tools help layout engineers considerably however the layout creation cycle time is still at unacceptable level for time-consuming analog designs. This paper presents a simplified methodology for generating complex analog modules layout using template driven parameterized cells to reduce layout creation cycle time significantly while meeting the layout designers need. The paper discusses step by step approach of developing a placement and routing template to capture layout engineers' expertise for complex analog modules and demonstrates its effectiveness by implementing a triple cascode amplifier super-pCell which is being used in pipeline Analog to Digital Converts. The implemented methodology is very flexible and fully controllable so that designers can easily create a layout with additional design requirements and constraints quickly. The proposed approach is successfully adopted by layout engineers and as a result, the required layout resources for a design are reduced significantly whereas layout engineers' efficiency is improved significantly.
{"title":"A simplified methodology for complex analog module layout generation","authors":"P. Chawda","doi":"10.1109/ISQED.2018.8357269","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357269","url":null,"abstract":"Analog layout design automation has been evolving constantly and several attempts have been made to find a solution for analog synthesis. Due to the complexity of analog design problem it is difficult to find a single approach which can be readily accepted by the industry. The optimization based full analog synthesis tools are quick but does not capture layout engineers' expertise and therefore produce sub optimal layout. The semi-automated layout tools help layout engineers considerably however the layout creation cycle time is still at unacceptable level for time-consuming analog designs. This paper presents a simplified methodology for generating complex analog modules layout using template driven parameterized cells to reduce layout creation cycle time significantly while meeting the layout designers need. The paper discusses step by step approach of developing a placement and routing template to capture layout engineers' expertise for complex analog modules and demonstrates its effectiveness by implementing a triple cascode amplifier super-pCell which is being used in pipeline Analog to Digital Converts. The implemented methodology is very flexible and fully controllable so that designers can easily create a layout with additional design requirements and constraints quickly. The proposed approach is successfully adopted by layout engineers and as a result, the required layout resources for a design are reduced significantly whereas layout engineers' efficiency is improved significantly.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115613647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357304
Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, M. Stan
The Internet of Things (IoT) brings a paradigm where humans and “things” are connected. Reliability of these devices becomes extremely critical. Circuit aging has become a limiting factor in technology scaling and a significant challenge in designing IoT systems for reliability-critical applications. As IoT becomes a general-purpose technology which starts to adapt to the advanced process nodes, it is necessary to understand how and on what level aging affects different categories of IoT applications. Since aging is highly dependent on operating conditions and switching activities, this paper classifies the IoT applications based on the aging-related metrics and studies aging using the foundry-provided FinFET aging models. We show that for many IoT applications, aging will indeed add to the already tight design margin. As the expected chip lifetime in IoT devices becomes much longer and the failure tolerant requirements of these applications become much more strict, we conclude that aging needs to be considered in the full design cycle and the IoT lifetime estimation needs to incorporate aging as an important factor. We also present application-specific solutions to mitigate circuit aging in IoT systems.
{"title":"When “things” get older: Exploring circuit aging in IoT applications","authors":"Xinfei Guo, Vaibhav Verma, Patricia Gonzalez-Guerrero, M. Stan","doi":"10.1109/ISQED.2018.8357304","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357304","url":null,"abstract":"The Internet of Things (IoT) brings a paradigm where humans and “things” are connected. Reliability of these devices becomes extremely critical. Circuit aging has become a limiting factor in technology scaling and a significant challenge in designing IoT systems for reliability-critical applications. As IoT becomes a general-purpose technology which starts to adapt to the advanced process nodes, it is necessary to understand how and on what level aging affects different categories of IoT applications. Since aging is highly dependent on operating conditions and switching activities, this paper classifies the IoT applications based on the aging-related metrics and studies aging using the foundry-provided FinFET aging models. We show that for many IoT applications, aging will indeed add to the already tight design margin. As the expected chip lifetime in IoT devices becomes much longer and the failure tolerant requirements of these applications become much more strict, we conclude that aging needs to be considered in the full design cycle and the IoT lifetime estimation needs to incorporate aging as an important factor. We also present application-specific solutions to mitigate circuit aging in IoT systems.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123618333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-13DOI: 10.1109/ISQED.2018.8357314
A. Prasad, P. Chawda
Internet of Things (IoT) is a system that renders the ability to exchange information and actions in an amalgamated environment consisting of machines and humans over a network. Such extraction of information flow through network will optimize the limitations of the physical world. A key player in the realization of IoT system is power management. In this paper, the need for power management in an application based IoT design is motivated. The paper outlines the factors concerning power management in IoT design for example, aging in battery sources, sleep and shutdown mode of operation, etc. Furthermore, the paper reviews some of the techniques like power grating, maximum power point tracking, etc. for currently used power sources that aid to enhance the performance of the system. The technical challenges faced in the IoT field for circuit power up and battery lives have also been discussed. Since power is imperative in variegated engineering disciplines all around the field of science and also is a fundamental prerequisite for the IoT system design. Wireless sensors, servers, Ethernet, and smart appliances, as a part of an IoT based solution are all affected by the scope of power management. With the novel IoT solutions operating under the absence of human intervention at data collection stage, it is crucial for the devices to be powered up smartly to offer accurate results and good performance.
{"title":"Power management factors and techniques for IoT design devices","authors":"A. Prasad, P. Chawda","doi":"10.1109/ISQED.2018.8357314","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357314","url":null,"abstract":"Internet of Things (IoT) is a system that renders the ability to exchange information and actions in an amalgamated environment consisting of machines and humans over a network. Such extraction of information flow through network will optimize the limitations of the physical world. A key player in the realization of IoT system is power management. In this paper, the need for power management in an application based IoT design is motivated. The paper outlines the factors concerning power management in IoT design for example, aging in battery sources, sleep and shutdown mode of operation, etc. Furthermore, the paper reviews some of the techniques like power grating, maximum power point tracking, etc. for currently used power sources that aid to enhance the performance of the system. The technical challenges faced in the IoT field for circuit power up and battery lives have also been discussed. Since power is imperative in variegated engineering disciplines all around the field of science and also is a fundamental prerequisite for the IoT system design. Wireless sensors, servers, Ethernet, and smart appliances, as a part of an IoT based solution are all affected by the scope of power management. With the novel IoT solutions operating under the absence of human intervention at data collection stage, it is crucial for the devices to be powered up smartly to offer accurate results and good performance.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128281813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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