Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357261
Juyeon Kim, Taewhan Kim
This work addresses a new problem of dynamic voltage scaling (DVS) in multicore platforms. We solve the multicore DVS problem, i.e., simultaneously scheduling execution of tasks assigned to cores and determining dynamically-varying voltage levels, with the objective of minimizing total energy consumption of the cores and voltage regulators (VRs) in the reconfigurable VR-to-core power distribution network (PDN) of platform while meeting the arrival/deadline constraint of tasks. Here, the key factors to be exploited for energy saving are (1) available voltage levels, (2) power conversion efficiency curve of VRs, and (3) turning on/off VRs. Specifically, we formulate the problem of task scheduling with the relation between factors 1, 2, and 3 into a linear programming problem and solve optimally in polynomial time.
{"title":"Energy-optimal dynamic voltage scaling in multicore platforms with reconfigurable power distribution network","authors":"Juyeon Kim, Taewhan Kim","doi":"10.1109/ISQED.2018.8357261","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357261","url":null,"abstract":"This work addresses a new problem of dynamic voltage scaling (DVS) in multicore platforms. We solve the multicore DVS problem, i.e., simultaneously scheduling execution of tasks assigned to cores and determining dynamically-varying voltage levels, with the objective of minimizing total energy consumption of the cores and voltage regulators (VRs) in the reconfigurable VR-to-core power distribution network (PDN) of platform while meeting the arrival/deadline constraint of tasks. Here, the key factors to be exploited for energy saving are (1) available voltage levels, (2) power conversion efficiency curve of VRs, and (3) turning on/off VRs. Specifically, we formulate the problem of task scheduling with the relation between factors 1, 2, and 3 into a linear programming problem and solve optimally in polynomial time.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123549408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357298
P. Mroszczyk, V. Pavlidis
This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-of-concept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4∗ higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.
{"title":"Ultra-low swing CMOS transceiver for 2.5-D integrated systems","authors":"P. Mroszczyk, V. Pavlidis","doi":"10.1109/ISQED.2018.8357298","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357298","url":null,"abstract":"This paper presents the design of a low swing transceiver for chip-to-chip communication in 2.5-D integrated systems using a passive interposer. High speed and low power operation is achieved through a new dynamic low swing tunable transmitter (DLST-TX) and inverter-based tunable receiver (INVT-RX) circuits. The novelty of the proposed solution lies in the digital trimming for PVT corners and random parameter variability allowing significant reduction of the voltage swing down to 120 mV with single ended signaling. The compensation method has negligible impact on the circuit performance and silicon area, not typically achievable by device geometry scaling. The proof-of-concept transceiver is implemented in a 65 nm CMOS technology and exhibits up to 4∗ higher energy efficiency at 1 Gb/s speed for 2.5 mm long chip-to-chip interconnect, as compared to state-of-the-art full swing communication schemes operating under the same conditions. The transceiver is suitable for parallel interfaces in 2.5-D integrated systems.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130492252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357325
Mihir Mody, Kumar Desappan, P. Swami, Manu Mathew, S. Nagori
Automated driving functions, like highway driving and parking assist, are increasingly getting deployed in high-end cars with the ultimate goal of realizing self-driving car using Deep learning techniques like convolution neural network (CNN). For mass-market deployment, the embedded solution is required to address the right cost and performance envelope along with security and safety. In the case of automated driving, one of the key functionality is “finding drivable free space”, which is addressed using deep learning techniques like CNN. These CNN networks pose huge computing requirements in terms of hundreds of GOPS/TOPS (Giga or Tera operations per second), which seems beyond the capability of today's embedded SoC. This paper covers various techniques consisting of fixed-point conversion, sparse multiplication, fusing of layers and network pruning, for tailoring on the embedded solution. These techniques are implemented on the device by means of optimized Deep learning library for inference. The paper concludes by demonstrating the results of a CNN network running in real time on TI's TDA2X embedded platform producing a high-quality drivable space output for automated driving.
{"title":"Low cost and power CNN/deep learning solution for automated driving","authors":"Mihir Mody, Kumar Desappan, P. Swami, Manu Mathew, S. Nagori","doi":"10.1109/ISQED.2018.8357325","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357325","url":null,"abstract":"Automated driving functions, like highway driving and parking assist, are increasingly getting deployed in high-end cars with the ultimate goal of realizing self-driving car using Deep learning techniques like convolution neural network (CNN). For mass-market deployment, the embedded solution is required to address the right cost and performance envelope along with security and safety. In the case of automated driving, one of the key functionality is “finding drivable free space”, which is addressed using deep learning techniques like CNN. These CNN networks pose huge computing requirements in terms of hundreds of GOPS/TOPS (Giga or Tera operations per second), which seems beyond the capability of today's embedded SoC. This paper covers various techniques consisting of fixed-point conversion, sparse multiplication, fusing of layers and network pruning, for tailoring on the embedded solution. These techniques are implemented on the device by means of optimized Deep learning library for inference. The paper concludes by demonstrating the results of a CNN network running in real time on TI's TDA2X embedded platform producing a high-quality drivable space output for automated driving.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"455 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133524297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357317
Raghav Mehta, Yuyang Huang, Mingxi Cheng, S. Bagga, Nishant Mathur, Ji Li, J. Draper, Shahin Nazarian
Recently, Deep Neural Networks (DNNs) have made unprecedented progress in various tasks. However, there is a timely need to accelerate the training process in DNNs specifically for real-time applications that demand high performance, energy efficiency and compactness. Numerous algorithms have been proposed to improve the accuracy, however the network training process is computationally slow. In this paper, we present a scalable pipelined hardware architecture with distributed memories for a digital neuron to implement deep neural networks. We also explore various functions and algorithms as well as different memory topologies, to optimize the performance of our training architecture. The power, area, and delay of our proposed model are evaluated with respect to software implementation. Experimental results on the MNIST dataset demonstrate that compared with the software training, our proposed hardware-based approach for training process achieves 33X runtime reduction, 5X power reduction, and nearly 168X energy reduction.
{"title":"High performance training of deep neural networks using pipelined hardware acceleration and distributed memory","authors":"Raghav Mehta, Yuyang Huang, Mingxi Cheng, S. Bagga, Nishant Mathur, Ji Li, J. Draper, Shahin Nazarian","doi":"10.1109/ISQED.2018.8357317","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357317","url":null,"abstract":"Recently, Deep Neural Networks (DNNs) have made unprecedented progress in various tasks. However, there is a timely need to accelerate the training process in DNNs specifically for real-time applications that demand high performance, energy efficiency and compactness. Numerous algorithms have been proposed to improve the accuracy, however the network training process is computationally slow. In this paper, we present a scalable pipelined hardware architecture with distributed memories for a digital neuron to implement deep neural networks. We also explore various functions and algorithms as well as different memory topologies, to optimize the performance of our training architecture. The power, area, and delay of our proposed model are evaluated with respect to software implementation. Experimental results on the MNIST dataset demonstrate that compared with the software training, our proposed hardware-based approach for training process achieves 33X runtime reduction, 5X power reduction, and nearly 168X energy reduction.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"28 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114359606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357296
Zuitoku Shin, Shumpei Morita, S. Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
The degradation of transistors in integrated circuits is known to be dependent on stress frequency in addition to the well-known stress duty cycle. This paper analyzes the impact of frequency dependence of the NBTI degradation on a processor-scale circuit under various workload scenarios by using different levels of available information. A simple estimation for wire switching frequency from duty cycle is also proposed. Using real workloads running on MIPS processor, it is found that frequency dependency of the worst path delay is not large since there are many DC stress components independent of frequency. However, frequency dependency of path delay increases when DC component decreases due to execution of multiple applications.
{"title":"A study on NBTI-induced delay degradation considering stress frequency dependence","authors":"Zuitoku Shin, Shumpei Morita, S. Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato","doi":"10.1109/ISQED.2018.8357296","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357296","url":null,"abstract":"The degradation of transistors in integrated circuits is known to be dependent on stress frequency in addition to the well-known stress duty cycle. This paper analyzes the impact of frequency dependence of the NBTI degradation on a processor-scale circuit under various workload scenarios by using different levels of available information. A simple estimation for wire switching frequency from duty cycle is also proposed. Using real workloads running on MIPS processor, it is found that frequency dependency of the worst path delay is not large since there are many DC stress components independent of frequency. However, frequency dependency of path delay increases when DC component decreases due to execution of multiple applications.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122058108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357275
Sara Karimi, Jelena Trajkovic
Multicore systems are becoming state-of-the-art and therefore need fast and energy efficient interconnects to take full advantage of the computational capabilities. Integration of silicon photonics with traditional electrical interconnect in Network on Chip (NoC) proposes a promising solution for overcoming the scalability issues of electrical interconnect. In this paper, we implement the simulation model for two Optical NoC architectures and compare their performance. We also derive and evaluate a prediction modeling technique for the design space exploration of ONoCs. Our proposed model accurately predicts packet latency, static and dynamic energy consumption of the network. This work specifically addresses the challenge of accurately estimating performance metrics without having to incur high costs of exhaustive simulations. Our case study shows that by using only 10% of the entire design space, our proposed technique builds a prediction model that achieved average error rates as low as 5.44%, 2.67% and 3.24% for network packet latency, static and dynamic energy consumption respectively in six different benchmarks from Splash-2 benchmark suite.
{"title":"Comparative study and prediction modeling of photonic ring Network on Chip architectures","authors":"Sara Karimi, Jelena Trajkovic","doi":"10.1109/ISQED.2018.8357275","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357275","url":null,"abstract":"Multicore systems are becoming state-of-the-art and therefore need fast and energy efficient interconnects to take full advantage of the computational capabilities. Integration of silicon photonics with traditional electrical interconnect in Network on Chip (NoC) proposes a promising solution for overcoming the scalability issues of electrical interconnect. In this paper, we implement the simulation model for two Optical NoC architectures and compare their performance. We also derive and evaluate a prediction modeling technique for the design space exploration of ONoCs. Our proposed model accurately predicts packet latency, static and dynamic energy consumption of the network. This work specifically addresses the challenge of accurately estimating performance metrics without having to incur high costs of exhaustive simulations. Our case study shows that by using only 10% of the entire design space, our proposed technique builds a prediction model that achieved average error rates as low as 5.44%, 2.67% and 3.24% for network packet latency, static and dynamic energy consumption respectively in six different benchmarks from Splash-2 benchmark suite.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123015454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357295
Mami Miyamoto, K. Hamaguchi
Various mining approaches have been proposed for the automatic generation of temporal assertions from execution traces of hardware designs. These approaches can handle assertions based on LTL formulas or PSL, and many of them can represent word-level relations such as inequalities, additions, and so on. In the existing methods, however, such relations are searched only within a clock cycle. They cannot extract a property such that two values at inputs are added, and its result appears two clock cycles later at an output. We propose a method to extract relations over multiple clock cycles between variables as atomic propositions by analyzing execution traces and to generate assertions including the relations. Our method can also efficiently generate assertions by extracting frequent relations between atomic propositions over multiple clock cycles as propositions, that is, conjunctives of atomic propositions. The experimental results demonstrate the feasibility of the proposed method.
{"title":"Extracting hardware assertions including word-level relations over multiple clock cycles","authors":"Mami Miyamoto, K. Hamaguchi","doi":"10.1109/ISQED.2018.8357295","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357295","url":null,"abstract":"Various mining approaches have been proposed for the automatic generation of temporal assertions from execution traces of hardware designs. These approaches can handle assertions based on LTL formulas or PSL, and many of them can represent word-level relations such as inequalities, additions, and so on. In the existing methods, however, such relations are searched only within a clock cycle. They cannot extract a property such that two values at inputs are added, and its result appears two clock cycles later at an output. We propose a method to extract relations over multiple clock cycles between variables as atomic propositions by analyzing execution traces and to generate assertions including the relations. Our method can also efficiently generate assertions by extracting frequent relations between atomic propositions over multiple clock cycles as propositions, that is, conjunctives of atomic propositions. The experimental results demonstrate the feasibility of the proposed method.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121410179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357301
H. Afzali-Kusha, A. Shafaei, M. Pedram
This paper proposes a robust and energy-efficient hybrid TFET-FinFET 6T SRAM cell which takes advantage of the higher ON/OFF current ratio of TFETs compared to that of FinFETs to reliably hold and access data at ultra-low supply voltages. More precisely, in the proposed hybrid cell, to achieve low static currents along with high noise margins, TFETs are used for cross-coupled inverters, and to speed up the access time, high-performance FinFETs are utilized for access transistors. The paper also presents a dual-Vt 6T SRAM, in which low-power (high-Vt) and high-performance (low-Vt) FinFETs are used for cross-coupled inverters and access transistors, respectively. For both SRAM cells, the Vdd boost read-assist technique is employed to improve the read stability. Characteristics of both SRAMs are analyzed using HSPICE simulations for technologies with the gate length of 20 nm for a 128times 128 SRAM array. Simulation results reveal that the lowest operating Vdd for the dual-Vt cell is 225 mV, whereas that of the hybrid cell is 125 mV. Moreover, to further decrease the access delay of the hybrid cell for 125 mV ≤ Vdd ≤ 225 mV, negative Gnd read-assist technique and a boosted voltage for the row decoder are used. Finally, the paper presents a 125mV 2ns-access-time 16Kb SRAM array based on the proposed hybrid TFET-FinFET SRAM cell.
{"title":"A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell","authors":"H. Afzali-Kusha, A. Shafaei, M. Pedram","doi":"10.1109/ISQED.2018.8357301","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357301","url":null,"abstract":"This paper proposes a robust and energy-efficient hybrid TFET-FinFET 6T SRAM cell which takes advantage of the higher ON/OFF current ratio of TFETs compared to that of FinFETs to reliably hold and access data at ultra-low supply voltages. More precisely, in the proposed hybrid cell, to achieve low static currents along with high noise margins, TFETs are used for cross-coupled inverters, and to speed up the access time, high-performance FinFETs are utilized for access transistors. The paper also presents a dual-Vt 6T SRAM, in which low-power (high-Vt) and high-performance (low-Vt) FinFETs are used for cross-coupled inverters and access transistors, respectively. For both SRAM cells, the Vdd boost read-assist technique is employed to improve the read stability. Characteristics of both SRAMs are analyzed using HSPICE simulations for technologies with the gate length of 20 nm for a 128times 128 SRAM array. Simulation results reveal that the lowest operating Vdd for the dual-Vt cell is 225 mV, whereas that of the hybrid cell is 125 mV. Moreover, to further decrease the access delay of the hybrid cell for 125 mV ≤ Vdd ≤ 225 mV, negative Gnd read-assist technique and a boosted voltage for the row decoder are used. Finally, the paper presents a 125mV 2ns-access-time 16Kb SRAM array based on the proposed hybrid TFET-FinFET SRAM cell.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123156287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357297
M. Fakhruddin, Kuok-Khian Lo, J. Karp, M. Hart, Min-Hsing P. Chen
The proposed verification methodology enables designers to meet a maximum resistance specification for the well taps routing. Key strengths of the flow are: automatic identification of both well taps and VDD/VSS grid; comparison of the extracted resistance to a user defined specification value; review of results with a graphical interface; no marker layers to identify the extraction path.
{"title":"Verification methodology to guarantee low routing resistance to well taps","authors":"M. Fakhruddin, Kuok-Khian Lo, J. Karp, M. Hart, Min-Hsing P. Chen","doi":"10.1109/ISQED.2018.8357297","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357297","url":null,"abstract":"The proposed verification methodology enables designers to meet a maximum resistance specification for the well taps routing. Key strengths of the flow are: automatic identification of both well taps and VDD/VSS grid; comparison of the extracted resistance to a user defined specification value; review of results with a graphical interface; no marker layers to identify the extraction path.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127801198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/ISQED.2018.8357291
Ujas Patel, S. Nimmalapudi, H. Stiegler, A. Marshall, Keith Jarreau
Consideration of random device mismatch is an important factor in the design of high performance analog circuits. Floating gate transistors have long been used for digital nonvolatile memory applications (such as flash memory), but a variant to this technology using an “analog floating gate” allows for higher precision programming. Analog floating gate devices can address mismatch observed in small geometry analog circuits. Enabling smaller devices to be used allows lower operating currents and higher frequencies. This property is exploited here to compensate for input mismatch and device parameter variations in an Operational Transconductance Amplifier.
{"title":"Enhancing circuit operation using analog floating gates","authors":"Ujas Patel, S. Nimmalapudi, H. Stiegler, A. Marshall, Keith Jarreau","doi":"10.1109/ISQED.2018.8357291","DOIUrl":"https://doi.org/10.1109/ISQED.2018.8357291","url":null,"abstract":"Consideration of random device mismatch is an important factor in the design of high performance analog circuits. Floating gate transistors have long been used for digital nonvolatile memory applications (such as flash memory), but a variant to this technology using an “analog floating gate” allows for higher precision programming. Analog floating gate devices can address mismatch observed in small geometry analog circuits. Enabling smaller devices to be used allows lower operating currents and higher frequencies. This property is exploited here to compensate for input mismatch and device parameter variations in an Operational Transconductance Amplifier.","PeriodicalId":213351,"journal":{"name":"2018 19th International Symposium on Quality Electronic Design (ISQED)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114086425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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