Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301580
Tanusree Kaibartta, G. Biswas, D. K. Das
The possibility of 3D integrated circuit (3D IC) has been considered as a choice to overcome the difficulties faced by two-dimensional integrated circuits (2D IC). Several technologies exist to connect the layers in 3D IC. Among these technologies through-silicon vias (TSVs) is the promising one since it helps to reduce interconnect length, delays and power consumption. In spite of the advantages it introduces different types of defects which ultimately make an entire IC faulty. Thus, testing of TSVs is an important necessity. Depending on the timing, the testing may be of two types -pre-bond and post-bond. In pre-bond TSV testing TSVs are tested in sessions. In this paper our objective is to reduce the pre-bond TSV test sessions as much as possible, so that overall testing time decreases. To reduce test sessions we need to reduce the individual TSV testing and increase group wise TSV testing.
{"title":"Heuristic Approach for Identification of Random TSV Defects in 3D IC During Pre-bond Testing","authors":"Tanusree Kaibartta, G. Biswas, D. K. Das","doi":"10.1109/ATS49688.2020.9301580","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301580","url":null,"abstract":"The possibility of 3D integrated circuit (3D IC) has been considered as a choice to overcome the difficulties faced by two-dimensional integrated circuits (2D IC). Several technologies exist to connect the layers in 3D IC. Among these technologies through-silicon vias (TSVs) is the promising one since it helps to reduce interconnect length, delays and power consumption. In spite of the advantages it introduces different types of defects which ultimately make an entire IC faulty. Thus, testing of TSVs is an important necessity. Depending on the timing, the testing may be of two types -pre-bond and post-bond. In pre-bond TSV testing TSVs are tested in sessions. In this paper our objective is to reduce the pre-bond TSV test sessions as much as possible, so that overall testing time decreases. To reduce test sessions we need to reduce the individual TSV testing and increase group wise TSV testing.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":" 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132158920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301561
A. Alamgir, A. A'Ain, Norlina Paraman, U. U. Sheikh, I. Grout
Determination of the most appropriate test set is a critical task for high fault coverage in digital testing. Linear feedback shift registers (LFSR) is a common choice to generate pseudo-random patterns for any circuit under test. However, literature shows that pseudo-random generation is incapable of achieving high fault coverage in complex circuits under test. Moreover, a proportional amount of LFSR hardware is loaded with additional circuitry to implement weighted random and mixed-mode reseeding techniques. Despite dense research around weighted random and mixed-mode reseeding techniques, test pattern generation remains a high-cost block in built-in self-test architectures. This research paper uses the parallel concatenation of LFSRs to propose a simple, uniform, and scalable test pattern generator architecture for BIST applications. The proposed test pattern generator reduces the large use of memory elements in an LFSR. Moreover, the parallel concatenation of LFSRs enables the test pattern generator to supply divergent test sequences for comparatively high fault coverage. Fault simulations on combinational profiles of ISCAS’89 benchmark circuits show higher fault coverage with low hardware overhead as compared to standard LFSR.
{"title":"A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications","authors":"A. Alamgir, A. A'Ain, Norlina Paraman, U. U. Sheikh, I. Grout","doi":"10.1109/ATS49688.2020.9301561","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301561","url":null,"abstract":"Determination of the most appropriate test set is a critical task for high fault coverage in digital testing. Linear feedback shift registers (LFSR) is a common choice to generate pseudo-random patterns for any circuit under test. However, literature shows that pseudo-random generation is incapable of achieving high fault coverage in complex circuits under test. Moreover, a proportional amount of LFSR hardware is loaded with additional circuitry to implement weighted random and mixed-mode reseeding techniques. Despite dense research around weighted random and mixed-mode reseeding techniques, test pattern generation remains a high-cost block in built-in self-test architectures. This research paper uses the parallel concatenation of LFSRs to propose a simple, uniform, and scalable test pattern generator architecture for BIST applications. The proposed test pattern generator reduces the large use of memory elements in an LFSR. Moreover, the parallel concatenation of LFSRs enables the test pattern generator to supply divergent test sequences for comparatively high fault coverage. Fault simulations on combinational profiles of ISCAS’89 benchmark circuits show higher fault coverage with low hardware overhead as compared to standard LFSR.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130667505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301524
Chee Hoo Kok, Soon Ee Ong
The major challenge when migrating platform to satisfy the current and future computing demands is to decide which is the most optimal option for migration. Without actually executing the workload in a platform, it is difficult to know the workload performance in the platform. However, comparing the workload performances between different platforms by testing the workload is very tedious and time consuming. This motivates us to design a modeling framework to predict the workload performance of CPU on different platforms without executing. The challenge for the modeling lies within the collection of highly correlated data to train a predictive model. In this paper, we present a novel CPU utilization (%CPU) micro-benchmarking method to collect the data needed as a vital step before proceeding to training phase.
{"title":"CPU Utilization Micro-Benchmarking for RealTime Workload Modeling","authors":"Chee Hoo Kok, Soon Ee Ong","doi":"10.1109/ATS49688.2020.9301524","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301524","url":null,"abstract":"The major challenge when migrating platform to satisfy the current and future computing demands is to decide which is the most optimal option for migration. Without actually executing the workload in a platform, it is difficult to know the workload performance in the platform. However, comparing the workload performances between different platforms by testing the workload is very tedious and time consuming. This motivates us to design a modeling framework to predict the workload performance of CPU on different platforms without executing. The challenge for the modeling lies within the collection of highly correlated data to train a predictive model. In this paper, we present a novel CPU utilization (%CPU) micro-benchmarking method to collect the data needed as a vital step before proceeding to training phase.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128713230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ats49688.2020.9301573
{"title":"[Copyright notice]","authors":"","doi":"10.1109/ats49688.2020.9301573","DOIUrl":"https://doi.org/10.1109/ats49688.2020.9301573","url":null,"abstract":"","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114481974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301553
Jun-Yu Yang, Shi-Yu Huang
We present in this paper the first fault and soft error tolerant Delay-Locked Loop (DLL) design, useful for the clock synchronization in a chip incorporating heterogeneous functional dies. In this robust DLL design, we introduce a powerful timing correction scheme to remedy the timing shortfall in a naïve Triple-Module Redundancy (TMR) architecture. Post-layout simulation results using a 90nm CMOS process is used to verify the performance of this design. In addition to the tolerance of randomly injected faults or soft errors, the Maximum Phase-Error can be improved tremendously from 117ps to just 17ps by the proposed timing correction scheme.
{"title":"Fault and Soft Error Tolerant Delay-Locked Loop","authors":"Jun-Yu Yang, Shi-Yu Huang","doi":"10.1109/ATS49688.2020.9301553","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301553","url":null,"abstract":"We present in this paper the first fault and soft error tolerant Delay-Locked Loop (DLL) design, useful for the clock synchronization in a chip incorporating heterogeneous functional dies. In this robust DLL design, we introduce a powerful timing correction scheme to remedy the timing shortfall in a naïve Triple-Module Redundancy (TMR) architecture. Post-layout simulation results using a 90nm CMOS process is used to verify the performance of this design. In addition to the tolerance of randomly injected faults or soft errors, the Maximum Phase-Error can be improved tremendously from 117ps to just 17ps by the proposed timing correction scheme.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126323527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301504
Chih-Yan Liu, Mu-Ting Wu, C. Li, Gaurav Bhargava, Chris Nigh
Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool.
{"title":"Systematic Hold-time Fault Diagnosis and Failure Debug in Production Chips","authors":"Chih-Yan Liu, Mu-Ting Wu, C. Li, Gaurav Bhargava, Chris Nigh","doi":"10.1109/ATS49688.2020.9301504","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301504","url":null,"abstract":"Hold-time faults can occur in complex designs but can be difficult to diagnose. This paper presents a systematic hold-time diagnosis method for logic circuits. A four-phase flow is introduced to solve the problem. The identification phase identifies groups of systematic error logs by systematic errors. The filtering phase builds a majority error log to avoid the effect of random defects. The verification phase verifies that the candidate fault is a hold-time fault and recognizes capture flip-flops. The determination phase determines the fault models and their corresponding faulty flip-flops. Experiments on two industrial cases show the effectiveness of our technique, both of which have been verified through root-cause analysis. The proposed technique outperforms standard diagnosis performed by a commercial tool.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122274131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301535
Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun
In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Various IMC memories using 8T static random access memory (SRAM) cell have been reported. Some of them, the memory array can provide SRAM and ternary content addressable memory (TCAM) function. In this paper, a March-like test algorithm is proposed, which requires 10 × 2p Read/Write operations, (2q + 4m) Compare operation, and (2r+1 + 4m) Erase operations to cover simple SRAM faults and TCAM Comparison faults, for an IMC 8T SRAM providing 2p ×w-bit SRAM and m× 2q−1-bit TCAM, where p = q+r and m = 2r ×w.
{"title":"Testing of Configurable 8T SRAMs for In-Memory Computing","authors":"Jin-Fu Li, Tsai-Ling Tsai, Chun-Lung Hsu, Chi-Tien Sun","doi":"10.1109/ATS49688.2020.9301535","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301535","url":null,"abstract":"In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Various IMC memories using 8T static random access memory (SRAM) cell have been reported. Some of them, the memory array can provide SRAM and ternary content addressable memory (TCAM) function. In this paper, a March-like test algorithm is proposed, which requires 10 × 2p Read/Write operations, (2q + 4m) Compare operation, and (2r+1 + 4m) Erase operations to cover simple SRAM faults and TCAM Comparison faults, for an IMC 8T SRAM providing 2p ×w-bit SRAM and m× 2q−1-bit TCAM, where p = q+r and m = 2r ×w.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129883183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/icedeg48599.2020.9096849
Provides an abstract for each of the tutorial presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
提供每个辅导演讲的摘要，并可包括每个演讲者的专业简历。完整的演讲稿不作为会议论文集的一部分出版。
{"title":"Tutorials","authors":"","doi":"10.1109/icedeg48599.2020.9096849","DOIUrl":"https://doi.org/10.1109/icedeg48599.2020.9096849","url":null,"abstract":"Provides an abstract for each of the tutorial presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"4 14","pages":"i-i"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141217827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-11DOI: 10.1017/S1431927607070766
Alice Dohnalkova, P. Walther, Daniel Studer, K. Mcdonald, P. Midgley
Provides an abstract for each of the tutorial presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.
{"title":"Tutorials","authors":"Alice Dohnalkova, P. Walther, Daniel Studer, K. Mcdonald, P. Midgley","doi":"10.1017/S1431927607070766","DOIUrl":"https://doi.org/10.1017/S1431927607070766","url":null,"abstract":"Provides an abstract for each of the tutorial presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"129 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124589975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：