Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301510
Ming Wang, Jian Xiao, Zhikuang Cai
In this paper, an adaptive scan chain structure based plaintext analysis technique is proposed. The technology is implemented by three circuits, including adaptive scan chain circuit, plaintext analysis circuit and controller circuit. The plaintext is analyzed whether meet the characteristics of the differential cryptanalysis in the plaintext analysis module. The adaptive scan chain contains MUX, XOR and traditional scan chain, which is easy to implement. If the last bit of two plaintexts differs by one, the adaptive scan chain is controlled to input them into different scan chain. Compared with complicated scan chain, the structure of adaptive scan chain is variable and can mislead attackers who use differential cryptanalysis attack. Through experimental analysis, it is proved that the security of the adaptive scan chain structure is greatly improved.
{"title":"An effective technique preventing differential cryptanalysis attack","authors":"Ming Wang, Jian Xiao, Zhikuang Cai","doi":"10.1109/ATS49688.2020.9301510","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301510","url":null,"abstract":"In this paper, an adaptive scan chain structure based plaintext analysis technique is proposed. The technology is implemented by three circuits, including adaptive scan chain circuit, plaintext analysis circuit and controller circuit. The plaintext is analyzed whether meet the characteristics of the differential cryptanalysis in the plaintext analysis module. The adaptive scan chain contains MUX, XOR and traditional scan chain, which is easy to implement. If the last bit of two plaintexts differs by one, the adaptive scan chain is controlled to input them into different scan chain. Compared with complicated scan chain, the structure of adaptive scan chain is variable and can mislead attackers who use differential cryptanalysis attack. Through experimental analysis, it is proved that the security of the adaptive scan chain structure is greatly improved.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"30 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126077901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301569
Aibin Yan, Yan Chen, Jun Zhou, Jie Cui, Tianming Ni, X. Wen, P. Girard
In this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can provide self-recoverability from any single-node upsets (SNUs) and partial double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of six access transistors. Simulation results show that the SCCS18T cell can save approximately 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with typical hardened SRAM cells.
{"title":"A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets","authors":"Aibin Yan, Yan Chen, Jun Zhou, Jie Cui, Tianming Ni, X. Wen, P. Girard","doi":"10.1109/ATS49688.2020.9301569","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301569","url":null,"abstract":"In this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can provide self-recoverability from any single-node upsets (SNUs) and partial double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of six access transistors. Simulation results show that the SCCS18T cell can save approximately 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with typical hardened SRAM cells.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123301342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301589
Arjun Chaudhuri, Sanmitra Banerjee, K. Chakrabarty
Monolithic 3D (M3D) ICs have emerged as a promising technology with significant improvement in power, performance, and area (PPA) over conventional 3D-stacked ICs. However, the sequential assembly of M3D tiers and immature fabrication process are prone to manufacturing defects and intertier process variations. Tier-level fault localization is therefore essential for yield ramp-up and diagnosis. Due to overhead concerns, only a limited number of observation points (OPs) can be inserted on the outgoing inter-layer vias (ILVs) of a tier to enable fault localization. We propose the computationally efficient NodeRank algorithm for observation-point insertion (OPI) on a small subset of outgoing ILVs. An ATPG-independent heuristic is presented, which is several orders-of-magnitude faster than ATPG fault simulation-based OPI. We introduce a metric called degree of fault localization to quantify the effectiveness of OPs. Evaluation results for two-tier M3D benchmark circuits show the effectiveness of the proposed method.
{"title":"NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs∗","authors":"Arjun Chaudhuri, Sanmitra Banerjee, K. Chakrabarty","doi":"10.1109/ATS49688.2020.9301589","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301589","url":null,"abstract":"Monolithic 3D (M3D) ICs have emerged as a promising technology with significant improvement in power, performance, and area (PPA) over conventional 3D-stacked ICs. However, the sequential assembly of M3D tiers and immature fabrication process are prone to manufacturing defects and intertier process variations. Tier-level fault localization is therefore essential for yield ramp-up and diagnosis. Due to overhead concerns, only a limited number of observation points (OPs) can be inserted on the outgoing inter-layer vias (ILVs) of a tier to enable fault localization. We propose the computationally efficient NodeRank algorithm for observation-point insertion (OPI) on a small subset of outgoing ILVs. An ATPG-independent heuristic is presented, which is several orders-of-magnitude faster than ATPG fault simulation-based OPI. We introduce a metric called degree of fault localization to quantify the effectiveness of OPs. Evaluation results for two-tier M3D benchmark circuits show the effectiveness of the proposed method.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125527770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301613
T. Ibuchi, T. Funaki
The fast switching characteristics of silicon carbide (SiC) power devices can be expected to realize low losses, light weight, and compact power converters. However, high dv/dt and di/dt during switching transients raise the concerns of electromagnetic interference (EMI) for high-power converters. This report focuses on the switching characteristics of SiC power devices, and discusses the relationship between their transient characteristics and EMI noise sources for power conversion circuit.
{"title":"EMI characterization for power conversion circuit with SiC power devices","authors":"T. Ibuchi, T. Funaki","doi":"10.1109/ATS49688.2020.9301613","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301613","url":null,"abstract":"The fast switching characteristics of silicon carbide (SiC) power devices can be expected to realize low losses, light weight, and compact power converters. However, high dv/dt and di/dt during switching transients raise the concerns of electromagnetic interference (EMI) for high-power converters. This report focuses on the switching characteristics of SiC power devices, and discusses the relationship between their transient characteristics and EMI noise sources for power conversion circuit.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"134 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120875710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301586
Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang
With the rapid advancements of the artificial intelligence, machine learning, especially neural networks, have shown huge superiority over humans in image recognition, autonomous vehicles and medical diagnosis. However, its opacity and inexplicability provide many chances for malicious attackers. Recent researches have shown that neural networks are vulnerable to adversarial example (AE) attacks. In the testing stage, it fools the model by adding subtle perturbations to the original sample to misclassify the input, which poses a serious threat to safety-critical areas such as autonomous driving. In order to mitigate this threat, this paper proposes a hardware-assisted randomization method against AEs, where an approximate computing technique in hardware, voltage over-scaling (VOS), is used to randomize the training set of the model, then the processed data are used to generate multiple neural network models, finally multiple redundant models are used for the integrated classification and detection of the AEs. Various AE attacks on the proposed defense are evaluated to prove its effectiveness.
{"title":"HRAE: Hardware-assisted Randomization against Adversarial Example Attacks","authors":"Jiliang Zhang, Shuang Peng, Yupeng Hu, Fei Peng, Wei Hu, Jinmei Lai, Jing Ye, Xiangqi Wang","doi":"10.1109/ATS49688.2020.9301586","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301586","url":null,"abstract":"With the rapid advancements of the artificial intelligence, machine learning, especially neural networks, have shown huge superiority over humans in image recognition, autonomous vehicles and medical diagnosis. However, its opacity and inexplicability provide many chances for malicious attackers. Recent researches have shown that neural networks are vulnerable to adversarial example (AE) attacks. In the testing stage, it fools the model by adding subtle perturbations to the original sample to misclassify the input, which poses a serious threat to safety-critical areas such as autonomous driving. In order to mitigate this threat, this paper proposes a hardware-assisted randomization method against AEs, where an approximate computing technique in hardware, voltage over-scaling (VOS), is used to randomize the training set of the model, then the processed data are used to generate multiple neural network models, finally multiple redundant models are used for the integrated classification and detection of the AEs. Various AE attacks on the proposed defense are evaluated to prove its effectiveness.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132157399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301547
Jiang-Tang Xiao, Ting-Shuo Hsu, C. Fuchs, Yu-Teng Chang, J. Liou, Harry H. Chen
Shrinking feature sizes and cell capacitances, lower operation voltages, and higher operation speeds intensify the influences of radiation-induced soft-errors. To guarantee the functional safety of electronic systems, designers need effective techniques to evaluate designs under errors. Fault injection is one of the standard assessment tools for system dependability. However, because traditional RTL fault simulation has become too slow for modern complex systems, we need abstraction models for early-stage system reliability analysis and design. In this paper, we present an accurate reliability assessment SystemC fault simulator. It features a dynamic mechanism for injecting faults and analyzing the produced errors to evaluate possible fault detection and tolerance designs. Our experimental results show that our simulator can achieve 470x speedup on accurate architecture register fault simulation, validated with the RTL model.
{"title":"An ISA-level Accurate Fault Simulator for System-level Fault Analysis","authors":"Jiang-Tang Xiao, Ting-Shuo Hsu, C. Fuchs, Yu-Teng Chang, J. Liou, Harry H. Chen","doi":"10.1109/ATS49688.2020.9301547","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301547","url":null,"abstract":"Shrinking feature sizes and cell capacitances, lower operation voltages, and higher operation speeds intensify the influences of radiation-induced soft-errors. To guarantee the functional safety of electronic systems, designers need effective techniques to evaluate designs under errors. Fault injection is one of the standard assessment tools for system dependability. However, because traditional RTL fault simulation has become too slow for modern complex systems, we need abstraction models for early-stage system reliability analysis and design. In this paper, we present an accurate reliability assessment SystemC fault simulator. It features a dynamic mechanism for injecting faults and analyzing the produced errors to evaluate possible fault detection and tolerance designs. Our experimental results show that our simulator can achieve 470x speedup on accurate architecture register fault simulation, validated with the RTL model.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117173507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301588
Masayuki Gondo, Yousuke Miyake, Takaaki Kato, S. Kajihara
An aging-tolerant ring oscillator (RO) has been proposed for a digital temperature and voltage sensor. This paper discusses on the effectiveness of aging-tolerance of the ROs through accelerated life test for a test chip with 65nm CMOS technology. The progress of delay degradation of the ROs is examined, and influence of delay degradation on measurement accuracy of the sensor is investigated. Experimental results show that the aging-tolerant ROs can mitigate delay degradation, and that the measurement errors of the sensor can be reduced. Compared with a sensor consisting of an aging-intolerant RO, temperature and voltage errors are reduced 2.5°C and 32mV, respectively.
{"title":"On Evaluation for Aging-Tolerant Ring Oscillators with Accelerated Life Test And Its Application to A Digital Sensor","authors":"Masayuki Gondo, Yousuke Miyake, Takaaki Kato, S. Kajihara","doi":"10.1109/ATS49688.2020.9301588","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301588","url":null,"abstract":"An aging-tolerant ring oscillator (RO) has been proposed for a digital temperature and voltage sensor. This paper discusses on the effectiveness of aging-tolerance of the ROs through accelerated life test for a test chip with 65nm CMOS technology. The progress of delay degradation of the ROs is examined, and influence of delay degradation on measurement accuracy of the sensor is investigated. Experimental results show that the aging-tolerant ROs can mitigate delay degradation, and that the measurement errors of the sensor can be reduced. Compared with a sensor consisting of an aging-intolerant RO, temperature and voltage errors are reduced 2.5°C and 32mV, respectively.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132483675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301574
U. VinodG., S. VineeshV., Jaynarayan T. Tudu, M. Fujita, Virendra Singh
Approximate circuits are widely gaining popularity in various fields where error tolerance is applicable. However, striking the right balance between error tolerance and the output quality is a challenging step in the overall design of approximate systems. We propose a systematic approach utilizing Look-Up Table (LUT)-based netlist transformations to achieve approximation while targeting specific error guarantees. Specifically, we employ a SAT-based property checking technique to accommodate worst-case error constraints acting as error guarantees. The proposed methodology involves the formulation of templates to enable the reusability of the technique for different design choices. The analysis comprises of fitness function evaluation based on layout area or the considered error guarantees. We analyze the impact of different parameters on the quality of the output of the resulting approximation and the time taken to obtain them.
{"title":"LUT-based Circuit Approximation with Targeted Error Guarantees","authors":"U. VinodG., S. VineeshV., Jaynarayan T. Tudu, M. Fujita, Virendra Singh","doi":"10.1109/ATS49688.2020.9301574","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301574","url":null,"abstract":"Approximate circuits are widely gaining popularity in various fields where error tolerance is applicable. However, striking the right balance between error tolerance and the output quality is a challenging step in the overall design of approximate systems. We propose a systematic approach utilizing Look-Up Table (LUT)-based netlist transformations to achieve approximation while targeting specific error guarantees. Specifically, we employ a SAT-based property checking technique to accommodate worst-case error constraints acting as error guarantees. The proposed methodology involves the formulation of templates to enable the reusability of the technique for different design choices. The analysis comprises of fitness function evaluation based on layout area or the considered error guarantees. We analyze the impact of different parameters on the quality of the output of the resulting approximation and the time taken to obtain them.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131148874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ATS49688.2020.9301533
Wei Hu, Lingjuan Wu, Yu Tai, Jing Tan, Jiliang Zhang
Taint-propagation and X-propagation analyses are important tools for enforcing circuit design properties such as security and reliability. Fundamental to these tools are effective models for accurately measuring the propagation of information and calculating metadata. In this work, we formalize a unified model for reasoning about taint- and X-propagation behaviors and verifying design properties related to these behaviors. Our model are developed from the perspective of information flow and can be described using standard hardware description language (HDL), which allows formal verification of both taint-propagation (i.e., security) and X-propagation (i.e., reliability) related properties using standard electronic design automation (EDA) verification tools. Experimental results show that our formal model can be used to prove both security and reliability properties in order to uncover unintended design flaw, timing channel and intentional malicious undocumented functionality in circuit designs.
{"title":"A Unified Formal Model for Proving Security and Reliability Properties","authors":"Wei Hu, Lingjuan Wu, Yu Tai, Jing Tan, Jiliang Zhang","doi":"10.1109/ATS49688.2020.9301533","DOIUrl":"https://doi.org/10.1109/ATS49688.2020.9301533","url":null,"abstract":"Taint-propagation and X-propagation analyses are important tools for enforcing circuit design properties such as security and reliability. Fundamental to these tools are effective models for accurately measuring the propagation of information and calculating metadata. In this work, we formalize a unified model for reasoning about taint- and X-propagation behaviors and verifying design properties related to these behaviors. Our model are developed from the perspective of information flow and can be described using standard hardware description language (HDL), which allows formal verification of both taint-propagation (i.e., security) and X-propagation (i.e., reliability) related properties using standard electronic design automation (EDA) verification tools. Experimental results show that our formal model can be used to prove both security and reliability properties in order to uncover unintended design flaw, timing channel and intentional malicious undocumented functionality in circuit designs.","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117158153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-23DOI: 10.1109/ats49688.2020.9301519
{"title":"ATS 2021 Call for Papers","authors":"","doi":"10.1109/ats49688.2020.9301519","DOIUrl":"https://doi.org/10.1109/ats49688.2020.9301519","url":null,"abstract":"","PeriodicalId":220508,"journal":{"name":"2020 IEEE 29th Asian Test Symposium (ATS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124519028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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