Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086641
Ranjith Kumar R, Saranraj B
In this paper image encryption algorithm based on confusion and diffusion using dynamic key space is proposed. Confusion of pixels is done by triangular confusion, method proposed in this work and diffusion is done by values obtained from logistic map iterations. An internal key generator is used to generate the initial seeds for the overall encryption scheme proposed, with these initial seeds, logistic map generates pseudo random numbers which are then converted into Confusion order (CO) for confusion. Confusion order is applied to the blocks which have undergone triangular confusion. The diffusion bits (DFB) are generated in parallel using the logistic map and manipulated with pixels confused according to confusion order. The image pixels are iteratively confused and diffused with CO and DFB respectively to produce cipher image in minimum number of rounds. This work focuses on key generation using logistic and tent maps with iterative reconstruction to secure the image. Chaos based method provides a dynamic changes for confusion and diffusion architecture in the image encryption. A single bit change in the key will dramatically change the result in the internal key generation structure proposed. The simulation results confirm that the satisfactory level security is achieved in three rounds and the overall encryption time is saved.
{"title":"A novel chaotic color image encryption / decryption based on triangular confusion","authors":"Ranjith Kumar R, Saranraj B","doi":"10.1109/ICECCE.2014.7086641","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086641","url":null,"abstract":"In this paper image encryption algorithm based on confusion and diffusion using dynamic key space is proposed. Confusion of pixels is done by triangular confusion, method proposed in this work and diffusion is done by values obtained from logistic map iterations. An internal key generator is used to generate the initial seeds for the overall encryption scheme proposed, with these initial seeds, logistic map generates pseudo random numbers which are then converted into Confusion order (CO) for confusion. Confusion order is applied to the blocks which have undergone triangular confusion. The diffusion bits (DFB) are generated in parallel using the logistic map and manipulated with pixels confused according to confusion order. The image pixels are iteratively confused and diffused with CO and DFB respectively to produce cipher image in minimum number of rounds. This work focuses on key generation using logistic and tent maps with iterative reconstruction to secure the image. Chaos based method provides a dynamic changes for confusion and diffusion architecture in the image encryption. A single bit change in the key will dramatically change the result in the internal key generation structure proposed. The simulation results confirm that the satisfactory level security is achieved in three rounds and the overall encryption time is saved.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131146976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086631
M. Nayana, S. Yellampalli, G. Harish
BIST is one of the DFT techniques in which the test circuitry will be present along with the CUT. Different BIST architectures are proposed in order to reduce the area overhead, power overhead, test time and test costs. The STUMPS architecture is best suited for BIST environment in terms of area and power, but it requires external TPG and Compactor. This paper presents the modified low power STUMPS architecture which eliminates the need for external TPG, by modifying one of the scan chains to operate in both scan and TPG mode. The proposed architecture is tested by considering 16×16 multiplier as CUT and results shows that area overhead is reduced by 4.4 % when compared to STUMPS architecture.
{"title":"Modified low power STUMPS architecture","authors":"M. Nayana, S. Yellampalli, G. Harish","doi":"10.1109/ICECCE.2014.7086631","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086631","url":null,"abstract":"BIST is one of the DFT techniques in which the test circuitry will be present along with the CUT. Different BIST architectures are proposed in order to reduce the area overhead, power overhead, test time and test costs. The STUMPS architecture is best suited for BIST environment in terms of area and power, but it requires external TPG and Compactor. This paper presents the modified low power STUMPS architecture which eliminates the need for external TPG, by modifying one of the scan chains to operate in both scan and TPG mode. The proposed architecture is tested by considering 16×16 multiplier as CUT and results shows that area overhead is reduced by 4.4 % when compared to STUMPS architecture.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122129639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086658
K. Parasuraman, G. Deeparani
In this paper presents a novel reversible watermarking scheme. The proposed scheme use an interpolation technique to generate residual values named as interpolation error. Additionally apply the additive expansion to these interpolation-errors, this project achieve a highly efficient reversible watermarking scheme which can guarantee high image quality without sacrificing embedding capacity. The experimental results show the proposed reversible scheme provides a higher capacity and achieves better image quality for watermarked images. The computational cost of the proposed scheme is small.
{"title":"Reversible image watermarking using interpolation technique","authors":"K. Parasuraman, G. Deeparani","doi":"10.1109/ICECCE.2014.7086658","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086658","url":null,"abstract":"In this paper presents a novel reversible watermarking scheme. The proposed scheme use an interpolation technique to generate residual values named as interpolation error. Additionally apply the additive expansion to these interpolation-errors, this project achieve a highly efficient reversible watermarking scheme which can guarantee high image quality without sacrificing embedding capacity. The experimental results show the proposed reversible scheme provides a higher capacity and achieves better image quality for watermarked images. The computational cost of the proposed scheme is small.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131447544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086657
V. Sailaja, E. R. Harshan, A. Voleti, B. Reddy
Mankind is facing major issues, power shortages is one among them. Instead of going for installations of new power houses substantial use of wastage power can reduce the intensity of the issue. Industries contribute major part of the load in any grid. There will be huge power losses in industrial applications. So, efficient installations of power recovery systems as a part of demand side management will reduce these power shortages to some extent. Almost all industries run on three phase Induction motor which is widely used. In Slip ring Induction motor, rotor terminals are available. Many speed control techniques have been developed because of this facility. One among them is Slip power recovery scheme in which the slip power is recovered and given back to supply. However, when the machine ratings are small to permit such an expensive and complex converters, it is more practicable to recover the slip energy and charge a small battery bank and use it for UPS to feed lighting other low power loads. This proposed work presents a model to use this slip power to charge a battery instead of giving it back to the supply. In this model the motor's rotor winding is connected to a rectifier via slip rings. Power from the rotor winding flows through the three phase rectifier to a switch-mode step up DC to DC converter to re-charge a bank of batteries. A dynamic model of the complete system is presented along with simulation results and hardware implementation.
{"title":"Battery charging using induction motor's Slip power","authors":"V. Sailaja, E. R. Harshan, A. Voleti, B. Reddy","doi":"10.1109/ICECCE.2014.7086657","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086657","url":null,"abstract":"Mankind is facing major issues, power shortages is one among them. Instead of going for installations of new power houses substantial use of wastage power can reduce the intensity of the issue. Industries contribute major part of the load in any grid. There will be huge power losses in industrial applications. So, efficient installations of power recovery systems as a part of demand side management will reduce these power shortages to some extent. Almost all industries run on three phase Induction motor which is widely used. In Slip ring Induction motor, rotor terminals are available. Many speed control techniques have been developed because of this facility. One among them is Slip power recovery scheme in which the slip power is recovered and given back to supply. However, when the machine ratings are small to permit such an expensive and complex converters, it is more practicable to recover the slip energy and charge a small battery bank and use it for UPS to feed lighting other low power loads. This proposed work presents a model to use this slip power to charge a battery instead of giving it back to the supply. In this model the motor's rotor winding is connected to a rectifier via slip rings. Power from the rotor winding flows through the three phase rectifier to a switch-mode step up DC to DC converter to re-charge a bank of batteries. A dynamic model of the complete system is presented along with simulation results and hardware implementation.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":"386 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134544075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086622
P. Samundiswary, R. Surender
Wireless Sensor Networks (WSNs) are an emerging field of engineering with various applications. The motivation is due to the low power and small size sensor nodes used in the network. It has started to emerge as the next generation wireless standard for Low-Rate Wireless Personal Area Networks (LRWPAN). The IEEE 802.15.4 standard is adopted as a communication protocol for LR-WPAN which supports low data rate, less power consumption and short transmission distance. IEEE 802.15.4 is the basis for the Zigbee enabled WSNs. IEEE and ZigBee alliance have joined hands to develop a complete specification of protocol stack for 802.15.4. The Guaranteed Time Slot (GTS) mechanism provided by IEEE 802.15.4 standard allocates specific time slots to all nodes in the network and makes communication more consistent. This consistency makes the network to enhance their performance. In this paper, the performance analysis of GTS mechanism enabled IEEE 802.15.4 based wireless sensor networks using various routing protocols is done by using QualNet. Performance metrics such as packet delivery ratio, delay and packets dropped of IEEE 802.15.4 based wireless sensor networks are analysed using Location Aided Routing (LAR) protocol. Then the performance metrics are then compared with that of DYnamic MANET On-Demand (DYMO) routing protocol.
{"title":"Performance comparison of GTS mechanism enabled IEEE 802.15.4 based Wireless Sensor Networks using LAR and DYMO protocol","authors":"P. Samundiswary, R. Surender","doi":"10.1109/ICECCE.2014.7086622","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086622","url":null,"abstract":"Wireless Sensor Networks (WSNs) are an emerging field of engineering with various applications. The motivation is due to the low power and small size sensor nodes used in the network. It has started to emerge as the next generation wireless standard for Low-Rate Wireless Personal Area Networks (LRWPAN). The IEEE 802.15.4 standard is adopted as a communication protocol for LR-WPAN which supports low data rate, less power consumption and short transmission distance. IEEE 802.15.4 is the basis for the Zigbee enabled WSNs. IEEE and ZigBee alliance have joined hands to develop a complete specification of protocol stack for 802.15.4. The Guaranteed Time Slot (GTS) mechanism provided by IEEE 802.15.4 standard allocates specific time slots to all nodes in the network and makes communication more consistent. This consistency makes the network to enhance their performance. In this paper, the performance analysis of GTS mechanism enabled IEEE 802.15.4 based wireless sensor networks using various routing protocols is done by using QualNet. Performance metrics such as packet delivery ratio, delay and packets dropped of IEEE 802.15.4 based wireless sensor networks are analysed using Location Aided Routing (LAR) protocol. Then the performance metrics are then compared with that of DYnamic MANET On-Demand (DYMO) routing protocol.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114065066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086656
R. Kamal, P. Chandravanshi, N. Jain, Rajkumar
In this paper, an efficient multiplier less finite impulse response (FIR) filter architecture based on distributed arithmetic (DA) using high speed residue number system (RNS) is presented. The proposed architecture uses RNS and parallel DA to increase the speed of the system. The proposed architecture is coded in VHDL and synthesized using Synopsys Design Compiler using SAED 90nm CMOS library to calculate area and delay. Synthesis results show that, the proposed structure using DA-RNS has 77.93% less area-delay-product (ADP) than the design proposed by Chan Hua Vun.
{"title":"Efficient VLSI architecture for FIR filter using DA-RNS","authors":"R. Kamal, P. Chandravanshi, N. Jain, Rajkumar","doi":"10.1109/ICECCE.2014.7086656","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086656","url":null,"abstract":"In this paper, an efficient multiplier less finite impulse response (FIR) filter architecture based on distributed arithmetic (DA) using high speed residue number system (RNS) is presented. The proposed architecture uses RNS and parallel DA to increase the speed of the system. The proposed architecture is coded in VHDL and synthesized using Synopsys Design Compiler using SAED 90nm CMOS library to calculate area and delay. Synthesis results show that, the proposed structure using DA-RNS has 77.93% less area-delay-product (ADP) than the design proposed by Chan Hua Vun.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131645011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086615
K. Anusha, D. Ezhilmaran
Intrusion Detection System is software based monitoring mechanism for a computer network that detects presence of malevolent activity in the network. Intrusion detection is an eminent upcoming area in relevance as more and more complex data is being stored and processed in networked systems. This paper focuses on investigations of well-known machine learning techniques to address the security issues in the MANET networks which are used for detection and classification of attacks: Intuitionistic fuzzy, genetic algorithm RVM (Relevance Vector Machine), and neural network algorithm. Machine Learning techniques can learn normal and anomalous patterns from training data and generate classifiers that then are used to detect attacks on computer systems. The selected attributes were applied to Data Mining Classification Algorithms which helps in bringing out the best and effective Algorithm by making use of the error rates, false positive and packet drop rates.
{"title":"Investigations on Classification Algorithms for Intrusion Detection System in MANETS","authors":"K. Anusha, D. Ezhilmaran","doi":"10.1109/ICECCE.2014.7086615","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086615","url":null,"abstract":"Intrusion Detection System is software based monitoring mechanism for a computer network that detects presence of malevolent activity in the network. Intrusion detection is an eminent upcoming area in relevance as more and more complex data is being stored and processed in networked systems. This paper focuses on investigations of well-known machine learning techniques to address the security issues in the MANET networks which are used for detection and classification of attacks: Intuitionistic fuzzy, genetic algorithm RVM (Relevance Vector Machine), and neural network algorithm. Machine Learning techniques can learn normal and anomalous patterns from training data and generate classifiers that then are used to detect attacks on computer systems. The selected attributes were applied to Data Mining Classification Algorithms which helps in bringing out the best and effective Algorithm by making use of the error rates, false positive and packet drop rates.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":" 19","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132041794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-11-01DOI: 10.1109/ICECCE.2014.7086640
Sourabh Chandra, Smita Paira, S. S. Alam, G. Sanyal
Network security is an important aspect of information sharing. Attempts have been made to remove various insecurities over internet. For this, many technological implementations and security policies have been developed. The amount of data, transferred, is not a factor. The basic factor is, how much security, the channel provides while transmitting data. Cryptography is one such technique, which allows secure data transmission without losing its confidentiality and integrity. Based on the key distribution, cryptography is further classified into two major types-Symmetric Key Cryptography and Asymmetric Key Cryptography. In this paper, we have surveyed the traditional algorithms, along with the proposed algorithms based on their pros and cons, related to Symmetric and Asymmetric Key Cryptography. We have also compared the importance of both these cryptographic techniques. The proposed algorithms proved to be highly efficient in their respective grounds but there are certain areas that remained open, related to these algorithms, and have not yet been thoroughly discussed. This paper also presents an appropriate future scope related to these open fields.
{"title":"A comparative survey of Symmetric and Asymmetric Key Cryptography","authors":"Sourabh Chandra, Smita Paira, S. S. Alam, G. Sanyal","doi":"10.1109/ICECCE.2014.7086640","DOIUrl":"https://doi.org/10.1109/ICECCE.2014.7086640","url":null,"abstract":"Network security is an important aspect of information sharing. Attempts have been made to remove various insecurities over internet. For this, many technological implementations and security policies have been developed. The amount of data, transferred, is not a factor. The basic factor is, how much security, the channel provides while transmitting data. Cryptography is one such technique, which allows secure data transmission without losing its confidentiality and integrity. Based on the key distribution, cryptography is further classified into two major types-Symmetric Key Cryptography and Asymmetric Key Cryptography. In this paper, we have surveyed the traditional algorithms, along with the proposed algorithms based on their pros and cons, related to Symmetric and Asymmetric Key Cryptography. We have also compared the importance of both these cryptographic techniques. The proposed algorithms proved to be highly efficient in their respective grounds but there are certain areas that remained open, related to these algorithms, and have not yet been thoroughly discussed. This paper also presents an appropriate future scope related to these open fields.","PeriodicalId":223751,"journal":{"name":"2014 International Conference on Electronics, Communication and Computational Engineering (ICECCE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128777751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：