Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270535
J. Glagolevs, Kārlis Freivalds
In this paper we present a study of logo detection in images from a media agency. We compare two most widely used methods — HOG and SIFT on a challenging dataset of images arising from a printed press and news portals. Despite common opinion that SIFT method is superior, our results show that HOG method performs significantly better on our dataset. We augment the HOG method with image resizing and rotation to improve its performance even more. We found out that by using such approach it is possible to obtain good results with increased recall and reasonably decreased precision.
{"title":"Logo detection in images using HOG and SIFT","authors":"J. Glagolevs, Kārlis Freivalds","doi":"10.1109/AIEEE.2017.8270535","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270535","url":null,"abstract":"In this paper we present a study of logo detection in images from a media agency. We compare two most widely used methods — HOG and SIFT on a challenging dataset of images arising from a printed press and news portals. Despite common opinion that SIFT method is superior, our results show that HOG method performs significantly better on our dataset. We augment the HOG method with image resizing and rotation to improve its performance even more. We found out that by using such approach it is possible to obtain good results with increased recall and reasonably decreased precision.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130189662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270545
Leonid Kladovscikov, R. Navickas
Integrated circuit fabrication technological processes affect error of transceiver's parameters. Such deviation of parameters are meant to be estimated and tuned up to desired. This paper describes self-test and self-calibration systems of active RC low pass filters. Main parameters to be estimated and tuned are cut-off frequency, gain and band-pass linearity. Self-calibration system is designed in 0.18 μm technology node, with 1.8 V supply voltage for 10 MHz application. Designed self-calibration system tuning accuracy varies from 0.8 % to 1 %.
{"title":"Design of self-test and self-calibration systems for analog active RC filters","authors":"Leonid Kladovscikov, R. Navickas","doi":"10.1109/AIEEE.2017.8270545","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270545","url":null,"abstract":"Integrated circuit fabrication technological processes affect error of transceiver's parameters. Such deviation of parameters are meant to be estimated and tuned up to desired. This paper describes self-test and self-calibration systems of active RC low pass filters. Main parameters to be estimated and tuned are cut-off frequency, gain and band-pass linearity. Self-calibration system is designed in 0.18 μm technology node, with 1.8 V supply voltage for 10 MHz application. Designed self-calibration system tuning accuracy varies from 0.8 % to 1 %.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125952846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270540
G. Staigvila, V. Novickij
Electroporation by Pulsed ElectroMagnetic Field (PEMF) is a novel, non-invasive technique, which has high potential and applicability in biomedicine and biotechnology. In this work, we present a concept of a high dB/dt and high power system (kA, kV range) for further application in PEMF electroporation experiments. The concept includes an array of synchronized SCRs (silicon controlled rectifiers) driving a high power ignitron. A pulsed power inductor is used as a load. The parameters of the system are selected based on the experimental results with a Marx generator circuit, which was used as a proof of concept. Finite element method (FEM) simulation of the expected spatial distribution of pulsed magnetic field is also presented in the study.
{"title":"Concept of high dB/dt pulse forming system for biological cell membrane permeabilization","authors":"G. Staigvila, V. Novickij","doi":"10.1109/AIEEE.2017.8270540","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270540","url":null,"abstract":"Electroporation by Pulsed ElectroMagnetic Field (PEMF) is a novel, non-invasive technique, which has high potential and applicability in biomedicine and biotechnology. In this work, we present a concept of a high dB/dt and high power system (kA, kV range) for further application in PEMF electroporation experiments. The concept includes an array of synchronized SCRs (silicon controlled rectifiers) driving a high power ignitron. A pulsed power inductor is used as a load. The parameters of the system are selected based on the experimental results with a Marx generator circuit, which was used as a proof of concept. Finite element method (FEM) simulation of the expected spatial distribution of pulsed magnetic field is also presented in the study.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122576470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270537
E. Šabanovič, D. Matuzevičius
Retinal imaging is an important test for diagnosis of eye diseases and treatment evaluation. One of the steps in eye fundus image processing is image registration. It is inevitable in order to eliminate geometrical differences, introduced during imaging with different settings or pursuing follow up disease screenings. One of available strategies for image alignment is feature-based approach where feature descriptors have an important role in registration process. The quality of feature descriptors affects feature matching performance and overall results of image registration. In this paper we present a comparison of various feature extractors in tandem with conventional, bio-inspired or deep neural network-based local feature detectors applied for retinal image registration. Comparative evaluation of descriptors has been carried out using Fundus Image Registration Dataset, measuring Euclidean distance between ground truth points after image alignment. We present the results showing the performance of various feature detector-descriptor pairs applied for retinal image registration.
{"title":"Experimental investigation of feature descriptors for retinal image registration","authors":"E. Šabanovič, D. Matuzevičius","doi":"10.1109/AIEEE.2017.8270537","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270537","url":null,"abstract":"Retinal imaging is an important test for diagnosis of eye diseases and treatment evaluation. One of the steps in eye fundus image processing is image registration. It is inevitable in order to eliminate geometrical differences, introduced during imaging with different settings or pursuing follow up disease screenings. One of available strategies for image alignment is feature-based approach where feature descriptors have an important role in registration process. The quality of feature descriptors affects feature matching performance and overall results of image registration. In this paper we present a comparison of various feature extractors in tandem with conventional, bio-inspired or deep neural network-based local feature detectors applied for retinal image registration. Comparative evaluation of descriptors has been carried out using Fundus Image Registration Dataset, measuring Euclidean distance between ground truth points after image alignment. We present the results showing the performance of various feature detector-descriptor pairs applied for retinal image registration.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126325691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270538
L. Kohútka, V. Stopjaková
This paper presents the design of a coprocessor that performs an efficient task scheduling for quad-core real-time systems. The proposed solution is based on two algorithms: Earliest Deadline First (EDF) algorithm that is proved to always find an optimum ordering of hard real-time tasks and the priority-based FCFS algorithm, which is suitable for non-real-time tasks. The proposed coprocessor can efficiently handle any combination of both types of tasks even though they use different parameters for scheduling. Thanks to HW implementation of the scheduler, the operations are performed in two clock cycles regardless of the current and the maximum number of tasks in the system. The proposed coprocessor is optimized for quad-core CPUs, which can lead to much higher performance of real-time embedded systems than the other schedulers. An existing approach originally designed for dual-core systems was used, known as semaphore approach. The new scheduler was verified using UVM and 256 million instructions with randomly generated deadline/priority values. The synthesis results of the new coprocessor designed for quad-core CPUs were compared to the synthesis results of previous versions of the scheduler. The quad-core version of the scheduler consumes only from 1% to 27% more LUTs than the single-core version.
{"title":"Extension of hardware-accelerated real-time task schedulers for support of quad-core processors","authors":"L. Kohútka, V. Stopjaková","doi":"10.1109/AIEEE.2017.8270538","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270538","url":null,"abstract":"This paper presents the design of a coprocessor that performs an efficient task scheduling for quad-core real-time systems. The proposed solution is based on two algorithms: Earliest Deadline First (EDF) algorithm that is proved to always find an optimum ordering of hard real-time tasks and the priority-based FCFS algorithm, which is suitable for non-real-time tasks. The proposed coprocessor can efficiently handle any combination of both types of tasks even though they use different parameters for scheduling. Thanks to HW implementation of the scheduler, the operations are performed in two clock cycles regardless of the current and the maximum number of tasks in the system. The proposed coprocessor is optimized for quad-core CPUs, which can lead to much higher performance of real-time embedded systems than the other schedulers. An existing approach originally designed for dual-core systems was used, known as semaphore approach. The new scheduler was verified using UVM and 256 million instructions with randomly generated deadline/priority values. The synthesis results of the new coprocessor designed for quad-core CPUs were compared to the synthesis results of previous versions of the scheduler. The quad-core version of the scheduler consumes only from 1% to 27% more LUTs than the single-core version.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126160178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270544
Marijan Jurgo, R. Navickas
In this paper parameters of time to digital converter (TDC), which is often used as phase detector in all-digital frequency synthesizers, designed in 65 nm and 0.13 μm CMOS integrated circuit technologies, were analyzed. The structure of the designed TDC is a variety of 2D Vernier time to digital converter, based on gated ring oscillators. Performance of these oscillators has biggest impact on resolution of TDC. Therefore, oscillators were simulated using analog approach using Cadence integrated circuit design software. Simulations were carried out in nominal (1.2 V, 40 °C, typical transistor models), worst (1.1 V, 40 °C, slow transistor models) and best (1.3 V, −40 °C, fast transistor models) operation conditions. In the nominal operation conditions, the frequency of gated ring oscillator can be tuned from 0.68 GHz to 3.38 GHz and from 0.33 GHz to 0.71 GHz respectively in 65 nm and 0.13 μm technology. The delay of single stage can be changed from 491 ps to 98 ps and from 1.013 ns to 0.466 ns respectively in 65 nm and 0.13 μm CMOS. At least 3 and 5 sections of oscillator need to be enabled respectively in 65 nm and 0.13 μm CMOS for oscillator to start. Tuning step of oscillator's stage delay, which corresponds to resolution of TDC, in nominal operating conditions can be changed from 3.4 ps to 0.8 ps and from 5.8 ps to 1.1 ps respectively in 65 nm and 0.13 μm CMOS, when number of enabled oscillator's sections is changed from 20 to 48. Total area of silicon occupied by TDC is 123 μm × 148.8 μm in 65 nm CMOS technology and 244.2 μm × 295.8 μm in 0.13 μm CMOS technology.
{"title":"Comparison of TDC parameters in 65 nm and 0.13 μm CMOS","authors":"Marijan Jurgo, R. Navickas","doi":"10.1109/AIEEE.2017.8270544","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270544","url":null,"abstract":"In this paper parameters of time to digital converter (TDC), which is often used as phase detector in all-digital frequency synthesizers, designed in 65 nm and 0.13 μm CMOS integrated circuit technologies, were analyzed. The structure of the designed TDC is a variety of 2D Vernier time to digital converter, based on gated ring oscillators. Performance of these oscillators has biggest impact on resolution of TDC. Therefore, oscillators were simulated using analog approach using Cadence integrated circuit design software. Simulations were carried out in nominal (1.2 V, 40 °C, typical transistor models), worst (1.1 V, 40 °C, slow transistor models) and best (1.3 V, −40 °C, fast transistor models) operation conditions. In the nominal operation conditions, the frequency of gated ring oscillator can be tuned from 0.68 GHz to 3.38 GHz and from 0.33 GHz to 0.71 GHz respectively in 65 nm and 0.13 μm technology. The delay of single stage can be changed from 491 ps to 98 ps and from 1.013 ns to 0.466 ns respectively in 65 nm and 0.13 μm CMOS. At least 3 and 5 sections of oscillator need to be enabled respectively in 65 nm and 0.13 μm CMOS for oscillator to start. Tuning step of oscillator's stage delay, which corresponds to resolution of TDC, in nominal operating conditions can be changed from 3.4 ps to 0.8 ps and from 5.8 ps to 1.1 ps respectively in 65 nm and 0.13 μm CMOS, when number of enabled oscillator's sections is changed from 20 to 48. Total area of silicon occupied by TDC is 123 μm × 148.8 μm in 65 nm CMOS technology and 244.2 μm × 295.8 μm in 0.13 μm CMOS technology.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129214438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270559
M. Vorobyov, I. Galkin
Motivated by the emerging needs to improve the quality of life for the elderly and disabled individuals who rely on wheelchairs for mobility, and who might have limited or no hand functionality at all, a new concept of wheelchair human-in-the-loop interface is proposed in this report. The beginning of the report provides an analysis of information sources on the presented topic. Then, based on this analysis, a concept of human-in-the-loop system is proposed, applying several hands free control interfaces including electroencephalography, myoelectric interface and gyroscope plus accelerometer interface. In the same time, vibration actuators are proposed as a prospective kind of the wheelchair-to-user feedback.
{"title":"Concept of cost-effective power-assisted wheelchair: Human-in-the-loop subsystem","authors":"M. Vorobyov, I. Galkin","doi":"10.1109/AIEEE.2017.8270559","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270559","url":null,"abstract":"Motivated by the emerging needs to improve the quality of life for the elderly and disabled individuals who rely on wheelchairs for mobility, and who might have limited or no hand functionality at all, a new concept of wheelchair human-in-the-loop interface is proposed in this report. The beginning of the report provides an analysis of information sources on the presented topic. Then, based on this analysis, a concept of human-in-the-loop system is proposed, applying several hands free control interfaces including electroencephalography, myoelectric interface and gyroscope plus accelerometer interface. In the same time, vibration actuators are proposed as a prospective kind of the wheelchair-to-user feedback.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128981022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270555
Julius Skirelis, D. Navakauskas
Edge computing, the subsidiary model of Cloud computing, is aiming to push computational resources closer to the edge of network. Its objectives are to improve network latency and ensure efficiency of performed tasks. However Internet of Things (IoT) devices usually are of limited processing power or/and connecting to network episodically, mostly due to power saving necessity and mobility. Thus in the paper investigation of the performance of edge computing for IoT is presented. Multiple simulations by EdgeNetworkCloudSim of different topologies, their parameters, together with considered IoT device primary limitations, are carried out. Simulation results confirm the specificity of edge computations for IoT and gives some practical insights.
{"title":"Edge computing in IoT: Preliminary results on modeling and performance analysis","authors":"Julius Skirelis, D. Navakauskas","doi":"10.1109/AIEEE.2017.8270555","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270555","url":null,"abstract":"Edge computing, the subsidiary model of Cloud computing, is aiming to push computational resources closer to the edge of network. Its objectives are to improve network latency and ensure efficiency of performed tasks. However Internet of Things (IoT) devices usually are of limited processing power or/and connecting to network episodically, mostly due to power saving necessity and mobility. Thus in the paper investigation of the performance of edge computing for IoT is presented. Multiple simulations by EdgeNetworkCloudSim of different topologies, their parameters, together with considered IoT device primary limitations, are carried out. Simulation results confirm the specificity of edge computations for IoT and gives some practical insights.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115171108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270528
A. Poreva, Y. Karplyuk, V. Vaityshyn
The article considers the basic methods of machine learning for applying them to the task of the lungs sounds classifying. A number of signal parameters were obtained on the basis of the lungs sounds set. The task of the study was to classify sounds using five different machine learning methods. It was also necessary to determine from a number of signal parameters those that give the highest accuracy. Thus the seven most diagnostically valuable parameters of lung sounds were found. The results showed that two methods of machine learning — the method of reference vectors and the decision tree method — have the best accuracy. Thus this classification technique can serve as an auxiliary tool for a pulmonary physician to diagnosis.
{"title":"Machine learning techniques application for lung diseases diagnosis","authors":"A. Poreva, Y. Karplyuk, V. Vaityshyn","doi":"10.1109/AIEEE.2017.8270528","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270528","url":null,"abstract":"The article considers the basic methods of machine learning for applying them to the task of the lungs sounds classifying. A number of signal parameters were obtained on the basis of the lungs sounds set. The task of the study was to classify sounds using five different machine learning methods. It was also necessary to determine from a number of signal parameters those that give the highest accuracy. Thus the seven most diagnostically valuable parameters of lung sounds were found. The results showed that two methods of machine learning — the method of reference vectors and the decision tree method — have the best accuracy. Thus this classification technique can serve as an auxiliary tool for a pulmonary physician to diagnosis.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125596786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-11-01DOI: 10.1109/AIEEE.2017.8270530
P. Ruberg, Keijo Lass, Elvar Liiv, P. Ellervee
Tools for performance estimation based on instruction set simulators (ISS) are mostly available and show good results. However when the need arises to choose a different platform or to estimate performance without having the ISS the developer needs all the different software suits and devices and also must be able to work with them. In this case we propose an estimation method based on physical measurement for generating performance models. This paper extends our previous work on source-code level performance estimations for microcontrollers. We compare two proposed estimation methods to find the most suitable for estimating embedded software performance for C source-code level on microcontrollers with higher compiler optimisation levels than −O0. As a result we show that both methods could be applied with some exceptions.
{"title":"Embedded software performance estimations at different compiler optimisation levels","authors":"P. Ruberg, Keijo Lass, Elvar Liiv, P. Ellervee","doi":"10.1109/AIEEE.2017.8270530","DOIUrl":"https://doi.org/10.1109/AIEEE.2017.8270530","url":null,"abstract":"Tools for performance estimation based on instruction set simulators (ISS) are mostly available and show good results. However when the need arises to choose a different platform or to estimate performance without having the ISS the developer needs all the different software suits and devices and also must be able to work with them. In this case we propose an estimation method based on physical measurement for generating performance models. This paper extends our previous work on source-code level performance estimations for microcontrollers. We compare two proposed estimation methods to find the most suitable for estimating embedded software performance for C source-code level on microcontrollers with higher compiler optimisation levels than −O0. As a result we show that both methods could be applied with some exceptions.","PeriodicalId":224275,"journal":{"name":"2017 5th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)","volume":"161 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120933665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：