Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741116
Junseok Lee, Kisong Yoon
This paper discusses the design of a system to support security communications between a Web browser and a CGI program using PKI (public key infrastructure). TLS (transport layer security) supports security communications between a Web browser and a Web server, but this system supports security communications between a Web server and a CGI program as well as between a Web browser and a Web server. This system uses GSS (generic security service) API to communicate with PKI, and offers a Web user a Web proxy, and offers three library functions for CGI applications related to security. This makes it easier for a CGI developer to write a CGI program.
{"title":"Design of a system to support security communication between a Web proxy and a CGI program based on PKI","authors":"Junseok Lee, Kisong Yoon","doi":"10.1109/ICPADS.1998.741116","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741116","url":null,"abstract":"This paper discusses the design of a system to support security communications between a Web browser and a CGI program using PKI (public key infrastructure). TLS (transport layer security) supports security communications between a Web browser and a Web server, but this system supports security communications between a Web server and a CGI program as well as between a Web browser and a Web server. This system uses GSS (generic security service) API to communicate with PKI, and offers a Web user a Web proxy, and offers three library functions for CGI applications related to security. This makes it easier for a CGI developer to write a CGI program.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128579672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741145
T. MacKenzie, T. Dix
The paper presents our language C++-with-Ease, a superset of C++ with primitives for process creation and communication. The work adopts the semantics of the Ease parallel primitives, as defined by S.E. Zenith (1990), within the object oriented paradigm. The result is a general purpose, high level, imperative parallel programming language that allows the simple expression of parallel algorithms within a type-safe implementation. Our language implementation is best suited to homogeneous parallel MIMD machines, independent of architecture, but also runs under threads packages. C++-with-Ease addresses efficiency for message copying and provides extensions to allow the passing of arbitrary messages in a natural fashion within the paradigm. The implementation and associated message protocols are discussed.
{"title":"Object-oriented Ease-based parallel primitives in C++","authors":"T. MacKenzie, T. Dix","doi":"10.1109/ICPADS.1998.741145","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741145","url":null,"abstract":"The paper presents our language C++-with-Ease, a superset of C++ with primitives for process creation and communication. The work adopts the semantics of the Ease parallel primitives, as defined by S.E. Zenith (1990), within the object oriented paradigm. The result is a general purpose, high level, imperative parallel programming language that allows the simple expression of parallel algorithms within a type-safe implementation. Our language implementation is best suited to homogeneous parallel MIMD machines, independent of architecture, but also runs under threads packages. C++-with-Ease addresses efficiency for message copying and provides extensions to allow the passing of arbitrary messages in a natural fashion within the paradigm. The implementation and associated message protocols are discussed.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124555904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741167
Yun-Woei Fann, Chao-Tung Yang, Chang-Jiun Tsai, S. Tseng
We propose a knowledge based approach for solving loop scheduling problems. A rule based system, called the IPLS, is developed by repertory grid and attribute ordering table to construct the knowledge base. The IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assigns parallel loops on multiprocessors for achieving high speedup. In addition, the refined system of IPLS can automatically adjust the attributes in a knowledge base according to profile information; therefore IPLS has feedback learning ability.
{"title":"IPLS: an intelligent parallel loop scheduling for multiprocessor systems","authors":"Yun-Woei Fann, Chao-Tung Yang, Chang-Jiun Tsai, S. Tseng","doi":"10.1109/ICPADS.1998.741167","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741167","url":null,"abstract":"We propose a knowledge based approach for solving loop scheduling problems. A rule based system, called the IPLS, is developed by repertory grid and attribute ordering table to construct the knowledge base. The IPLS chooses an appropriate scheduling algorithm by inferring some features of loops and assigns parallel loops on multiprocessors for achieving high speedup. In addition, the refined system of IPLS can automatically adjust the attributes in a knowledge base according to profile information; therefore IPLS has feedback learning ability.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125697091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741126
Der-Lin Pean, Jia-Rong Wu, Cheng Chen
Migratory-sharing data references will incur many cache misses that can be reduced by merging the invalidation/update requests and the cache misses. This paper presents effective software and hardware techniques to reduce the overhead of migratory-sharing references for the linked-based cache coherence protocols. The software scheme combines both compiler labeling and run time detection techniques. The hardware scheme uses the special access patterns in the linked-based protocoIs to detect migratory data objects. We have evaluated the performance on the linked-based program-driven simulation environment by using a set of SPLASH benchmarks. According to the simulation results, our software and hardware methods effectively enhanced the system performance up to 29% and 23% respectively by reducing the overhead of the migratory-sharing references.
{"title":"Effective mechanisms to reduce the overhead of migratory sharing for linked-based cache coherence protocols in clustering multiprocessor architecture","authors":"Der-Lin Pean, Jia-Rong Wu, Cheng Chen","doi":"10.1109/ICPADS.1998.741126","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741126","url":null,"abstract":"Migratory-sharing data references will incur many cache misses that can be reduced by merging the invalidation/update requests and the cache misses. This paper presents effective software and hardware techniques to reduce the overhead of migratory-sharing references for the linked-based cache coherence protocols. The software scheme combines both compiler labeling and run time detection techniques. The hardware scheme uses the special access patterns in the linked-based protocoIs to detect migratory data objects. We have evaluated the performance on the linked-based program-driven simulation environment by using a set of SPLASH benchmarks. According to the simulation results, our software and hardware methods effectively enhanced the system performance up to 29% and 23% respectively by reducing the overhead of the migratory-sharing references.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132109069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741141
V. Gruhn, P. Herrmann, H. Krumm
A user-defined telecooperation service (UTS) provides service elements for application-specific communication and cooperation processes as well as integrated means for the service definition, adaptation, and management. It supports user groups with particular communication, cooperation, and coordination needs which may change over time and which may be that special, that the service maintenance can be carried out only by the users themselves in an economic and satisfactory way. The users may be organized in various open and closed groups. They dispose of personal computing equipment connected via wide-area telecommunication networks. The users participate only from time to time. Therefore, there is a partial and varying accessibility of users and user sites. Interactions are mainly based on asynchronous communication operations. The cooperation and coordination functions have to consider unreachable users. The paper introduces the notion of UTS. Fields of application are addressed. Moreover, we describe the principles of the service element definitions and outline the architecture of a supporting system.
{"title":"User-defined telecooperation services","authors":"V. Gruhn, P. Herrmann, H. Krumm","doi":"10.1109/ICPADS.1998.741141","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741141","url":null,"abstract":"A user-defined telecooperation service (UTS) provides service elements for application-specific communication and cooperation processes as well as integrated means for the service definition, adaptation, and management. It supports user groups with particular communication, cooperation, and coordination needs which may change over time and which may be that special, that the service maintenance can be carried out only by the users themselves in an economic and satisfactory way. The users may be organized in various open and closed groups. They dispose of personal computing equipment connected via wide-area telecommunication networks. The users participate only from time to time. Therefore, there is a partial and varying accessibility of users and user sites. Interactions are mainly based on asynchronous communication operations. The cooperation and coordination functions have to consider unreachable users. The paper introduces the notion of UTS. Fields of application are addressed. Moreover, we describe the principles of the service element definitions and outline the architecture of a supporting system.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130171683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741166
Hiecheol Kim, J. Gaudiot
The paper presents a systematic approach to the compilation of logic programs for efficient clause indexing. As the kernel of the approach, we propose the indexing tree which provides a simple, but precise representation of average parallelism per node (i.e., choice point) as well as the amount of clause trials. It also provides the way to evaluate the number of the cases that the control is passed to the failure code by the indexing instruction such as switch on term, switch on constant, or switch on structure. By analyzing the indexing tree created when using the indexing scheme implemented in the WAM, we show the drawback of the WAM indexing scheme in terms of parallelism exposition and scheduling. Subsequently we propose a new indexing scheme, which we call Flat indexing. Experimental results show that over one half of the benchmarks benefit from the Flat indexing, such that compared with the WAM indexing scheme, the number of choice points is reduced by 15%. Moreover, the amount of failures which occur during the execution of indexing instructions is reduced by 35%.
{"title":"Flat indexing: a compilation technique to enhance parallelism of logic programs","authors":"Hiecheol Kim, J. Gaudiot","doi":"10.1109/ICPADS.1998.741166","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741166","url":null,"abstract":"The paper presents a systematic approach to the compilation of logic programs for efficient clause indexing. As the kernel of the approach, we propose the indexing tree which provides a simple, but precise representation of average parallelism per node (i.e., choice point) as well as the amount of clause trials. It also provides the way to evaluate the number of the cases that the control is passed to the failure code by the indexing instruction such as switch on term, switch on constant, or switch on structure. By analyzing the indexing tree created when using the indexing scheme implemented in the WAM, we show the drawback of the WAM indexing scheme in terms of parallelism exposition and scheduling. Subsequently we propose a new indexing scheme, which we call Flat indexing. Experimental results show that over one half of the benchmarks benefit from the Flat indexing, such that compared with the WAM indexing scheme, the number of choice points is reduced by 15%. Moreover, the amount of failures which occur during the execution of indexing instructions is reduced by 35%.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133831183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741148
Vincent Boudet, F. Rastello, Y. Robert
An efficient algorithm to simultaneously implement array alignment and data/computation distribution is introduced and evaluated. We re-visit previous work of Li and Chen (J. Li and M. Chen, 1990; 1991), and we show that their alignment step should not be conducted without preserving the potential parallelism. In other words, the optimal alignment may well sequentialize computations, whatever the distribution afterwards. We provide an efficient algorithm that handles alignment and data/computation distribution simultaneously. The good news is that several important instances of the whole alignment/distribution problem have polynomial complexity, while alignment itself is NP-complete (J. Li and M. Chen, 1990).
介绍并评价了一种同时实现阵列对齐和数据/计算分配的有效算法。我们重新审视Li和Chen之前的工作(J. Li and M. Chen, 1990;1991)，我们表明，如果不保留潜在的并行性，他们的对齐步骤不应该进行。换句话说，无论之后的分布如何，最佳对齐都可以很好地将计算顺序化。我们提供了一种高效的算法，可以同时处理对齐和数据/计算分布。好消息是，整个对齐/分布问题的几个重要实例具有多项式复杂度，而对齐本身是np完全的(J. Li和M. Chen, 1990)。
{"title":"Alignment and distribution is NOT (always) NP-hard","authors":"Vincent Boudet, F. Rastello, Y. Robert","doi":"10.1109/ICPADS.1998.741148","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741148","url":null,"abstract":"An efficient algorithm to simultaneously implement array alignment and data/computation distribution is introduced and evaluated. We re-visit previous work of Li and Chen (J. Li and M. Chen, 1990; 1991), and we show that their alignment step should not be conducted without preserving the potential parallelism. In other words, the optimal alignment may well sequentialize computations, whatever the distribution afterwards. We provide an efficient algorithm that handles alignment and data/computation distribution simultaneously. The good news is that several important instances of the whole alignment/distribution problem have polynomial complexity, while alignment itself is NP-complete (J. Li and M. Chen, 1990).","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134275073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741161
N. Kataoka, K. Kuroda, Tsutomu Ohkawa, H. Koizumi, N. Shiratori
As corporations continue to introduce workflow systems, different systems have appeared for processing of core-business tasks for information processing and clerical work. A number of different models for coordination of different workflow systems have been proposed; but workflows for core-business tasks constitute the central business processes of the company, and certain aspects of coordination of such workflows differ from other kinds of coordination. This paper clarifies these differences, and proposes a model for coordination, which takes these differences into consideration. In addition the application of this model to an actual system and confirmation of its effectiveness are also reported.
{"title":"Proposal and verification of a workflow coordination model for core business","authors":"N. Kataoka, K. Kuroda, Tsutomu Ohkawa, H. Koizumi, N. Shiratori","doi":"10.1109/ICPADS.1998.741161","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741161","url":null,"abstract":"As corporations continue to introduce workflow systems, different systems have appeared for processing of core-business tasks for information processing and clerical work. A number of different models for coordination of different workflow systems have been proposed; but workflows for core-business tasks constitute the central business processes of the company, and certain aspects of coordination of such workflows differ from other kinds of coordination. This paper clarifies these differences, and proposes a model for coordination, which takes these differences into consideration. In addition the application of this model to an actual system and confirmation of its effectiveness are also reported.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134323554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741017
W.-K. Hong, Nam-Hee Kim, Shin-Dug Kim
In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically, depending on the transfer mode, so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event-driven simulation, and its results show a 58% decrease in the data traffic and a 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about a 56% improvement in the execution time.
{"title":"Design and performance evaluation of an adaptive cache coherence protocol","authors":"W.-K. Hong, Nam-Hee Kim, Shin-Dug Kim","doi":"10.1109/ICPADS.1998.741017","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741017","url":null,"abstract":"In shared-memory multiprocessor systems, the local caches which are used to tolerate the performance gap between processor and memory cause additional bus transactions to maintain the coherency of shared data. Especially, coherency misses and data traffic due to spatial locality and false sharing have a significant effect on the system performance. In this approach, an adaptive cache coherence protocol based on the sectored cache is introduced. It determines the size of a block to be migrated or invalidated dynamically, depending on the transfer mode, so that it can exploit the spatial locality and reduce useless data traffic due to false sharing at the same time. This protocol is evaluated via event-driven simulation, and its results show a 58% decrease in the data traffic and a 45% decrease in the cache miss ratio. Thus, the adaptive cache coherence protocol provides about a 56% improvement in the execution time.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134619812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741123
Hui-Yue Hwang, R.-Ming Shiu, J. Shann
Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive scheduling policy of load/store operations becomes crucial. We examine the scheduling policies of loads/stores on x86 superscalar microprocessors and propose a new aggressive scheduling policy called load speculation, which allows loads to precede the previous unsolved pending stores. Simulation results show that the load speculation achieves the higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the load speculation can achieve even higher performance.
{"title":"An x86 load/store unit with aggressive scheduling of load/store operations","authors":"Hui-Yue Hwang, R.-Ming Shiu, J. Shann","doi":"10.1109/ICPADS.1998.741123","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741123","url":null,"abstract":"Because of register-memory instruction set architecture and limited register set, there are significant amounts of memory access instructions in x86 microprocessors. As the higher issue degree of superscalar microprocessor is provided, an aggressive scheduling policy of load/store operations becomes crucial. We examine the scheduling policies of loads/stores on x86 superscalar microprocessors and propose a new aggressive scheduling policy called load speculation, which allows loads to precede the previous unsolved pending stores. Simulation results show that the load speculation achieves the higher performance in comparison with the traditional scheduling policies such as load bypassing and load forwarding. Furthermore, by reducing the pipeline stages, the load speculation can achieve even higher performance.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124301250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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