Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741047
G. Nam, Jong-Hee Park, Tai-Yun Kim
As the World Wide Web is popular, it is in high demand for retrieving the right information. In addition, the amount of information that is available has been increased. A search engine is used to locate information, due to the fact that searching for information from an increased amount of information is difficult. The search engine has started to use robot agents to facilitate easier access to the information. The paper proposes a dynamic URL management technique by using the object oriented paradigm for efficient performance of the robot agent. While URLs are saved in a file or database to decide whether the site is visited or not, this technique creates a URL object and pushes in a hash table. Therefore we can easily compare a new URL to others in a hash table which allows us to save, and insert a new URL if the URL is not in a hash table. This technique has the advantage of saving URL in a unique way. Other useful information about URL also can be stored. If the robot agent is suspended, we can save into files by using object serialization to save the main memory.
{"title":"Dynamic management of URL based on object-oriented paradigm","authors":"G. Nam, Jong-Hee Park, Tai-Yun Kim","doi":"10.1109/ICPADS.1998.741047","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741047","url":null,"abstract":"As the World Wide Web is popular, it is in high demand for retrieving the right information. In addition, the amount of information that is available has been increased. A search engine is used to locate information, due to the fact that searching for information from an increased amount of information is difficult. The search engine has started to use robot agents to facilitate easier access to the information. The paper proposes a dynamic URL management technique by using the object oriented paradigm for efficient performance of the robot agent. While URLs are saved in a file or database to decide whether the site is visited or not, this technique creates a URL object and pushes in a hash table. Therefore we can easily compare a new URL to others in a hash table which allows us to save, and insert a new URL if the URL is not in a hash table. This technique has the advantage of saving URL in a unique way. Other useful information about URL also can be stored. If the robot agent is suspended, we can save into files by using object serialization to save the main memory.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129276981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741045
K. Law, H. Ip, Fang Wei
A recent research trend in Web applications is the integration of legacy applications on the World Wide Web. The motivations behind this research are the goals of producing a hybrid system where the Web can provide greater accessibility and distribution for legacy applications, and some standards to increase the interoperability and ease of use. For user interaction driven legacy applications, we propose a 3-tier conceptual architecture to support applications for the WWW, and present a approach to building sophisticated inactive Web systems. We benefit from this modelling approach in terms of universal accessibility, platform independency, modularity and migration efficiency. The interaction scenario between the client and server in the prototype implementation is an example to demonstrate the procedures for migrating a legacy application to the Web. Some basic technologies are reviewed and deployed for implementation of our design, including Java applet, servlet, JDBC and CORBA. Such an approach can also be extended to the newly developed Web based applications.
{"title":"Web-enabling legacy applications","authors":"K. Law, H. Ip, Fang Wei","doi":"10.1109/ICPADS.1998.741045","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741045","url":null,"abstract":"A recent research trend in Web applications is the integration of legacy applications on the World Wide Web. The motivations behind this research are the goals of producing a hybrid system where the Web can provide greater accessibility and distribution for legacy applications, and some standards to increase the interoperability and ease of use. For user interaction driven legacy applications, we propose a 3-tier conceptual architecture to support applications for the WWW, and present a approach to building sophisticated inactive Web systems. We benefit from this modelling approach in terms of universal accessibility, platform independency, modularity and migration efficiency. The interaction scenario between the client and server in the prototype implementation is an example to demonstrate the procedures for migrating a legacy application to the Web. Some basic technologies are reviewed and deployed for implementation of our design, including Java applet, servlet, JDBC and CORBA. Such an approach can also be extended to the newly developed Web based applications.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115499574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741102
Chun-Nan Hung, Lih-Hsing Hsu, Ting-Yi Sung
The token ring topology is required in the token passing approach used in distributed operating systems. Fault tolerance is also required in the design of distributed systems. We consider the 1-fault-tolerant design for token rings, which can tolerate 1-processor fault- or 1-link fault. Note that the 1-fault-tolerant design for token rings is equivalent to the design of 1-Hamiltonian graphs. The paper introduces a new family of interconnection networks called Christmas tree. The under graph of the Christmas tree, denoted by CT(s), is a 3-regular, planar, 1-Hamiltonian, and Hamiltonian-connected graph. The number of nodes and the diameter of CT(s) are 3/spl times/2/sup s/-2 and 2s, respectively. In other words, the diameter of CT(s) is 2 log/sub 2/ n-O(1), where n is the number of nodes.
{"title":"Christmas tree: a 1-fault-tolerant network for token rings","authors":"Chun-Nan Hung, Lih-Hsing Hsu, Ting-Yi Sung","doi":"10.1109/ICPADS.1998.741102","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741102","url":null,"abstract":"The token ring topology is required in the token passing approach used in distributed operating systems. Fault tolerance is also required in the design of distributed systems. We consider the 1-fault-tolerant design for token rings, which can tolerate 1-processor fault- or 1-link fault. Note that the 1-fault-tolerant design for token rings is equivalent to the design of 1-Hamiltonian graphs. The paper introduces a new family of interconnection networks called Christmas tree. The under graph of the Christmas tree, denoted by CT(s), is a 3-regular, planar, 1-Hamiltonian, and Hamiltonian-connected graph. The number of nodes and the diameter of CT(s) are 3/spl times/2/sup s/-2 and 2s, respectively. In other words, the diameter of CT(s) is 2 log/sub 2/ n-O(1), where n is the number of nodes.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741163
Win-Tsung Lo, Yue-Shan Chang, S. Yuan, Deron Liang
The distributed object oriented computing model is the next logical step to develop distributed applications. In recent years, several object models have been proposed, such as COM/DCOM, CORBA, and JAVA Bean etc. In CORBA, which was announced by OMG, object request broker is a software bus to connect applications and object components. In addition, multi threaded programming is a well known technique to improve the performance of applications. In a CORBA environment, clients can invoke the remote objects that are shared. If those objects are single threaded it will affect system performance in large distributed applications. We describe in detail the design and implementation of multi threaded object request broker based on CORBA. Our ORB was implemented atop Windows NT and underlying TCP protocol. Finally, we compare our system's performance with IONA's Orbix, which is a well known commercial product, in both one-way and two-way request.
{"title":"Design and implementation of multi-threaded object request broker","authors":"Win-Tsung Lo, Yue-Shan Chang, S. Yuan, Deron Liang","doi":"10.1109/ICPADS.1998.741163","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741163","url":null,"abstract":"The distributed object oriented computing model is the next logical step to develop distributed applications. In recent years, several object models have been proposed, such as COM/DCOM, CORBA, and JAVA Bean etc. In CORBA, which was announced by OMG, object request broker is a software bus to connect applications and object components. In addition, multi threaded programming is a well known technique to improve the performance of applications. In a CORBA environment, clients can invoke the remote objects that are shared. If those objects are single threaded it will affect system performance in large distributed applications. We describe in detail the design and implementation of multi threaded object request broker based on CORBA. Our ORB was implemented atop Windows NT and underlying TCP protocol. Finally, we compare our system's performance with IONA's Orbix, which is a well known commercial product, in both one-way and two-way request.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127281096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741097
Yuh-Shyan Chen, T. Juang, E. Tseng
The arrangement graph A/sub n,k/ is a generalization of star graph (n-k=1) and more flexible than the star graph. In this paper we consider the embedding of multiple spanning trees in an arrangement graph with the objective of being congestion-free. This is first result to exploit multiple spanning trees in the arrangement graphs. We develop a congestion-free embedding of n-k spanning trees with height 2k-1 in an (n, k)-dimensional arrangement graph.
{"title":"Congestion-free embedding of multiple spanning trees in an arrangement graph","authors":"Yuh-Shyan Chen, T. Juang, E. Tseng","doi":"10.1109/ICPADS.1998.741097","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741097","url":null,"abstract":"The arrangement graph A/sub n,k/ is a generalization of star graph (n-k=1) and more flexible than the star graph. In this paper we consider the embedding of multiple spanning trees in an arrangement graph with the objective of being congestion-free. This is first result to exploit multiple spanning trees in the arrangement graphs. We develop a congestion-free embedding of n-k spanning trees with height 2k-1 in an (n, k)-dimensional arrangement graph.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123179613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741015
Chien-Chun Chou, Pozung Chen, Shyh-Nong Chen
In recent years, it has been very popular to employ discrete-event simulation as a hardware architecture analytical tool to study distributed-memory multicomputers and shared-memory multiprocessors. After the hardware architecture prototype has been completed, a complete and detailed machine simulation environment can be utilized to evaluate the architecture's efficiency under real operating systems and application software. In this article, we discuss all the development and implementation of a program-executable Transputer network multicomputer as well as 80x86 series multiprocessors, and how they can be operated. On another level, owing to the extreme complexity of the simulated computer systems, parallel discrete-event simulation has also been used to shorten the time of running the simulation. In practice, this simulator can solve problems through a network connection with many workstations. Some of the workstations may be in charge of computing, while others can be responsible for the management of memory, thus making it simpler to establish a parallel machine simulation environment. In addition to providing an environment for programs to execute on it, such a simulator also calculates the time spent in running these programs, so as to evaluate the feasibility for these application programs to run on a hardware system.
{"title":"A program-driven parallel machine simulation environment","authors":"Chien-Chun Chou, Pozung Chen, Shyh-Nong Chen","doi":"10.1109/ICPADS.1998.741015","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741015","url":null,"abstract":"In recent years, it has been very popular to employ discrete-event simulation as a hardware architecture analytical tool to study distributed-memory multicomputers and shared-memory multiprocessors. After the hardware architecture prototype has been completed, a complete and detailed machine simulation environment can be utilized to evaluate the architecture's efficiency under real operating systems and application software. In this article, we discuss all the development and implementation of a program-executable Transputer network multicomputer as well as 80x86 series multiprocessors, and how they can be operated. On another level, owing to the extreme complexity of the simulated computer systems, parallel discrete-event simulation has also been used to shorten the time of running the simulation. In practice, this simulator can solve problems through a network connection with many workstations. Some of the workstations may be in charge of computing, while others can be responsible for the management of memory, thus making it simpler to establish a parallel machine simulation environment. In addition to providing an environment for programs to execute on it, such a simulator also calculates the time spent in running these programs, so as to evaluate the feasibility for these application programs to run on a hardware system.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129558682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741024
W. Liang, M. Orlowska
Computing multiple related group-by aggregates is one of the core operations of online analytical processing (OLAP) applications. This kind of computation involves a huge volume of data operations (megabytes or treabytes). The response time for such applications is crucial, so, using parallel processing techniques to handle such computation is inevitable. We present several parallel algorithms for computing a collection of group-by aggregates based on a multiprocessor system with shared disks. We focus on a special case of the aggregation problem-"Cube" operator which computes group-by aggregates over all possible combinations of a list of attributes. The proposed algorithms introduce a novel processor scheduling policy and a non-trivial decomposition approach for the problem in the parallel environment. Particularly, the hybrid algorithm has the best performance potential among the four proposed algorithms. All the proposed algorithms are scalable.
{"title":"Computing multidimensional aggregates in parallel","authors":"W. Liang, M. Orlowska","doi":"10.1109/ICPADS.1998.741024","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741024","url":null,"abstract":"Computing multiple related group-by aggregates is one of the core operations of online analytical processing (OLAP) applications. This kind of computation involves a huge volume of data operations (megabytes or treabytes). The response time for such applications is crucial, so, using parallel processing techniques to handle such computation is inevitable. We present several parallel algorithms for computing a collection of group-by aggregates based on a multiprocessor system with shared disks. We focus on a special case of the aggregation problem-\"Cube\" operator which computes group-by aggregates over all possible combinations of a list of attributes. The proposed algorithms introduce a novel processor scheduling policy and a non-trivial decomposition approach for the problem in the parallel environment. Particularly, the hybrid algorithm has the best performance potential among the four proposed algorithms. All the proposed algorithms are scalable.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129875889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741010
F. Mu, C. Svensson
Communications between processing elements (PEs) in high speed parallel systems become a bottleneck as the function and speed of the PEs improve continuously. Clocked I/O ports in PEs may malfunction if data read failure occurs due to clock skew. To reduce the clock skew, global clock distribution is utilized, however it seems to be more difficult to use this for high speed parallel systems in the future. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. This method has these features: high data throughput; low power consumption; no constraints on clock skew and system scale; flexibility in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. Using a jitter injected test signal, robust vector transfer between PEs with arbitrary clock phases is achieved without global synchronization.
{"title":"Self-synchronized vector transfer for high speed parallel systems","authors":"F. Mu, C. Svensson","doi":"10.1109/ICPADS.1998.741010","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741010","url":null,"abstract":"Communications between processing elements (PEs) in high speed parallel systems become a bottleneck as the function and speed of the PEs improve continuously. Clocked I/O ports in PEs may malfunction if data read failure occurs due to clock skew. To reduce the clock skew, global clock distribution is utilized, however it seems to be more difficult to use this for high speed parallel systems in the future. This paper addresses a self-tested self-synchronization (STSS) method for vector transfer between PEs. A test signal is added to remove the data read failure. This method has these features: high data throughput; low power consumption; no constraints on clock skew and system scale; flexibility in design; less latency. A failure zone concept is used to characterize the behavior of storage elements. Using a jitter injected test signal, robust vector transfer between PEs with arbitrary clock phases is achieved without global synchronization.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130894721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741107
Yung-Jin Wu, Jun-Yao Wang, L. Kung, W. Hwang
The traditional slotted ring network is one of the high speed networks, however its transmission delay in heavy network load is too long. We propose a reservation mechanism to improve this drawback. The mechanism is particularly useful in the heavy network load to get a lower delay for high priority packet transmission. We compare it with a traditional slotted ring network by using simulations, and the results show that this mechanism provides the lower delay when the network traffic load is heavy.
{"title":"Design of reservation mechanism based on the slotted ring network","authors":"Yung-Jin Wu, Jun-Yao Wang, L. Kung, W. Hwang","doi":"10.1109/ICPADS.1998.741107","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741107","url":null,"abstract":"The traditional slotted ring network is one of the high speed networks, however its transmission delay in heavy network load is too long. We propose a reservation mechanism to improve this drawback. The mechanism is particularly useful in the heavy network load to get a lower delay for high priority packet transmission. We compare it with a traditional slotted ring network by using simulations, and the results show that this mechanism provides the lower delay when the network traffic load is heavy.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134188324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-12-14DOI: 10.1109/ICPADS.1998.741157
Chun-Mok Chung, Shin-Dug Kim
The Java-Web computing paradigm has changed the Internet into a computing environment. For Java-Web computing and many Java applications, a new Java processor called simultaneous multithreaded (SMT) JavaChip, is proposed to enhance the performance of previous Java processors by hardware support of Java multithreading. SMT JavaChip is a modified architecture with the enhanced mechanism of stack cache, instruction cache, functional units, etc. It executes dual independent threads simultaneously and enhances instruction level parallelism. The performance of SMT JavaChip is evaluated through the simulation using JavaSim, a Java processor simulator. This research is focused to enhance the performance of the Java processor by considering the characteristics of the Java language and computation environment. Performance results show that SMT JavaChip can provide an execution speedup of between 1.28 and 2.00 compared with the single threaded Java processors.
{"title":"A dualthreaded Java processor for Java multithreading","authors":"Chun-Mok Chung, Shin-Dug Kim","doi":"10.1109/ICPADS.1998.741157","DOIUrl":"https://doi.org/10.1109/ICPADS.1998.741157","url":null,"abstract":"The Java-Web computing paradigm has changed the Internet into a computing environment. For Java-Web computing and many Java applications, a new Java processor called simultaneous multithreaded (SMT) JavaChip, is proposed to enhance the performance of previous Java processors by hardware support of Java multithreading. SMT JavaChip is a modified architecture with the enhanced mechanism of stack cache, instruction cache, functional units, etc. It executes dual independent threads simultaneously and enhances instruction level parallelism. The performance of SMT JavaChip is evaluated through the simulation using JavaSim, a Java processor simulator. This research is focused to enhance the performance of the Java processor by considering the characteristics of the Java language and computation environment. Performance results show that SMT JavaChip can provide an execution speedup of between 1.28 and 2.00 compared with the single threaded Java processors.","PeriodicalId":226947,"journal":{"name":"Proceedings 1998 International Conference on Parallel and Distributed Systems (Cat. No.98TB100250)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1998-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130952327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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