Silicon devices are becoming less and less reliable as technology moves to smaller feature sizes. As a result, digital systems are increasingly likely to experience permanent failures during their life-time. To overcome this problem, networks-on-chip (NoCs) should be designed to, not only fulfill performance requirements, but also be robust to many fault occurrences. This paper proposes a fault- and application-aware routing framework called FATE: it leverages the diversity of communication patterns in applications for highly faulty NoCs to reduce congestion during execution. To this end, FATE estimates routing demands in applications to balance traffic load among the available resources. We propose a set of novel route-enabling rules that greatly reduce the search for deadlock-free, maximally-connected routes for any faulty 2D mesh topology, by preventing early on the exploration of routing configuration options that lead eventually to unviable solutions. Our experimental results show a 33% improvement on average saturation throughput for synthetic traffic patterns, and a 59% improvement on average packet latency for SPLASH-2 benchmarks, over state-of-the-art fault-tolerant solutions. The FATE approach is also beneficial in the complete absence of faults: indeed, it outperforms prior fully-adaptive routing techniques by improving the saturation throughput by up to 33%.
{"title":"Highly Fault-tolerant NoC Routing with Application-aware Congestion Management","authors":"Doowon Lee, Ritesh Parikh, V. Bertacco","doi":"10.1145/2786572.2786590","DOIUrl":"https://doi.org/10.1145/2786572.2786590","url":null,"abstract":"Silicon devices are becoming less and less reliable as technology moves to smaller feature sizes. As a result, digital systems are increasingly likely to experience permanent failures during their life-time. To overcome this problem, networks-on-chip (NoCs) should be designed to, not only fulfill performance requirements, but also be robust to many fault occurrences. This paper proposes a fault- and application-aware routing framework called FATE: it leverages the diversity of communication patterns in applications for highly faulty NoCs to reduce congestion during execution. To this end, FATE estimates routing demands in applications to balance traffic load among the available resources. We propose a set of novel route-enabling rules that greatly reduce the search for deadlock-free, maximally-connected routes for any faulty 2D mesh topology, by preventing early on the exploration of routing configuration options that lead eventually to unviable solutions. Our experimental results show a 33% improvement on average saturation throughput for synthetic traffic patterns, and a 59% improvement on average packet latency for SPLASH-2 benchmarks, over state-of-the-art fault-tolerant solutions. The FATE approach is also beneficial in the complete absence of faults: indeed, it outperforms prior fully-adaptive routing techniques by improving the saturation throughput by up to 33%.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115766944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mohammad Fattah, A. Airola, Rachata Ausavarungnirun, N. Mirzaei, P. Liljeberg, J. Plosila, S. Mohammadi, T. Pahikkala, O. Mutlu, H. Tenhunen
This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips. The algorithm is the first to provide all of the following properties at the same time: 1) fully-distributed with no centralized component, 2) guaranteed delivery (it guarantees to deliver packets when a path exists between nodes, or otherwise indicate that destination is unreachable, while being deadlock and livelock free), 3) low area cost, 4) low reconfiguration overhead upon a fault. To achieve all these properties, we propose Maze-routing, a new variant of face routing in on-chip networks and make use of deflections in routing. Our evaluations show that Maze-routing has 16X less area overhead than other algorithms that provide guaranteed delivery. Our Maze-routing algorithm is also high performance: for example, when up to 5 links are broken, it provides 50% higher saturation throughput compared to the state-of-the-art.
{"title":"A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips","authors":"Mohammad Fattah, A. Airola, Rachata Ausavarungnirun, N. Mirzaei, P. Liljeberg, J. Plosila, S. Mohammadi, T. Pahikkala, O. Mutlu, H. Tenhunen","doi":"10.1145/2786572.2786591","DOIUrl":"https://doi.org/10.1145/2786572.2786591","url":null,"abstract":"This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips. The algorithm is the first to provide all of the following properties at the same time: 1) fully-distributed with no centralized component, 2) guaranteed delivery (it guarantees to deliver packets when a path exists between nodes, or otherwise indicate that destination is unreachable, while being deadlock and livelock free), 3) low area cost, 4) low reconfiguration overhead upon a fault. To achieve all these properties, we propose Maze-routing, a new variant of face routing in on-chip networks and make use of deflections in routing. Our evaluations show that Maze-routing has 16X less area overhead than other algorithms that provide guaranteed delivery. Our Maze-routing algorithm is also high performance: for example, when up to 5 links are broken, it provides 50% higher saturation throughput compared to the state-of-the-art.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Emerging heterogeneous interconnects have shown lower latency and higher throughput, which can improve the efficiency of communication and create new opportunities for memory system designs. In this paper, transmission lines are employed as a latency-optimized network and combined with a packet-switched network to create heterogeneous interconnects improving the efficiencies of on-chip communication and cache coherence. We take advantage of this heterogeneous interconnect design, and keep cache coherence adaptively based on data locality. Different type of messages are adaptively directed through selected medium of the heterogeneous interconnects to enhance cache coherence effectiveness. Compared with a state-of-the-art coherence mechanism, the proposed technique can reduce the coherence overhead by 24%, reduce the network energy consumption by 35%, and improve the system performance by 25% on a 64-core system.
{"title":"Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence","authors":"Qi Hu, Peng Liu, Michael C. Huang, Xiang-hui Xie","doi":"10.1145/2786572.2786576","DOIUrl":"https://doi.org/10.1145/2786572.2786576","url":null,"abstract":"Emerging heterogeneous interconnects have shown lower latency and higher throughput, which can improve the efficiency of communication and create new opportunities for memory system designs. In this paper, transmission lines are employed as a latency-optimized network and combined with a packet-switched network to create heterogeneous interconnects improving the efficiencies of on-chip communication and cache coherence. We take advantage of this heterogeneous interconnect design, and keep cache coherence adaptively based on data locality. Different type of messages are adaptively directed through selected medium of the heterogeneous interconnects to enhance cache coherence effectiveness. Compared with a state-of-the-art coherence mechanism, the proposed technique can reduce the coherence overhead by 24%, reduce the network energy consumption by 35%, and improve the system performance by 25% on a 64-core system.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131765004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Zong, Michael Opoku Agyeman, Xiaohang Wang, T. Mak
Adaptive routing in Network-on-Chip (NoC) selects paths for packets according to network state to reduce packet latency and balance network load. Existing adaptive routing schemes can degrade network performance due to their dependency on either inadequate or outdated network information. We present an adaptive routing scheme in which a router is provided adequate and timely congestion information of the network. A low-complexity routing selection function that considers regional congestion status is proposed. The selection function is unbiased as it considers the same amount of congestion information on both admissible directions. Proposed selection function achieves 18% lower packet latency than local congestion aware selection under realistic workloads. It also reduces regional congestion aware selection logic area and power overhead by 73% and 35% on an 8×8 mesh network.
{"title":"Unbiased Regional Congestion Aware Selection Function for NoCs","authors":"W. Zong, Michael Opoku Agyeman, Xiaohang Wang, T. Mak","doi":"10.1145/2786572.2786574","DOIUrl":"https://doi.org/10.1145/2786572.2786574","url":null,"abstract":"Adaptive routing in Network-on-Chip (NoC) selects paths for packets according to network state to reduce packet latency and balance network load. Existing adaptive routing schemes can degrade network performance due to their dependency on either inadequate or outdated network information. We present an adaptive routing scheme in which a router is provided adequate and timely congestion information of the network. A low-complexity routing selection function that considers regional congestion status is proposed. The selection function is unbiased as it considers the same amount of congestion information on both admissible directions. Proposed selection function achieves 18% lower packet latency than local congestion aware selection under realistic workloads. It also reduces regional congestion aware selection logic area and power overhead by 73% and 35% on an 8×8 mesh network.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133925730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With increase in complexity of multicore chips, efficiency of data transfer between cores of a chip is becoming increasingly challenging. Several novel on-chip network architectures are proposed to improve the design flexibility and communication efficiency in multicore chips. On the other hand, computing modules in typical data center nodes or server racks consist of several multicore chips on either a board or in a System-in-Package (SiP) environment. State-of-the-art interchip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the interchip channels to the destination chip. After reaching the destination chip they will be finally routed from the I/O to the internal nets there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Moreover, intrachip and interchip communication within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. In this work we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. This enables direct chip-to-chip communication between internal cores. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.
{"title":"An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links","authors":"Md Shahriar Shamim, J. Muralidharan, A. Ganguly","doi":"10.1145/2786572.2786581","DOIUrl":"https://doi.org/10.1145/2786572.2786581","url":null,"abstract":"With increase in complexity of multicore chips, efficiency of data transfer between cores of a chip is becoming increasingly challenging. Several novel on-chip network architectures are proposed to improve the design flexibility and communication efficiency in multicore chips. On the other hand, computing modules in typical data center nodes or server racks consist of several multicore chips on either a board or in a System-in-Package (SiP) environment. State-of-the-art interchip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the interchip channels to the destination chip. After reaching the destination chip they will be finally routed from the I/O to the internal nets there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Moreover, intrachip and interchip communication within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. In this work we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. This enables direct chip-to-chip communication between internal cores. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125307377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Michael Opoku Agyeman, W. Zong, Ji-Xiang Wan, A. Yakovlev, K. Tong, T. Mak
Existing wireless communication interface of Hybrid Wired-Wireless Network-on-Chip (WiNoC) has 3-dimensional free space signal radiation which has high power dissipation and drastically affects the received signal strength. In this paper, we propose a CMOS based 2-dimensional (2-D) waveguide communication fabric that is able to match the channel reliability of traditional wired NoCs as the wireless communication fabric. Our experimental results demonstrate that, the proposed communication fabric can achieve a 5dB operational bandwidth of about 60GHz around the center frequency (60GHz). Compared to existing WiNoCs, the proposed communication fabric can improve the reliability of WiNoCs with average gains of 21.4%, 13.8% and 10.6% performance efficiencies in terms of maximum sustainable load, throughput and delay, respectively.
{"title":"Novel Hybrid Wired-Wireless Network-on-Chip Architectures: Transducer and Communication Fabric Design","authors":"Michael Opoku Agyeman, W. Zong, Ji-Xiang Wan, A. Yakovlev, K. Tong, T. Mak","doi":"10.1145/2786572.2786586","DOIUrl":"https://doi.org/10.1145/2786572.2786586","url":null,"abstract":"Existing wireless communication interface of Hybrid Wired-Wireless Network-on-Chip (WiNoC) has 3-dimensional free space signal radiation which has high power dissipation and drastically affects the received signal strength. In this paper, we propose a CMOS based 2-dimensional (2-D) waveguide communication fabric that is able to match the channel reliability of traditional wired NoCs as the wireless communication fabric. Our experimental results demonstrate that, the proposed communication fabric can achieve a 5dB operational bandwidth of about 60GHz around the center frequency (60GHz). Compared to existing WiNoCs, the proposed communication fabric can improve the reliability of WiNoCs with average gains of 21.4%, 13.8% and 10.6% performance efficiencies in terms of maximum sustainable load, throughput and delay, respectively.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
On-chip electrical links exhibit large energy-to-bandwidth costs, whereas on-chip nanophotonics, which attain high throughput, yet energy-efficient communication, have emerged as an alternative interconnect in multicore chips. Here we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to existing die on-surface silicon nanophotonics. As nanophotonic components now reside subsurface, within the silica substrate, non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such Silicon-in-Silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a SiS-based mesh-interconnected topology with augmented diagonal optical channels that provides both higher effective throughput and throughput-to-power ratio versus prior-art.
{"title":"Designing High-Performance, Power-Efficient NoCs With Embedded Silicon-in-Silica Nanophotonics","authors":"E. Kakoulli, V. Soteriou, C. Koutsides, K. Kalli","doi":"10.1145/2786572.2786588","DOIUrl":"https://doi.org/10.1145/2786572.2786588","url":null,"abstract":"On-chip electrical links exhibit large energy-to-bandwidth costs, whereas on-chip nanophotonics, which attain high throughput, yet energy-efficient communication, have emerged as an alternative interconnect in multicore chips. Here we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to existing die on-surface silicon nanophotonics. As nanophotonic components now reside subsurface, within the silica substrate, non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial tools that such Silicon-in-Silica (SiS) structures are feasible, and then demonstrate our proof of concept by utilizing a SiS-based mesh-interconnected topology with augmented diagonal optical channels that provides both higher effective throughput and throughput-to-power ratio versus prior-art.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124027634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless interconnects have emerged as an energy-efficient interconnection paradigm for multicore chips with Networks-on-Chips (NoCs). As wireless interconnects have the unique advantage of eliminating the need to layout physical channels they provide an inherent opportunity for dynamic reconfiguration of the NoC architecture. Large temporal and spatial variability in traffic patterns is expected in large multicore chips and especially in future heterogeneous systems-on-chips integrating different kinds of cores such as CPUs, GPUs, ASICs and memory. By establishing on-demand wireless links in response to dynamically varying traffic patterns the data bandwidth and energy efficiency of NoC architectures can be improved compared to static architectures with the same raw bandwidth. We present a dynamic medium access mechanism that establishes wireless links depending on traffic requirements while reducing the overheads. Such an interconnection system incorporating wireless links in a NoC fabric will be better suited to address non-uniformity and temporal variations in traffic patterns which are expected in future large multicore chips.
{"title":"Reconfigurable Wireless Network-on-Chip with a Dynamic Medium Access Mechanism","authors":"N. Mansoor, A. Ganguly","doi":"10.1145/2786572.2788711","DOIUrl":"https://doi.org/10.1145/2786572.2788711","url":null,"abstract":"Wireless interconnects have emerged as an energy-efficient interconnection paradigm for multicore chips with Networks-on-Chips (NoCs). As wireless interconnects have the unique advantage of eliminating the need to layout physical channels they provide an inherent opportunity for dynamic reconfiguration of the NoC architecture. Large temporal and spatial variability in traffic patterns is expected in large multicore chips and especially in future heterogeneous systems-on-chips integrating different kinds of cores such as CPUs, GPUs, ASICs and memory. By establishing on-demand wireless links in response to dynamically varying traffic patterns the data bandwidth and energy efficiency of NoC architectures can be improved compared to static architectures with the same raw bandwidth. We present a dynamic medium access mechanism that establishes wireless links depending on traffic requirements while reducing the overheads. Such an interconnection system incorporating wireless links in a NoC fabric will be better suited to address non-uniformity and temporal variations in traffic patterns which are expected in future large multicore chips.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128601833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
On-chip wireless links have been shown to overcome the performance limitations of wired interconnects in Networks-on-chip (NoCs). However actual performance gains obtained are largely dependent on efficient data transmission between on-chip antennas. An analysis of on-chip wireless channel shows that propagation is highly affected by different components of the chip. In this work, we include the effects of chip environment on wireless propagation to obtain a more realistic performance evaluation of Wireless NoC (WiNoC). Using these, we derive the latency and energy characteristics of WiNoC and quantify the achievable performance. Results presented show wireless received signal with on-chip effects considered and compare them with that of a wired link.
{"title":"Achievable Performance Enhancements with mm-Wave Wireless Interconnects in NoC","authors":"G. Harsha, Sujay Deb","doi":"10.1145/2786572.2786584","DOIUrl":"https://doi.org/10.1145/2786572.2786584","url":null,"abstract":"On-chip wireless links have been shown to overcome the performance limitations of wired interconnects in Networks-on-chip (NoCs). However actual performance gains obtained are largely dependent on efficient data transmission between on-chip antennas. An analysis of on-chip wireless channel shows that propagation is highly affected by different components of the chip. In this work, we include the effects of chip environment on wireless propagation to obtain a more realistic performance evaluation of Wireless NoC (WiNoC). Using these, we derive the latency and energy characteristics of WiNoC and quantify the achievable performance. Results presented show wireless received signal with on-chip effects considered and compare them with that of a wired link.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125854349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rajesh Js, D. Ancajas, Koushik Chakraborty, Sanghamitra Roy
In this paper, we propose a covert threat model for MPSoCs designed using 3rd party Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on-chip resources, thereby causing large performance bottlenecks for the software running on the MPSoC platform. We then propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. For the proposed technique, our comprehensive cross-layer analysis indicates modest overheads of 12.73% in area, 9.844% in power and 5.4% in terms of network latency.
{"title":"Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip","authors":"Rajesh Js, D. Ancajas, Koushik Chakraborty, Sanghamitra Roy","doi":"10.1145/2786572.2786580","DOIUrl":"https://doi.org/10.1145/2786572.2786580","url":null,"abstract":"In this paper, we propose a covert threat model for MPSoCs designed using 3rd party Network-on-Chips (NoC). We illustrate that a malicious NoC can disrupt the availability of on-chip resources, thereby causing large performance bottlenecks for the software running on the MPSoC platform. We then propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. For the proposed technique, our comprehensive cross-layer analysis indicates modest overheads of 12.73% in area, 9.844% in power and 5.4% in terms of network latency.","PeriodicalId":228605,"journal":{"name":"Proceedings of the 9th International Symposium on Networks-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129629869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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