Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105601
T. Nanya, Masatoshi Uchida
Strongly fault-secure (SFS) circuits are known to achieve the totally self-checking (TSC) goal of producing a noncodeword as the first erroneous output due to a fault. Strongly code-disjoint (SCD) circuits are known to always map noncodeword inputs to noncodeword outputs, even in the presence of faults, as long as the faults remain undetected. The authors present a general design method for SFS and SCD combinational circuits for the previously proposed fault model that covers the broad classes of likely faults in VLSI. In the design, the input and output of a combinational circuit are encoded in systematic unordered codes whose check part is obtained by adding two extra bits to the check part of any known systematic unordered code. Thanks to the uniform input/output encoding and the SCD property for the proposed combinational circuits, a number of the circuits can be interconnected in cascade to construct a larger SFS combinational circuit if each interface is sufficiently exercised.<>
{"title":"A strongly fault-secure and strongly code-disjoint realization of combinational circuits","authors":"T. Nanya, Masatoshi Uchida","doi":"10.1109/FTCS.1989.105601","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105601","url":null,"abstract":"Strongly fault-secure (SFS) circuits are known to achieve the totally self-checking (TSC) goal of producing a noncodeword as the first erroneous output due to a fault. Strongly code-disjoint (SCD) circuits are known to always map noncodeword inputs to noncodeword outputs, even in the presence of faults, as long as the faults remain undetected. The authors present a general design method for SFS and SCD combinational circuits for the previously proposed fault model that covers the broad classes of likely faults in VLSI. In the design, the input and output of a combinational circuit are encoded in systematic unordered codes whose check part is obtained by adding two extra bits to the check part of any known systematic unordered code. Thanks to the uniform input/output encoding and the SCD property for the proposed combinational circuits, a number of the circuits can be interconnected in cascade to construct a larger SFS combinational circuit if each interface is sufficiently exercised.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128835492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105586
Shamsul Chowdhury
Current flow in power distribution systems inside an integrated circuit (IC), especially in VLSI and wafer-scale ICs, causes problems of voltage drop and metal migration, leading to logic malfunction, reduction in operating speed, and reduction in the expected life span of a chip. Accurate estimations of currents are needed to design the power distribution systems so that they will withstand the adverse effects of current surges. During fabrication or as a result of aging, the power distribution systems may break at some weak points. As a result, some parts of the systems may have to route excessive amounts of currents. A power distribution system should be designed so that, in the presence of a limited number of these breaks, the system will deliver currents to the macro cells without violating some prescribed limits on voltage drops and without causing metal migration. The author deals with estimating currents in the segments of power distribution systems under fault conditions and develops guidelines for designing the systems so that the voltage drop and metal migration constraints with respect to these current estimates will not be violated.<>
{"title":"Estimation of maximum currents for fault tolerant design of power distribution systems in integrated circuits","authors":"Shamsul Chowdhury","doi":"10.1109/FTCS.1989.105586","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105586","url":null,"abstract":"Current flow in power distribution systems inside an integrated circuit (IC), especially in VLSI and wafer-scale ICs, causes problems of voltage drop and metal migration, leading to logic malfunction, reduction in operating speed, and reduction in the expected life span of a chip. Accurate estimations of currents are needed to design the power distribution systems so that they will withstand the adverse effects of current surges. During fabrication or as a result of aging, the power distribution systems may break at some weak points. As a result, some parts of the systems may have to route excessive amounts of currents. A power distribution system should be designed so that, in the presence of a limited number of these breaks, the system will deliver currents to the macro cells without violating some prescribed limits on voltage drops and without causing metal migration. The author deals with estimating currents in the segments of power distribution systems under fault conditions and develops guidelines for designing the systems so that the voltage drop and metal migration constraints with respect to these current estimates will not be violated.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125717004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105555
N. Vasanthavada, Philip M. Thambidurai, P. Marinos
The authors address the problem of designing fault-tolerant, phase-locked clocks in the presence of different types of clock failures and show that significant improvements in hardware complexity and reliability can be achieved when failed clock modules are partitioned into two classes: malicious and nonmalicious. They show that the condition N>2t+max(t1, 1) is necessary and sufficient to tolerate up to t failed clock modules out of which a maximum of t1 can behave maliciously. The practical value of this design concept is demonstrated by examples.<>
{"title":"Design of fault-tolerant clocks with realistic failure assumptions","authors":"N. Vasanthavada, Philip M. Thambidurai, P. Marinos","doi":"10.1109/FTCS.1989.105555","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105555","url":null,"abstract":"The authors address the problem of designing fault-tolerant, phase-locked clocks in the presence of different types of clock failures and show that significant improvements in hardware complexity and reliability can be achieved when failed clock modules are partitioned into two classes: malicious and nonmalicious. They show that the condition N>2t+max(t1, 1) is necessary and sufficient to tolerate up to t failed clock modules out of which a maximum of t1 can behave maliciously. The practical value of this design concept is demonstrated by examples.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116046537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105624
R. Melhem
Fault-tolerant architectures and algorithms are studied for processor arrays which are subject to computational loads that alternate between two phases-a strict phase, characterized by a heavy load and strict constraints on response time, and a relaxed phase, characterized by a light load and relatively relaxed constraints on response time. Under this type of load, a bilevel algorithm may be applied to reconfigure the system after faults. Specifically, at one level, called the fast response level, a local distributed fault-tolerant algorithm is used during the strict phase to achieve fast fault recovery at the expense of possible rapid degradation in the potential to tolerate future faults. In order to minimize the effect of this degradation, a second level, called the optimization level, is added. At that level, a global, relatively slow reorganization algorithm is applied during the relaxed phase to restore the system into a shape that ensures adequate fault-tolerance capability in the remaining part of the system's mission. Three examples are given for bilevel reconfiguration algorithms that emphasize three different restoration criteria.<>
{"title":"Bi-level reconfigurations of fault tolerant arrays in bi-modal computational environments","authors":"R. Melhem","doi":"10.1109/FTCS.1989.105624","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105624","url":null,"abstract":"Fault-tolerant architectures and algorithms are studied for processor arrays which are subject to computational loads that alternate between two phases-a strict phase, characterized by a heavy load and strict constraints on response time, and a relaxed phase, characterized by a light load and relatively relaxed constraints on response time. Under this type of load, a bilevel algorithm may be applied to reconfigure the system after faults. Specifically, at one level, called the fast response level, a local distributed fault-tolerant algorithm is used during the strict phase to achieve fast fault recovery at the expense of possible rapid degradation in the potential to tolerate future faults. In order to minimize the effect of this degradation, a second level, called the optimization level, is added. At that level, a global, relatively slow reorganization algorithm is applied during the relaxed phase to restore the system into a shape that ensures adequate fault-tolerance capability in the remaining part of the system's mission. Three examples are given for bilevel reconfiguration algorithms that emphasize three different restoration criteria.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"510 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116206603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105552
H. Wunderlich
A method is described for selecting a minimal set of directly accessible flip-flops. Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. An algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. The entire approach is validated with the help of examples. Only 10-40% of the flip-flops have to be integrated into a partial scan path or into a built-in self-test register to obtain nearly complete fault coverage by weighted random patterns.<>
{"title":"The design of random-testable sequential circuits","authors":"H. Wunderlich","doi":"10.1109/FTCS.1989.105552","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105552","url":null,"abstract":"A method is described for selecting a minimal set of directly accessible flip-flops. Since this problem turns out to be NP-complete, suboptimal solutions can be derived using some heuristics. An algorithm is presented to compute the corresponding weights of the patterns, which are time-dependent in some cases. The entire approach is validated with the help of examples. Only 10-40% of the flip-flops have to be integrated into a partial scan path or into a built-in self-test register to obtain nearly complete fault coverage by weighted random patterns.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115613268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105628
S. Adams
Presents hardware-assisted recovery techniques that detect which memory segments in the failed processor need to be restored, so that recovery can be accomplished incrementally, by only restoring segments of memory that have been corrupted. The techniques, one-shot recovery and running recovery, accomplish recovery without degrading real-time control functions. The efficiency of the recovery algorithms depends on the supposition that only small changes in memory occur from iteration to iteration, and this is demonstrated from experimental data on two test algorithms. The author evaluates the applicability of this technique as applied to an Autoland simulation of a 737 aircraft and a simulated annealing planning algorithm.<>
{"title":"Hardware assisted recovery from transient errors in redundant processing systems","authors":"S. Adams","doi":"10.1109/FTCS.1989.105628","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105628","url":null,"abstract":"Presents hardware-assisted recovery techniques that detect which memory segments in the failed processor need to be restored, so that recovery can be accomplished incrementally, by only restoring segments of memory that have been corrupted. The techniques, one-shot recovery and running recovery, accomplish recovery without degrading real-time control functions. The efficiency of the recovery algorithms depends on the supposition that only small changes in memory occur from iteration to iteration, and this is demonstrated from experimental data on two test algorithms. The author evaluates the applicability of this technique as applied to an Autoland simulation of a 737 aircraft and a simulated annealing planning algorithm.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128701258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105623
P. Mazumder, Jih-Shyr Yih
A demonstration is presented of how to represent the objective function of the memory repair problem as a neural network energy function, and how to utilize the neural net's convergence property to find near-optimal solutions. Two algorithms have been developed using a neural network, and their performance is compared with the 'repair most' algorithm that is used commercially. For randomly generated defect patterns, the proposed algorithm with a hill-climbing capability has been found to be successful in repairing memory arrays in 98% of the cases, as opposed to the repair most algorithm's 20% of cases.<>
{"title":"Neural computing for built-in self-repair of embedded memory arrays","authors":"P. Mazumder, Jih-Shyr Yih","doi":"10.1109/FTCS.1989.105623","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105623","url":null,"abstract":"A demonstration is presented of how to represent the objective function of the memory repair problem as a neural network energy function, and how to utilize the neural net's convergence property to find near-optimal solutions. Two algorithms have been developed using a neural network, and their performance is compared with the 'repair most' algorithm that is used commercially. For randomly generated defect patterns, the proposed algorithm with a hill-climbing capability has been found to be successful in repairing memory arrays in 98% of the cases, as opposed to the repair most algorithm's 20% of cases.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125643368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105596
M. Iacoponi
The problem of controlling latent fault accumulation in digital memory devices in a dynamic space environment is analyzed. Previous analytical modeling work has examined constant error rate environments and constant rate error scrubbing and has generally assumed single error correction. This work is extended to consider environments that cause orders of magnitude variation in the device error rate over the mission life. Such variation can be caused by solar flare activity or time-dependent variations in geomagnetic shielding. Based on the probability models and approximations developed, optimal time-invariant and time-varying error scrubbing policies are analyzed. The models are generalized to allow multiple error correction. Definitions of optimal scrubbing policies are given, and this class of policies is shown to bound the performance of nonoptimal policies.<>
{"title":"Optimal control of latent fault accumulation","authors":"M. Iacoponi","doi":"10.1109/FTCS.1989.105596","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105596","url":null,"abstract":"The problem of controlling latent fault accumulation in digital memory devices in a dynamic space environment is analyzed. Previous analytical modeling work has examined constant error rate environments and constant rate error scrubbing and has generally assumed single error correction. This work is extended to consider environments that cause orders of magnitude variation in the device error rate over the mission life. Such variation can be caused by solar flare activity or time-dependent variations in geomagnetic shielding. Based on the probability models and approximations developed, optimal time-invariant and time-varying error scrubbing policies are analyzed. The models are generalized to allow multiple error correction. Definitions of optimal scrubbing policies are given, and this class of policies is shown to bound the performance of nonoptimal policies.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121831567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105553
Rajesh Gupta, Rajiv Gupta, M. Breuer
In the proposed partial scan methodology, the scan path is constructed so that the rest of the circuit belongs to a class of circuits called balanced sequential structures. Test patterns for this structure are generated by treating it as being combinational. Each test pattern is applied to the circuit by shifting it into the scan path. holding it constant for a fixed number of clock cycles, loading the test result into the scan path, and then shifting it out. This technique achieves full coverage of all detectable faults with a minimal number of scannable storage elements and using only combinational test pattern generation.<>
{"title":"BALLAST: a methodology for partial scan design","authors":"Rajesh Gupta, Rajiv Gupta, M. Breuer","doi":"10.1109/FTCS.1989.105553","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105553","url":null,"abstract":"In the proposed partial scan methodology, the scan path is constructed so that the rest of the circuit belongs to a class of circuits called balanced sequential structures. Test patterns for this structure are generated by treating it as being combinational. Each test pattern is applied to the circuit by shifting it into the scan path. holding it constant for a fixed number of clock cycles, loading the test result into the scan path, and then shifting it out. This technique achieves full coverage of all detectable faults with a minimal number of scannable storage elements and using only combinational test pattern generation.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116912608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105541
M. Schulz, K. Fuchs, F. Fink
Based on the sophisticated techniques applied in the automatic test pattern generation system SOCRATES, the authors present the extension of SOCRATES to test generation for path delay faults. In particular, they propose a ten-valued logic and describe the corresponding implication and path sensitization procedures in detail. After discussing an extended multiple backtrace procedure, which has been developed specifically to meet the requirements of path delay testing, they conclude with a number of experimental results.<>
{"title":"Advanced automatic test pattern generation techniques for path delay faults","authors":"M. Schulz, K. Fuchs, F. Fink","doi":"10.1109/FTCS.1989.105541","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105541","url":null,"abstract":"Based on the sophisticated techniques applied in the automatic test pattern generation system SOCRATES, the authors present the extension of SOCRATES to test generation for path delay faults. In particular, they propose a ten-valued logic and describe the corresponding implication and path sensitization procedures in detail. After discussing an extended multiple backtrace procedure, which has been developed specifically to meet the requirements of path delay testing, they conclude with a number of experimental results.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134380424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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