Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105574
Takahiko Yamada, S. Ogawa
A description is given of the fault-tolerant multiprocessor used in the D70 digital switching system (the main model in Japan). The multiprocessor architecture adopts function sharing as well as load sharing to achieve expansion of processing power efficiently using small but reliable VLSI processors. The fault-tolerance objectives of this multiprocessor are based on the failure magnitude dependence concept, which specifies that the requirement for reliability increases with system size. The multiprocessor combines a redundant configuration and the fail-soft principle to achieve the objectives. The fault recovery procedure comprises four stages of the hierarchical structure. Fault influence propagation is limited using the rationality test for interprocessor communication on the call processing level. Field experience shows that the objectives are satisfied.<>
{"title":"Fault tolerant multiprocessor for digital switching systems","authors":"Takahiko Yamada, S. Ogawa","doi":"10.1109/FTCS.1989.105574","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105574","url":null,"abstract":"A description is given of the fault-tolerant multiprocessor used in the D70 digital switching system (the main model in Japan). The multiprocessor architecture adopts function sharing as well as load sharing to achieve expansion of processing power efficiently using small but reliable VLSI processors. The fault-tolerance objectives of this multiprocessor are based on the failure magnitude dependence concept, which specifies that the requirement for reliability increases with system size. The multiprocessor combines a redundant configuration and the fail-soft principle to achieve the objectives. The fault recovery procedure comprises four stages of the hierarchical structure. Fault influence propagation is limited using the rationality test for interprocessor communication on the call processing level. Field experience shows that the objectives are satisfied.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124250224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105603
N. Jha
The problem of single stuck-at, stuck-open, and stuck-on fault detection in cascode voltage switch (CVS) parity trees is considered. The results are also applied to parity and two-rail checkers. CVS circuits are dynamic CMOS circuits which can implement both inverting and noninverting functions. If the CVS parity tree consists of only differential cascode voltage switch (DCVS) EX-OR gates, then it is shown that at most only five tests are needed for detecting all single stuck-at, stuck-open, and stuck-on faults, independent of the number of primary inputs and the number of inputs to any EX-OR gate in the tree. If, however, only a single-ended output is desired from the tree, than the final gate will be a single-ended cascode voltage switch (SCVS) EX-OR gate. For such a tree it is shown that only eight tests are enough. For a strongly self-checking (SSC) CVS parity checker the number of required tests is nine, whereas for an SSC CVS two-rail checker the size of the test set is at most five.<>
{"title":"Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers","authors":"N. Jha","doi":"10.1109/FTCS.1989.105603","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105603","url":null,"abstract":"The problem of single stuck-at, stuck-open, and stuck-on fault detection in cascode voltage switch (CVS) parity trees is considered. The results are also applied to parity and two-rail checkers. CVS circuits are dynamic CMOS circuits which can implement both inverting and noninverting functions. If the CVS parity tree consists of only differential cascode voltage switch (DCVS) EX-OR gates, then it is shown that at most only five tests are needed for detecting all single stuck-at, stuck-open, and stuck-on faults, independent of the number of primary inputs and the number of inputs to any EX-OR gate in the tree. If, however, only a single-ended output is desired from the tree, than the final gate will be a single-ended cascode voltage switch (SCVS) EX-OR gate. For such a tree it is shown that only eight tests are enough. For a strongly self-checking (SSC) CVS parity checker the number of required tests is nine, whereas for an SSC CVS two-rail checker the size of the test set is at most five.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127914432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105583
B. Becker, U. Sparmann
The authors consider the test pattern generation problem for circuits than compute expressions over some algebraic structure. The relation between the algebraic properties of this structure and its test complexity is analyzed. This relation is looked at in detail for the family of all finite monoids. The test complexity of a monoid with respect to a problem is measured by the number of tests needed to check the best testable circuit (in a certain computational model) that will solve the problem. Two important computations over finite monoids, namely, expression evaluation and parallel prefix computation, are considered. In both cases it can be shown that the set of all finite monoids partitions into exactly three classes with constant, logarithmic, and linear test complexity, respectively. These classes are characterized using algebraic properties. For each class, circuits are provided with optimal test sets and efficient methods, which decide the membership problem for a given finite monoid M.<>
{"title":"Computations over finite monoids and their test complexity","authors":"B. Becker, U. Sparmann","doi":"10.1109/FTCS.1989.105583","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105583","url":null,"abstract":"The authors consider the test pattern generation problem for circuits than compute expressions over some algebraic structure. The relation between the algebraic properties of this structure and its test complexity is analyzed. This relation is looked at in detail for the family of all finite monoids. The test complexity of a monoid with respect to a problem is measured by the number of tests needed to check the best testable circuit (in a certain computational model) that will solve the problem. Two important computations over finite monoids, namely, expression evaluation and parallel prefix computation, are considered. In both cases it can be shown that the set of all finite monoids partitions into exactly three classes with constant, logarithmic, and linear test complexity, respectively. These classes are characterized using algebraic properties. For each class, circuits are provided with optimal test sets and efficient methods, which decide the membership problem for a given finite monoid M.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128123011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105580
J. Bolot, P. Jalote
Linguistic mechanisms for exception handling facilitate the production of reliable software and play an important role in fault-tolerant computing. A description is given of the functional semantics of a Pascal-like language which supports exception handling. A program with exceptions is considered as having a standard semantics, as well as an exceptional semantics for each exception that may be signaled during its execution. Standard functional semantics methods provide rules to obtain the function representing the standard semantics. The authors provide rules to determine the functions representing the exceptional semantics. Computing these functions also provides the exceptional domains of the program, i.e. the sets of initial conditions that will result in exceptions being signaled.<>
{"title":"Formal verification of programs with exceptions","authors":"J. Bolot, P. Jalote","doi":"10.1109/FTCS.1989.105580","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105580","url":null,"abstract":"Linguistic mechanisms for exception handling facilitate the production of reliable software and play an important role in fault-tolerant computing. A description is given of the functional semantics of a Pascal-like language which supports exception handling. A program with exceptions is considered as having a standard semantics, as well as an exceptional semantics for each exception that may be signaled during its execution. Standard functional semantics methods provide rules to obtain the function representing the standard semantics. The authors provide rules to determine the functions representing the exceptional semantics. Computing these functions also provides the exceptional domains of the program, i.e. the sets of initial conditions that will result in exceptions being signaled.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130742555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105587
Siu-Cheung Chau, A. L. Liestman
A modular fault-tolerant binary hypercube architecture is proposed that uses redundant processors and is suitable for use in long-life unmaintained applications. Each module initially contains 2/sup i/ (for any >or=0) active processors and k spare processors and is constructed so that each of the spare processors can replace any of the active processors (or any of the other spares) within the module. Thus, the module can tolerate up to k processor faults. This scheme is compared to previously proposed fault-tolerant binary hypercube architectures. It is shown that the scheme can achieve the same level of reliability as other proposed schemes while using significantly fewer spares.<>
{"title":"A proposal for a fault-tolerant binary hypercube architecture","authors":"Siu-Cheung Chau, A. L. Liestman","doi":"10.1109/FTCS.1989.105587","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105587","url":null,"abstract":"A modular fault-tolerant binary hypercube architecture is proposed that uses redundant processors and is suitable for use in long-life unmaintained applications. Each module initially contains 2/sup i/ (for any >or=0) active processors and k spare processors and is constructed so that each of the spare processors can replace any of the active processors (or any of the other spares) within the module. Thus, the module can tolerate up to k processor faults. This scheme is compared to previously proposed fault-tolerant binary hypercube architectures. It is shown that the scheme can achieve the same level of reliability as other proposed schemes while using significantly fewer spares.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133608273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105548
J. Trotter, W. Moore
An image processing architecture designed for ultralarge-scale and wafer-scale integration which uses a novel fault-tolerance strategy is described. The strategy overcomes many of the problems associated with configuring a 2D array from cells and spares with some kind of switching network. It provides a novel approach to fault tolerance because the primary mechanism for tolerating faults is neither hardware redundancy nor time redundancy but is a trade against processing resolution. The architecture provides a working, gracefully degrading array for image processing.<>
{"title":"Imperfectly connected 2D arrays for image processing","authors":"J. Trotter, W. Moore","doi":"10.1109/FTCS.1989.105548","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105548","url":null,"abstract":"An image processing architecture designed for ultralarge-scale and wafer-scale integration which uses a novel fault-tolerance strategy is described. The strategy overcomes many of the problems associated with configuring a 2D array from cells and spares with some kind of switching network. It provides a novel approach to fault tolerance because the primary mechanism for tolerating faults is neither hardware redundancy nor time redundancy but is a trade against processing resolution. The architecture provides a working, gracefully degrading array for image processing.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127985734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105564
N. Speirs, P. Barrett
As part of the European Strategic Programme for Research in Information Technology (ESPRIT), the Delta-4 project is seeking to define an open, fault-tolerant, distributed computing architecture. The Delta-4 approach to fault tolerance is based on the replication of software components on distinct host computers. Both active and passive replication strategies are contained within the framework of Delta-4. The philosophy behind the mechanisms used within the passive replication paradigm is presented. In the Delta-4 approach, backward error recovery is achieved by integrating checkpointing with interprocess communication. This approach is seen to be applicable to both deterministic and nondeterministic programs. A description is also given of the implementation of such a system within the overall Delta-4 framework.<>
{"title":"Using passive replicates in Delta-4 to provide dependable distributed computing","authors":"N. Speirs, P. Barrett","doi":"10.1109/FTCS.1989.105564","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105564","url":null,"abstract":"As part of the European Strategic Programme for Research in Information Technology (ESPRIT), the Delta-4 project is seeking to define an open, fault-tolerant, distributed computing architecture. The Delta-4 approach to fault tolerance is based on the replication of software components on distinct host computers. Both active and passive replication strategies are contained within the framework of Delta-4. The philosophy behind the mechanisms used within the passive replication paradigm is presented. In the Delta-4 approach, backward error recovery is achieved by integrating checkpointing with interprocess communication. This approach is seen to be applicable to both deterministic and nondeterministic programs. A description is also given of the implementation of such a system within the overall Delta-4 framework.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116711628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-06-21DOI: 10.1109/FTCS.1989.105547
L. M. Napolitano, D. Andaleon, K. Berry, P. R. Bryson, S. R. Klapp, J. Leeper, G. Redinbo
Starloc (Sandia target location computer), a special-purpose computer for locating 3D objects in a 2D image using a generalized correlation filter algorithm, is described. Starloc performs high-speed 2D convolution/correlation using commercially available floating-point processors and was designed with fault tolerance as a central feature. Its basic architecture consists of ten pipeline stages (eight for fast Fourier transform (FFT) processing and two for pixel-by-pixel weighting), arranged in a ringlike structure that includes two hot-standby stages for replacing any failed stage. Protection techniques from bit-level parity up through algorithm-based methods are used. All data paths involving memory through and within the distributed sections are covered by standard binary error-correcting codes. The floating-point processors are duplicated and surrounded by appropriate comparison circuits to detect failures while the overall system function is protected by algorithm-based checks. Dual bit-slice sequencers use internal comparators and the regular memory addressing in both FFT and weighting sections uses fault-tolerant counters. Design and fabrication of a prototype have been completed.<>
{"title":"Fault-tolerance in a high-speed 2D convolver/correlator: Starloc","authors":"L. M. Napolitano, D. Andaleon, K. Berry, P. R. Bryson, S. R. Klapp, J. Leeper, G. Redinbo","doi":"10.1109/FTCS.1989.105547","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105547","url":null,"abstract":"Starloc (Sandia target location computer), a special-purpose computer for locating 3D objects in a 2D image using a generalized correlation filter algorithm, is described. Starloc performs high-speed 2D convolution/correlation using commercially available floating-point processors and was designed with fault tolerance as a central feature. Its basic architecture consists of ten pipeline stages (eight for fast Fourier transform (FFT) processing and two for pixel-by-pixel weighting), arranged in a ringlike structure that includes two hot-standby stages for replacing any failed stage. Protection techniques from bit-level parity up through algorithm-based methods are used. All data paths involving memory through and within the distributed sections are covered by standard binary error-correcting codes. The floating-point processors are duplicated and surrounded by appropriate comparison circuits to detect failures while the overall system function is protected by algorithm-based checks. Dual bit-slice sequencers use internal comparators and the regular memory addressing in both FFT and weighting sections uses fault-tolerant counters. Design and fabrication of a prototype have been completed.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116912902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-03-01DOI: 10.1109/FTCS.1989.105551
S. Devadas, Hi-Keung Tony Ma
A synthesis procedure, which begins with a state transition graph description of a sequential machine and produces an optimized, easily testable PLA (programmable logic array) based logic implementation, is outlined. A procedure is proposed for constrained state assignment and logic optimization that guarantee testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented to illustrate the efficacy of this procedure. The area/performance penalties in return for easy testability are small.<>
{"title":"Easily testable PLA-based finite state machines","authors":"S. Devadas, Hi-Keung Tony Ma","doi":"10.1109/FTCS.1989.105551","DOIUrl":"https://doi.org/10.1109/FTCS.1989.105551","url":null,"abstract":"A synthesis procedure, which begins with a state transition graph description of a sequential machine and produces an optimized, easily testable PLA (programmable logic array) based logic implementation, is outlined. A procedure is proposed for constrained state assignment and logic optimization that guarantee testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented to illustrate the efficacy of this procedure. The area/performance penalties in return for easy testability are small.<<ETX>>","PeriodicalId":230363,"journal":{"name":"[1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133068353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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