Boundary-scan technology is a popular design-for-test technology, which is used by some embedded chips by means of embedding special boundary scan cells inside the circuits. It allows the debugger to talk via a JTAG port directly to the IC's core. As more and more chips using the JTAG interface, the application of JTAG emulator becomes frequent. Commercial JTAG emulators using parallel port on the market are usually expensive and inconvenience. This paper describes two methods to design an inexpensive USB interface JTAG emulator based on a single-chip ARM, including theirs hardware and software. One is the GPIO pins of an ARM device are used to generate TAP timing and its USB port is used to communicate with PC. Another is used the SPI interface to generate higher TCK. Result shows that this emulator not only has high speed but also is portable.
{"title":"Design and Implementation of a Single-Chip ARM-Based USB Interface JTAG Emulator","authors":"Xuhui Chen, Dengyi Zhang, Hongyun Yang","doi":"10.1109/SEC.2008.13","DOIUrl":"https://doi.org/10.1109/SEC.2008.13","url":null,"abstract":"Boundary-scan technology is a popular design-for-test technology, which is used by some embedded chips by means of embedding special boundary scan cells inside the circuits. It allows the debugger to talk via a JTAG port directly to the IC's core. As more and more chips using the JTAG interface, the application of JTAG emulator becomes frequent. Commercial JTAG emulators using parallel port on the market are usually expensive and inconvenience. This paper describes two methods to design an inexpensive USB interface JTAG emulator based on a single-chip ARM, including theirs hardware and software. One is the GPIO pins of an ARM device are used to generate TAP timing and its USB port is used to communicate with PC. Another is used the SPI interface to generate higher TCK. Result shows that this emulator not only has high speed but also is portable.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129588508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Early power estimation is important to guide architectural design, especially for embedded systems. Since the power consumption of memory subsystem dominates, while DRAM and NAND Flash are the two main storage mediums nowadays, we analyze the power model of DRAM and propose a power model for NAND Flash, considering its system-level behaviors. Experimental results show that the accuracy of model proposed can be up to 95% .
{"title":"System-Level Early Power Estimation for Memory Subsystem in Embedded Systems","authors":"J. Ji, Chao Wang, Xuehai Zhou","doi":"10.1109/SEC.2008.48","DOIUrl":"https://doi.org/10.1109/SEC.2008.48","url":null,"abstract":"Early power estimation is important to guide architectural design, especially for embedded systems. Since the power consumption of memory subsystem dominates, while DRAM and NAND Flash are the two main storage mediums nowadays, we analyze the power model of DRAM and propose a power model for NAND Flash, considering its system-level behaviors. Experimental results show that the accuracy of model proposed can be up to 95% .","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117211594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shi Qingsong, Feng Degui, Jijun Ma, Nan Zhang, Tianzhou Chen
The need of extensive computing capacity is expanding all the time. Especially in company providing network service, adding servers physically requires much more cost. Also in embedded system, resource is also very limited. That is why virtulization is so popular in research and industry application. A lot of virtulization technique is raised to supply great computing capacity with multiple operating system running synchronously in a single real machine. Of all the aspects affecting real time performance of a computer, I/O processing has played a major role. Because I/O bound process has to wait for device to be free and thus increase response time which may delay them go beyond deadline. The system-on-a-chip technology provides the scratch-pad memory(SPM), which is small, isolated and located on chip. We implement a little operating system running in SPM (SPMOS). The SPMOS provide virtual I/O interface for general operating system. Different I/O requestis buffered and scheduled if necessary. Also, with proper memory checking mechanism, we could prevent malicious attacks on SPM, which means that any program running in the SPM could be protected effectively. Experiment shows that the SPMOS based virtual I/O interface is efficient and practical.
{"title":"Dual OS Support Peripheral Device Encapsulation","authors":"Shi Qingsong, Feng Degui, Jijun Ma, Nan Zhang, Tianzhou Chen","doi":"10.1109/SEC.2008.31","DOIUrl":"https://doi.org/10.1109/SEC.2008.31","url":null,"abstract":"The need of extensive computing capacity is expanding all the time. Especially in company providing network service, adding servers physically requires much more cost. Also in embedded system, resource is also very limited. That is why virtulization is so popular in research and industry application. A lot of virtulization technique is raised to supply great computing capacity with multiple operating system running synchronously in a single real machine. Of all the aspects affecting real time performance of a computer, I/O processing has played a major role. Because I/O bound process has to wait for device to be free and thus increase response time which may delay them go beyond deadline. The system-on-a-chip technology provides the scratch-pad memory(SPM), which is small, isolated and located on chip. We implement a little operating system running in SPM (SPMOS). The SPMOS provide virtual I/O interface for general operating system. Different I/O requestis buffered and scheduled if necessary. Also, with proper memory checking mechanism, we could prevent malicious attacks on SPM, which means that any program running in the SPM could be protected effectively. Experiment shows that the SPMOS based virtual I/O interface is efficient and practical.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115710492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiang Guan-jun, Ma Jijun, Zheng Zhenwei, Chen Tianzhou
With the development of ubiquitous computing and ambient intelligence, the requirement of embedding data and evaluating database queries is a growing variety of ultra-light computing devices. In the same time, embedded system and system-on-chip (SoC) architecture are becoming commonly used in computing area, because of the low design cost and extensible architecture. We design a special system called DBoC (database on chip) in our previous paper, in which there is a special core for SQLs running. In this paper, we present a DBoC with high speed buffer support to accelerate the data access.The method used in this paper to accelerate access is that we add a high speed buffer between DBoC and main memory. This method likes a data cache, but the data cache is passive for data access and is not useful in database because the locality in database is not good. on the contrary, our method is active, because we design a powerful BC (buffer controller) for data exchanging and signal transmission. The experiment shows significant efficiency improvement of SQLs in DBoC. The efficiency improvement of create table, drop table, select, insert, delete and update are 30.0%, 28.2%, 57.4%, 23.8%, 59.7% and 55.5% respectively.
随着普适计算和环境智能的发展，各种超轻计算设备对嵌入数据和评估数据库查询的要求越来越高。与此同时，嵌入式系统和片上系统(SoC)架构因其设计成本低和架构可扩展性强而在计算领域得到越来越广泛的应用。在上一篇论文中，我们设计了一个特殊的DBoC (database on chip)系统，其中有一个专门的sql运行内核。在本文中，我们提出了一个具有高速缓冲支持的DBoC来加速数据访问。本文采用的加速存取的方法是在DBoC和主存之间增加高速缓冲区。这种方法类似于数据缓存，但数据缓存对于数据访问是被动的，并且在数据库中用处不大，因为数据库中的局部性不好。相反，我们的方法是主动的，因为我们设计了一个强大的BC(缓冲控制器)进行数据交换和信号传输。实验表明，sql在DBoC中的效率得到了显著提高。创建表、删除表、选择、插入、删除和更新的效率提高分别为30.0%、28.2%、57.4%、23.8%、59.7%和55.5%。
{"title":"H/S Co-design of Embedded DBMS with High Speed Buffer Support","authors":"Jiang Guan-jun, Ma Jijun, Zheng Zhenwei, Chen Tianzhou","doi":"10.1109/SEC.2008.24","DOIUrl":"https://doi.org/10.1109/SEC.2008.24","url":null,"abstract":"With the development of ubiquitous computing and ambient intelligence, the requirement of embedding data and evaluating database queries is a growing variety of ultra-light computing devices. In the same time, embedded system and system-on-chip (SoC) architecture are becoming commonly used in computing area, because of the low design cost and extensible architecture. We design a special system called DBoC (database on chip) in our previous paper, in which there is a special core for SQLs running. In this paper, we present a DBoC with high speed buffer support to accelerate the data access.The method used in this paper to accelerate access is that we add a high speed buffer between DBoC and main memory. This method likes a data cache, but the data cache is passive for data access and is not useful in database because the locality in database is not good. on the contrary, our method is active, because we design a powerful BC (buffer controller) for data exchanging and signal transmission. The experiment shows significant efficiency improvement of SQLs in DBoC. The efficiency improvement of create table, drop table, select, insert, delete and update are 30.0%, 28.2%, 57.4%, 23.8%, 59.7% and 55.5% respectively.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124753308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hardware/software partitioning is a key problem in hardware/software co-design. This paper presents a new hardware/software partitioning methodology based on improved particle swarm optimization algorithm. The model of the embedded system was constructed by directed acyclic graph to obtain the objective function. Then improvement strategies are introduced in order to overcome the problems of low precision and divergence in traditional particle swarm optimization algorithm. The improved algorithm can avoid local optimal solution efficiently and be conveniently implemented in the field of hardware/software partitioning.
{"title":"The Hardware/Software Partitioning in Embedded System by Improved Particle Swarm Optimization Algorithm","authors":"Qiaoling Tong, X. Zou, Qiao Zhang, Fei Gao, Hengqing Tong","doi":"10.1109/SEC.2008.23","DOIUrl":"https://doi.org/10.1109/SEC.2008.23","url":null,"abstract":"Hardware/software partitioning is a key problem in hardware/software co-design. This paper presents a new hardware/software partitioning methodology based on improved particle swarm optimization algorithm. The model of the embedded system was constructed by directed acyclic graph to obtain the objective function. Then improvement strategies are introduced in order to overcome the problems of low precision and divergence in traditional particle swarm optimization algorithm. The improved algorithm can avoid local optimal solution efficiently and be conveniently implemented in the field of hardware/software partitioning.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115579597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To satisfy the requirement of embedded video encoder in various scenarios, an embedded multi-channel video coding system based on multimedia processor-DM642 DSP is designed in this paper. For real-time application requirement, we optimize the encoder at three levels: Firstly, at algorithm level, develop some fast algorithm fitting for DSP; secondly, at system level, adjust the architecture of encoder and optimization data transfer with EDMA; thirdly, at code level, use linear assembly for key code. Experimental results show that the embedded video encoder can compress four channel CIF video data real-time.
{"title":"Embedded Multi-Channel Video Encoder Based on DSP","authors":"Yao Chunlian, L. Wei, Meng Qinglei, G. Lihua","doi":"10.1109/SEC.2008.30","DOIUrl":"https://doi.org/10.1109/SEC.2008.30","url":null,"abstract":"To satisfy the requirement of embedded video encoder in various scenarios, an embedded multi-channel video coding system based on multimedia processor-DM642 DSP is designed in this paper. For real-time application requirement, we optimize the encoder at three levels: Firstly, at algorithm level, develop some fast algorithm fitting for DSP; secondly, at system level, adjust the architecture of encoder and optimization data transfer with EDMA; thirdly, at code level, use linear assembly for key code. Experimental results show that the embedded video encoder can compress four channel CIF video data real-time.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116684179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Placement machine is the most critical equipment of SMT (surface mount technology). Using visual location technology in its pick and place process can offer a high speed and precision component placement. This paper presents a visual location system based on machine vision for the placement machine. It begins with an introduction of placement machine and then describes the design and implementation of the visual location system. In the system, two key techniques are completed by secondary development based on VisionPro. One is accurate image location that is solved by the pattern-based location algorithms of PatMax. The other one, camera calibration, is achieved by image warping technology through the checkerboard plate. Moreover, this system can give good performances such as high image locating accuracy with 1/40 sub-pixels, high anti-jamming, and high-speed location of objects whose appearance is rotated, scaled, and/or stretched.
{"title":"Visual Location System for Placement Machine Based on Machine Vision","authors":"Luosi Wei, Zongxia Jiao","doi":"10.1109/SEC.2008.41","DOIUrl":"https://doi.org/10.1109/SEC.2008.41","url":null,"abstract":"Placement machine is the most critical equipment of SMT (surface mount technology). Using visual location technology in its pick and place process can offer a high speed and precision component placement. This paper presents a visual location system based on machine vision for the placement machine. It begins with an introduction of placement machine and then describes the design and implementation of the visual location system. In the system, two key techniques are completed by secondary development based on VisionPro. One is accurate image location that is solved by the pattern-based location algorithms of PatMax. The other one, camera calibration, is achieved by image warping technology through the checkerboard plate. Moreover, this system can give good performances such as high image locating accuracy with 1/40 sub-pixels, high anti-jamming, and high-speed location of objects whose appearance is rotated, scaled, and/or stretched.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131677725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained tradeoffs in the power-delay tradeoff curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and precisions. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bitwidth of each sub-adder.
{"title":"Design of Heterogeneous Adders Based on Power-Delay Tradeoffs","authors":"Sanghoon Kwak, D. Har, Jeong-Gun Lee, Jeong-A Lee","doi":"10.1109/SEC.2008.63","DOIUrl":"https://doi.org/10.1109/SEC.2008.63","url":null,"abstract":"The performance of arithmetic adders varies widely in their power consumption, delay, and area requirements. To acquire more fine-grained tradeoffs in the power-delay tradeoff curve of a binary adder, the heterogeneous adder architecture is adopted. In heterogeneous adder architecture, a binary adder is decomposed into sub-adder blocks with different carry propagation schemes and precisions. Thus the method allows us to expand the original design space of a specific type of adder into the more fine-grained design space by mixing that of each sub-adder. In this paper, a design for heterogeneous adder through power optimization under delay constraints or delay optimization under power constraints was presented by determining the bitwidth of each sub-adder.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132201000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Song-He Liu, Xiang-Mo Zhao, Jun Zhang, Ya-Nan Huang
Flash memory is a kind of common storage device. Its characteristics of flexibility, low power, and so on offer excellent qualifications for embedded system and mobile system. But flash memory must be written after erasure operation, and the most important thing is that the erasure operation times are very limitable. For assurance of long time availability, data must be distributed over all memory space reasonably and politic, which brings forward challenge for storage system designer. This paper analyses the data structure and physical characteristics of typical flash memory. And a static trigger wear-leveling strategy based on classifying data with trigger condition is brought forward, called STWL. STWL forces these static data to move over all memory space according to the trigger condition so as to avoid some certain data blocks being damaged in advance. An experiment is carried out to simulate this strategy using VHDL. We construct a 4M bytes RAM as flash memory simulation model, a static wear-leveling unit to implement STWL and an excitation generation unit to yield memory store/load operations, As a result, the wear-leveling rate improves. 33% of space recycle times can be reduced and the biggest gap of number of erasing times of data block decreases from 883% to 38%.
{"title":"A Static Trigger Wear-Leveling Strategy for Flash Memory In Embedded System","authors":"Song-He Liu, Xiang-Mo Zhao, Jun Zhang, Ya-Nan Huang","doi":"10.1109/SEC.2008.18","DOIUrl":"https://doi.org/10.1109/SEC.2008.18","url":null,"abstract":"Flash memory is a kind of common storage device. Its characteristics of flexibility, low power, and so on offer excellent qualifications for embedded system and mobile system. But flash memory must be written after erasure operation, and the most important thing is that the erasure operation times are very limitable. For assurance of long time availability, data must be distributed over all memory space reasonably and politic, which brings forward challenge for storage system designer. This paper analyses the data structure and physical characteristics of typical flash memory. And a static trigger wear-leveling strategy based on classifying data with trigger condition is brought forward, called STWL. STWL forces these static data to move over all memory space according to the trigger condition so as to avoid some certain data blocks being damaged in advance. An experiment is carried out to simulate this strategy using VHDL. We construct a 4M bytes RAM as flash memory simulation model, a static wear-leveling unit to implement STWL and an excitation generation unit to yield memory store/load operations, As a result, the wear-leveling rate improves. 33% of space recycle times can be reduced and the biggest gap of number of erasing times of data block decreases from 883% to 38%.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"1164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134319143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dianjun Wang, Hongxing Wei, Xiaohui Wang, Aiming Shen, R. Fujun
For service robot vision localization requirements, the localization technology research based on the image SIFT characteristic was introduced. The space examination, the precise positions of characteristic points, the direction parameters of the assigned operator and the description of the characteristic point were analyzed. At the same time, the stability under the condition of image zoom, rotation and affine transformation was analyzed according to experiments. Experiments result shows that the SIFT characteristic has the proportion zoom invariability, the revolving invariability, the part affine invariability and a high recognition rate at complex environments. On the basis of above work, the vision localization method based on SIFT characteristic turns out to be an applicable technology in in-building complex environment.
{"title":"Research on Service Robot Vision Alignment Algorithm Based on the SIFT Characteristic","authors":"Dianjun Wang, Hongxing Wei, Xiaohui Wang, Aiming Shen, R. Fujun","doi":"10.1109/SEC.2008.10","DOIUrl":"https://doi.org/10.1109/SEC.2008.10","url":null,"abstract":"For service robot vision localization requirements, the localization technology research based on the image SIFT characteristic was introduced. The space examination, the precise positions of characteristic points, the direction parameters of the assigned operator and the description of the characteristic point were analyzed. At the same time, the stability under the condition of image zoom, rotation and affine transformation was analyzed according to experiments. Experiments result shows that the SIFT characteristic has the proportion zoom invariability, the revolving invariability, the part affine invariability and a high recognition rate at complex environments. On the basis of above work, the vision localization method based on SIFT characteristic turns out to be an applicable technology in in-building complex environment.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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