Qikui Wang, Wei Li, Youdong Chen, Hongxing Wei, Yong Zou
NC program processor is an important module in Computer Numerical Control (CNC) system. NC program processor is divided into interpreter and look-ahead function. In the paper, the macro variable computation, the geometric transformation and the look-ahead pre-interpolation which is widely adopted in machining small-line blocks are introduced for their importance in modern CNC system. The former two works are executed in the interpreter, and the last one is performed in look-ahead pre-interpolation function. A method for five formats of computing macro variable is proposed as well as the proportion and rotation transformation in the interpreter. Then, four conditions including angle constraint between two NC blocks, chord constraint rule, length of the small-line and monotone rule are also discussed. NC program processor is implemented in an embedded control system based ARM (advanced RISC machine), DSP (digital signal processor) and FPGA (field programmable gate array) processors. Experiments show the system is reliable.
{"title":"Research of NC Program Processor in Embedded Control System","authors":"Qikui Wang, Wei Li, Youdong Chen, Hongxing Wei, Yong Zou","doi":"10.1109/SEC.2008.17","DOIUrl":"https://doi.org/10.1109/SEC.2008.17","url":null,"abstract":"NC program processor is an important module in Computer Numerical Control (CNC) system. NC program processor is divided into interpreter and look-ahead function. In the paper, the macro variable computation, the geometric transformation and the look-ahead pre-interpolation which is widely adopted in machining small-line blocks are introduced for their importance in modern CNC system. The former two works are executed in the interpreter, and the last one is performed in look-ahead pre-interpolation function. A method for five formats of computing macro variable is proposed as well as the proportion and rotation transformation in the interpreter. Then, four conditions including angle constraint between two NC blocks, chord constraint rule, length of the small-line and monotone rule are also discussed. NC program processor is implemented in an embedded control system based ARM (advanced RISC machine), DSP (digital signal processor) and FPGA (field programmable gate array) processors. Experiments show the system is reliable.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122784267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the development of the micro-electronics and computer technology, especially with the expansion of field programmable gate array (FPGA), the reconfigurable system technology is becoming the key issue of research and application. In this paper, the principle of the dynamically reconfigurable FPGA, the method and flow of the configurable design are introduced. Based on the application requirement of the modular reconfigurable robot (MRR), a designing method of reconfigurable robot controller is proposed, which is based on the Advanced RISC Machine (ARM) processor and FPGA. The design principle, internal logic function design and the design course of the reconfiguration method are presented. Finally, the experiments of the MRR prove the feasibility of the reconfigurable robot controller to different configuration requirement of MRR and the efficiency of the software and hardware resource.
{"title":"Design of a Reconfigurable Robot Controller Based on FPGA","authors":"M. Xu, Wenzhang Zhu, Ying Zou","doi":"10.1109/SEC.2008.33","DOIUrl":"https://doi.org/10.1109/SEC.2008.33","url":null,"abstract":"With the development of the micro-electronics and computer technology, especially with the expansion of field programmable gate array (FPGA), the reconfigurable system technology is becoming the key issue of research and application. In this paper, the principle of the dynamically reconfigurable FPGA, the method and flow of the configurable design are introduced. Based on the application requirement of the modular reconfigurable robot (MRR), a designing method of reconfigurable robot controller is proposed, which is based on the Advanced RISC Machine (ARM) processor and FPGA. The design principle, internal logic function design and the design course of the reconfiguration method are presented. Finally, the experiments of the MRR prove the feasibility of the reconfigurable robot controller to different configuration requirement of MRR and the efficiency of the software and hardware resource.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124791792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In many embedded system, researches focus on how to use on-chip memory, like SPM, to reduce the energy consumption generated by off-chip memory, such as SDRAM or DRAM. They put the often use instructions and important data into on-chip memory to reduce the power because off-chip memory consumes a large of energy than on-chip memory. However, stack is a key factor that impacts the power consumption, since when function is called, the passing parameter, local variables and temporary data will use stack. We organize a shadow stack scratch-pad memory which operation behavior is somewhat like Cache, to store the stack data to reduce the stack access of off-chip memory. This memory architecture is called S3PM. The S3PM has two segments to remap the off-chip memory, leading CPU to access the S3PM when the access address is in the range of remapped area byS3PM. The paper proposes a novel memory subsystem architecture which constituted by the off-chip SDRAM, on-chip S3PM and traditional SPM. The S3PM is used to remap the stack off-chip memory which address is accessed high frequently while traditional SPM is used to store instruction and data. The results shows that the S3PM can reduce many energy but using a little size of on-chip memory.
{"title":"Shadow Stack Scratch-Pad-Memory for Low Power SoC","authors":"Ling Ming, Shi Xianqiang, Zhang Yu","doi":"10.1109/SEC.2008.74","DOIUrl":"https://doi.org/10.1109/SEC.2008.74","url":null,"abstract":"In many embedded system, researches focus on how to use on-chip memory, like SPM, to reduce the energy consumption generated by off-chip memory, such as SDRAM or DRAM. They put the often use instructions and important data into on-chip memory to reduce the power because off-chip memory consumes a large of energy than on-chip memory. However, stack is a key factor that impacts the power consumption, since when function is called, the passing parameter, local variables and temporary data will use stack. We organize a shadow stack scratch-pad memory which operation behavior is somewhat like Cache, to store the stack data to reduce the stack access of off-chip memory. This memory architecture is called S3PM. The S3PM has two segments to remap the off-chip memory, leading CPU to access the S3PM when the access address is in the range of remapped area byS3PM. The paper proposes a novel memory subsystem architecture which constituted by the off-chip SDRAM, on-chip S3PM and traditional SPM. The S3PM is used to remap the stack off-chip memory which address is accessed high frequently while traditional SPM is used to store instruction and data. The results shows that the S3PM can reduce many energy but using a little size of on-chip memory.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127132476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bin Yao, Haisen S. Li, Tian Zhou, Baowei Chen, H. Yu
Multiple sub-array beam-space MUSIC (MSB-MUSIC) is a new beam-space high resolution DOA estimation algorithm. In order to solve the problem of huge computation load of the algorithm, a real-time processing scheme based on FPGA and DSP array is proposed and implemented on the hardware. In the hardware platform MSB-MUSIC with 80 channels data is real-time implemented, where both the digital down conversion based on CORDIC and the eigenvalue decomposition using the two-side CORDIC based parallel Jacobi algorithm are implemented on the FPGA. The calculation of the covariance matrix and MUSIC angular spectra are implemented on DSP array, respectively. The parallel processing platform has been applied to the shallow water high resolution multi-beam echo sounder, and the lake test proves that the system can achieve the high performance.
{"title":"Real-Time Implementation of Multiple Sub-array Beam-Space MUSIC Based on FPGA and DSP Array","authors":"Bin Yao, Haisen S. Li, Tian Zhou, Baowei Chen, H. Yu","doi":"10.1109/SEC.2008.6","DOIUrl":"https://doi.org/10.1109/SEC.2008.6","url":null,"abstract":"Multiple sub-array beam-space MUSIC (MSB-MUSIC) is a new beam-space high resolution DOA estimation algorithm. In order to solve the problem of huge computation load of the algorithm, a real-time processing scheme based on FPGA and DSP array is proposed and implemented on the hardware. In the hardware platform MSB-MUSIC with 80 channels data is real-time implemented, where both the digital down conversion based on CORDIC and the eigenvalue decomposition using the two-side CORDIC based parallel Jacobi algorithm are implemented on the FPGA. The calculation of the covariance matrix and MUSIC angular spectra are implemented on DSP array, respectively. The parallel processing platform has been applied to the shallow water high resolution multi-beam echo sounder, and the lake test proves that the system can achieve the high performance.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116931358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we address the problem of maximizing sensor networks lifetime under coverage constraint. A Distributed Coverage Control Strategy based on Precise Coverage Degree (DSP) is proposed for both homogeneous and heterogeneous sensor networks randomly deployed. We extend the coverage degree concept by defining Pure Coverage and Joint Coverage. DSP adopts the probabilistic sense model, which is a more practical model compared with the binary sensing model. In DSP, each node calculates the coverage degree locally, so it can provide differentiated service of coverage degree, which can be adjusted dynamically according to the precision requirement by the application. Our protocol takes the complicated boundary effect into account. Experiments results show that with k-coverage guarantee, DSP can reduce the number of the active nodes and prolong the networks lifetime effectively. In addition, DSP can balance the energy consumption, and the protocol needs limited communication.
{"title":"A Precise Coverage Control Protocol with Limited Communication in Wireless Sensor Networks","authors":"Hanmei Luo, Huanzhao Wang","doi":"10.1109/SEC.2008.66","DOIUrl":"https://doi.org/10.1109/SEC.2008.66","url":null,"abstract":"In this paper, we address the problem of maximizing sensor networks lifetime under coverage constraint. A Distributed Coverage Control Strategy based on Precise Coverage Degree (DSP) is proposed for both homogeneous and heterogeneous sensor networks randomly deployed. We extend the coverage degree concept by defining Pure Coverage and Joint Coverage. DSP adopts the probabilistic sense model, which is a more practical model compared with the binary sensing model. In DSP, each node calculates the coverage degree locally, so it can provide differentiated service of coverage degree, which can be adjusted dynamically according to the precision requirement by the application. Our protocol takes the complicated boundary effect into account. Experiments results show that with k-coverage guarantee, DSP can reduce the number of the active nodes and prolong the networks lifetime effectively. In addition, DSP can balance the energy consumption, and the protocol needs limited communication.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"432 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123035162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An appropriate formal model should be established to perform simulation analysis in prophase of embedded system design. This paper analyzes the current Petri net models and presents an EPRES model which gives its structural definition, graphical representation and behavioral rules concretely. The places were extended to two types such as control places and data places in EPRES. Transition function and transition time delay were introduced. Then EPRES can specify and analyze the function realization, resource consumption and time constraint. Finally, an example of the EPRES representation of an embedded system is given to show that EPRES is suitable for embedded system modeling.
{"title":"An Extended Petri Net EPRES for Embedded System Modeling","authors":"Sen Liu, C. Mu","doi":"10.1109/SEC.2008.42","DOIUrl":"https://doi.org/10.1109/SEC.2008.42","url":null,"abstract":"An appropriate formal model should be established to perform simulation analysis in prophase of embedded system design. This paper analyzes the current Petri net models and presents an EPRES model which gives its structural definition, graphical representation and behavioral rules concretely. The places were extended to two types such as control places and data places in EPRES. Transition function and transition time delay were introduced. Then EPRES can specify and analyze the function realization, resource consumption and time constraint. Finally, an example of the EPRES representation of an embedded system is given to show that EPRES is suitable for embedded system modeling.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133756275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In wireless sensor networks (WSNs), secure data aggregation is an important application. Previous works are implemented by authentication among neighboring sensors. Considering that in many cases, data aggregation is both spatial and temporal correlation, this paper proposes a distributed and localized secure data aggregation algorithm based on behavior trust (BTDA). The security and reliability of the algorithm are implemented by using statistical hypothesis test for matching the reading sequence of sensors and statistical characteristics of the data aggregation. Simulation shows the algorithm efficiently.
{"title":"A Secure Data Aggregation Algorithm Based on Behavior Trust in Wireless Sensor Networks","authors":"Ming-zheng Zhou, Jin-sheng Xu, Cheng Zhu","doi":"10.1109/SEC.2008.15","DOIUrl":"https://doi.org/10.1109/SEC.2008.15","url":null,"abstract":"In wireless sensor networks (WSNs), secure data aggregation is an important application. Previous works are implemented by authentication among neighboring sensors. Considering that in many cases, data aggregation is both spatial and temporal correlation, this paper proposes a distributed and localized secure data aggregation algorithm based on behavior trust (BTDA). The security and reliability of the algorithm are implemented by using statistical hypothesis test for matching the reading sequence of sensors and statistical characteristics of the data aggregation. Simulation shows the algorithm efficiently.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133180951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Omni-directional mobile robot based on Zigbee technology is designed in this paper according to the conception of remote-cerebellum. The hardware design and realization scheme of primary function module in the robot is introduced in detail. And the analysis and illustration of the robot are also present in this paper.
{"title":"Design and Realization of Omni-directional Mobile Robot Body Based on Zigbee Technology","authors":"Ding Ru, Zheng Tong, Z. Li, L. Gang","doi":"10.1109/SEC.2008.73","DOIUrl":"https://doi.org/10.1109/SEC.2008.73","url":null,"abstract":"The Omni-directional mobile robot based on Zigbee technology is designed in this paper according to the conception of remote-cerebellum. The hardware design and realization scheme of primary function module in the robot is introduced in detail. And the analysis and illustration of the robot are also present in this paper.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122003175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the coal mine, open field or a severe surveillance environment, the use of computers and data collection card to achieve surveillance task is fairly dangerous and unreliable. This paper analyzes platform selection in special surveillance environment based on such problems as the high possibility of flammability and explosion, high humidity and lots of dust in surveillance environment, and the inconvenience of separate, long distance surveillance fields. It also proposes the concept of establishing the embedded surveillance platform. Finally a surveillance platform based on system on programmable chip (SOPC) is presented. The result shows that the embedded platform can afford the task in severe environment.
{"title":"Research on Embedded Surveillance Platform in Severe Environment","authors":"Ma Sen, Shang Yuan-yuan, Jie Yi, Bai Meng","doi":"10.1109/SEC.2008.39","DOIUrl":"https://doi.org/10.1109/SEC.2008.39","url":null,"abstract":"In the coal mine, open field or a severe surveillance environment, the use of computers and data collection card to achieve surveillance task is fairly dangerous and unreliable. This paper analyzes platform selection in special surveillance environment based on such problems as the high possibility of flammability and explosion, high humidity and lots of dust in surveillance environment, and the inconvenience of separate, long distance surveillance fields. It also proposes the concept of establishing the embedded surveillance platform. Finally a surveillance platform based on system on programmable chip (SOPC) is presented. The result shows that the embedded platform can afford the task in severe environment.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127761946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Validation is one of the most complex and expensive tasks in current Application Specific Instruction Set Processors (ASIP) design process. Many existing approaches employ a multiple-level approach to efficiently design and verify ASIP design. This paper presents a novel extended timed Petri net model called HDPN-Hardware Design based-on Petri Net to model systems at multiple levels, and introduces a verification scheme based on HDPN to satisfy the requirement of Design Space Exploration (DSE). This paper focuses on formal modeling and verification ASIP architecture. And a DLX pipelined processor is presented to demonstrate the validity and usage of this method.
验证是当前应用特定指令集处理器(ASIP)设计过程中最复杂、最昂贵的任务之一。许多现有的方法采用多级方法来有效地设计和验证ASIP设计。提出了一种新的扩展时间Petri网模型——基于Petri网的HDPN-硬件设计模型，对系统进行多层次建模，并介绍了一种基于HDPN的验证方案，以满足设计空间探索(Design Space Exploration, DSE)的要求。本文重点研究了ASIP体系结构的形式化建模和验证。最后以一个DLX流水线处理器为例，验证了该方法的有效性和实用性。
{"title":"Validation of ASIP Architecture Description","authors":"Yanyan Gao, Xi Li, Jie Yu","doi":"10.1109/SEC.2008.49","DOIUrl":"https://doi.org/10.1109/SEC.2008.49","url":null,"abstract":"Validation is one of the most complex and expensive tasks in current Application Specific Instruction Set Processors (ASIP) design process. Many existing approaches employ a multiple-level approach to efficiently design and verify ASIP design. This paper presents a novel extended timed Petri net model called HDPN-Hardware Design based-on Petri Net to model systems at multiple levels, and introduces a verification scheme based on HDPN to satisfy the requirement of Design Space Exploration (DSE). This paper focuses on formal modeling and verification ASIP architecture. And a DLX pipelined processor is presented to demonstrate the validity and usage of this method.","PeriodicalId":231129,"journal":{"name":"2008 Fifth IEEE International Symposium on Embedded Computing","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114496771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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