Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237397
W. Bandurski
The paper presents a fast and effective method of modeling a nonuniform and dispersive interconnect by means of S-parameters. The paper presents an approach based on the method of successive approximations, but taking into account the dependence on the frequency of line parameters. The concept is to use a rational approximation of the per-unit-length parameter of the line calculated for each frequency. An example of the Bessel dispersive transmission line has been considered.
{"title":"Transmission line model with frequency-dependent and nonuniform parameters in frequency and time domain","authors":"W. Bandurski","doi":"10.1109/SAPIW.2015.7237397","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237397","url":null,"abstract":"The paper presents a fast and effective method of modeling a nonuniform and dispersive interconnect by means of S-parameters. The paper presents an approach based on the method of successive approximations, but taking into account the dependence on the frequency of line parameters. The concept is to use a rational approximation of the per-unit-length parameter of the line calculated for each frequency. An example of the Bessel dispersive transmission line has been considered.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117140027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237390
F. Demuynck, L. Eichinger, V. Poisson
Power plane noise is a well-known source of signal integrity (SI) issues in a high speed digital design. This paper first reviews the basic principles which are at the root of the problem. We then illustrate how electronic design automation (EDA) tools can be used to analyze the phenomenon and provide guidance on how to mitigate the issue by adjusting the design.
{"title":"Power plane noise coupling to high speed signals","authors":"F. Demuynck, L. Eichinger, V. Poisson","doi":"10.1109/SAPIW.2015.7237390","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237390","url":null,"abstract":"Power plane noise is a well-known source of signal integrity (SI) issues in a high speed digital design. This paper first reviews the basic principles which are at the root of the problem. We then illustrate how electronic design automation (EDA) tools can be used to analyze the phenomenon and provide guidance on how to mitigate the issue by adjusting the design.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128854052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237400
G. Benoit, Gautier Cyrille, Amedeo Alexandre
The following paper presents the simulation methodology for optimizing the decoupling network of an integrated circuit like a processor or a Field Programmable Gate Array. The efficiency of simulation tools from commercial electronic computer aided design solution is demonstrated by correlating simulation results with measurement for S parameters analysis of bare PCB and the PCB associated with decoupling capacitors thanks to a dedicated test vehicle equipped with SMA connectors allowing S12 parameter measurement. An integrated module of the commercial solution calculating mounted inductance of capacitors is also presented as it is an essential element for decoupling optimization. Design flow is then given for optimizing the decoupling performance of a capacitor network in the case of reusing a electronic design. Surface occupied by decoupling components is firstly reduced and its efficiency increased by reducing mounted inductance. Performances of decoupling network are then analyzed in order to remove all unnecessary elements.
{"title":"Simulation methodology for enhancement of power delivery network decoupling","authors":"G. Benoit, Gautier Cyrille, Amedeo Alexandre","doi":"10.1109/SAPIW.2015.7237400","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237400","url":null,"abstract":"The following paper presents the simulation methodology for optimizing the decoupling network of an integrated circuit like a processor or a Field Programmable Gate Array. The efficiency of simulation tools from commercial electronic computer aided design solution is demonstrated by correlating simulation results with measurement for S parameters analysis of bare PCB and the PCB associated with decoupling capacitors thanks to a dedicated test vehicle equipped with SMA connectors allowing S12 parameter measurement. An integrated module of the commercial solution calculating mounted inductance of capacitors is also presented as it is an essential element for decoupling optimization. Design flow is then given for optimizing the decoupling performance of a capacitor network in the case of reusing a electronic design. Surface occupied by decoupling components is firstly reduced and its efficiency increased by reducing mounted inductance. Performances of decoupling network are then analyzed in order to remove all unnecessary elements.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115276304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237394
Ingvar Karlsson
In production of printed circuit boards (PCB) signal skew will be introduced in differential traces due to the weave effect. A skew that will vary from PCB to PCB. This signal skew generates mode conversion that together with poor common mode properties along the high speed channel will degrade the system performance. For example might the skew effect give a crosstalk much higher than the pure differential crosstalk. If the poor common mode properties in the channel are high and the skew can be expected to be high enough, the channel performance will be affected. Some PCB's, with right combination of skew, might fail with too high bit error rate (BER) and other PCB's will work.
{"title":"Common mode effects in high speed serial links","authors":"Ingvar Karlsson","doi":"10.1109/SAPIW.2015.7237394","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237394","url":null,"abstract":"In production of printed circuit boards (PCB) signal skew will be introduced in differential traces due to the weave effect. A skew that will vary from PCB to PCB. This signal skew generates mode conversion that together with poor common mode properties along the high speed channel will degrade the system performance. For example might the skew effect give a crosstalk much higher than the pure differential crosstalk. If the poor common mode properties in the channel are high and the skew can be expected to be high enough, the channel performance will be affected. Some PCB's, with right combination of skew, might fail with too high bit error rate (BER) and other PCB's will work.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121698589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-05-10DOI: 10.1109/SAPIW.2015.7237402
B. Curran, K. Lang, I. Ndip, H. Potter
Silicon interposer technology with through-silicon-vias will play a significant role in the development of future 2.5D systems. Furthermore, such systems will have high density and real-time computing requirements, leading to smaller sizes and higher bit-rates. In this paper, through-silicon-via structures in normal resistivity silicon with 3 different return current configurations are modeled and measured. It is shown that reflections and attenuations in the transmission structure can be predicted and reduced with predictive modeling using full-wave simulation techniques. With a silicon conductivity of 25 S/m, the examined TSV structures enter the quasi-TEM mode between 10GHz and 20GHz with a transmission coefficient of ca. -3dB. The transmission coefficient decreases between -5dB and -7dB, depending on the design of the structure. Reflection coefficients for all three structures reaches a maximum of -11dB as the structure enters the quasi-TEM mode.
{"title":"Optimization of the return current paths of interposer TSVs for frequencies up to 110GHz","authors":"B. Curran, K. Lang, I. Ndip, H. Potter","doi":"10.1109/SAPIW.2015.7237402","DOIUrl":"https://doi.org/10.1109/SAPIW.2015.7237402","url":null,"abstract":"Silicon interposer technology with through-silicon-vias will play a significant role in the development of future 2.5D systems. Furthermore, such systems will have high density and real-time computing requirements, leading to smaller sizes and higher bit-rates. In this paper, through-silicon-via structures in normal resistivity silicon with 3 different return current configurations are modeled and measured. It is shown that reflections and attenuations in the transmission structure can be predicted and reduced with predictive modeling using full-wave simulation techniques. With a silicon conductivity of 25 S/m, the examined TSV structures enter the quasi-TEM mode between 10GHz and 20GHz with a transmission coefficient of ca. -3dB. The transmission coefficient decreases between -5dB and -7dB, depending on the design of the structure. Reflection coefficients for all three structures reaches a maximum of -11dB as the structure enters the quasi-TEM mode.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116718496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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