Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592557
Koki Narita, M. Okushima
This paper presents a CDM protection design for cross-domain interface circuits using an internal cross clamp as voltage divider between the internal power supply node of analog circuits and the digital GND node. The proposed protection circuit meets high CDM current request from large packaged IC with 16nm FinFET.
{"title":"CDM protection design using internal power node for cross power domain in 16nm CMOS technology","authors":"Koki Narita, M. Okushima","doi":"10.1109/EOSESD.2016.7592557","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592557","url":null,"abstract":"This paper presents a CDM protection design for cross-domain interface circuits using an internal cross clamp as voltage divider between the internal power supply node of analog circuits and the digital GND node. The proposed protection circuit meets high CDM current request from large packaged IC with 16nm FinFET.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123497714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592562
T. Maloney
Heat flow from a surface source to a sink at a specified depth, using uniform "effective" materials parameters, models many power-to-fail (Dwyer) curves, while capturing the Wunsch-Bell relation as the infinite depth limit. A fast-converging series produces the complete thermal impedance function and predicts peak temperature for arbitrary power waveforms.
{"title":"Unified model of 1-D pulsed heating, combining Wunsch-Bell with the Dwyer curve: This paper is co-copyrighted by Intel Corporation and the ESD association","authors":"T. Maloney","doi":"10.1109/EOSESD.2016.7592562","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592562","url":null,"abstract":"Heat flow from a surface source to a sink at a specified depth, using uniform \"effective\" materials parameters, models many power-to-fail (Dwyer) curves, while capturing the Wunsch-Bell relation as the infinite depth limit. A fast-converging series produces the complete thermal impedance function and predicts peak temperature for arbitrary power waveforms.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126521309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EOSESD.2016.7592555
Shih-Hung Chen, D. Linten, G. Hellings, A. Veloso, M. Scholz, R. Boschke, G. Groeseneken, N. Collaert, N. Horiguchi, A. Thean
Beyond 7nm nodes, gate-all-around (GAA) nanowire (NW) is a promising device architecture. However, new architecture can result in intrinsic ESD performance degradation. In this work, we study vfTLP characteristics of GAA ESD devices. Transient analysis bring an in-depth understanding on physical failure mechanism of GAA devices during CDM ESD events.
{"title":"vfTLP characteristics of ESD devices in Si gate-all-around (GAA) nanowires","authors":"Shih-Hung Chen, D. Linten, G. Hellings, A. Veloso, M. Scholz, R. Boschke, G. Groeseneken, N. Collaert, N. Horiguchi, A. Thean","doi":"10.1109/EOSESD.2016.7592555","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592555","url":null,"abstract":"Beyond 7nm nodes, gate-all-around (GAA) nanowire (NW) is a promising device architecture. However, new architecture can result in intrinsic ESD performance degradation. In this work, we study vfTLP characteristics of GAA ESD devices. Transient analysis bring an in-depth understanding on physical failure mechanism of GAA devices during CDM ESD events.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123803357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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