Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592543
N. Wakai, Kunihiro Maki, Futoshi Kaku, K. Hirose, T. Setoya
We considered and proposed an advanced ESD control method with device charged voltage monitored by using voltmeter. This proposal is based on the review of actual breakdown reports and considerations of monitoring method with the investigation of semiconductor devices charge up phenomena.
{"title":"An ESD control method considering the semiconductor device charged voltage","authors":"N. Wakai, Kunihiro Maki, Futoshi Kaku, K. Hirose, T. Setoya","doi":"10.1109/EOSESD.2016.7592543","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592543","url":null,"abstract":"We considered and proposed an advanced ESD control method with device charged voltage monitored by using voltmeter. This proposal is based on the review of actual breakdown reports and considerations of monitoring method with the investigation of semiconductor devices charge up phenomena.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"52 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121015338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592551
Benjamin Viale, M. Fer, L. Courau, P. Galy, B. Jacquier, J. Lescot, B. Allard
This paper describes a tool for full-chip static ESD (ElectroStatic Discharge) verification called ESD IP Explorer. The tool feasibility is first demonstrated on a 64-pin custom R&D testchip. Its scalability is tested in a second example involving a 138mm2 3,066-bump prototype, which basic verification is performed in less than 8 hours. Both examples are in 28nm UTBB (Ultra-thin-body and BOX - Buried Oxide) FD-SOI High-K metal gate technology. More advanced static verification features are finally discussed.
本文介绍了一种全芯片静电放电(ESD)验证工具——ESD IP Explorer。该工具的可行性首先在64引脚定制研发测试芯片上进行了验证。其可扩展性在第二个示例中进行了测试，该示例涉及138mm2 3,066个凸起原型，其基本验证在不到8小时的时间内完成。这两个例子都采用了28nm UTBB(超薄体和BOX -埋氧化物)FD-SOI高k金属栅极技术。最后讨论了更高级的静态验证特性。
{"title":"An automated tool for chip-scale ESD network exploration and verification","authors":"Benjamin Viale, M. Fer, L. Courau, P. Galy, B. Jacquier, J. Lescot, B. Allard","doi":"10.1109/EOSESD.2016.7592551","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592551","url":null,"abstract":"This paper describes a tool for full-chip static ESD (ElectroStatic Discharge) verification called ESD IP Explorer. The tool feasibility is first demonstrated on a 64-pin custom R&D testchip. Its scalability is tested in a second example involving a 138mm2 3,066-bump prototype, which basic verification is performed in less than 8 hours. Both examples are in 28nm UTBB (Ultra-thin-body and BOX - Buried Oxide) FD-SOI High-K metal gate technology. More advanced static verification features are finally discussed.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"1 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121008845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592554
K. Fukasaku, Daisuke Nakagawa, Toshihiko Miyazaki, T. Tatsumi, H. Ohnuma
Our new ESD design methodology use gate work function control and channel length optimization. We developed a P/N hybrid gate NMOS, where P gate in the channel region reduces subthreshold leakage current thanks to a higher Vth, and N gate in the overlap region reduces GIDL thanks to a lower electric field.
{"title":"Ultra-low standby current ESD clamp MOSFET with P/N hybrid gate","authors":"K. Fukasaku, Daisuke Nakagawa, Toshihiko Miyazaki, T. Tatsumi, H. Ohnuma","doi":"10.1109/EOSESD.2016.7592554","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592554","url":null,"abstract":"Our new ESD design methodology use gate work function control and channel length optimization. We developed a P/N hybrid gate NMOS, where P gate in the channel region reduces subthreshold leakage current thanks to a higher Vth, and N gate in the overlap region reduces GIDL thanks to a lower electric field.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125979488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592559
P. Tamminen, T. Viheriakoski
A charged electronic system failed while it was connected to a USB port. The resulting discharge current waveform had a sub-nanosecond initial peak that bypassed on-board protection devices. In this study the ESD stress waveform is analyzed with simulation and measurement methods.
{"title":"Charged cable—system ESD event","authors":"P. Tamminen, T. Viheriakoski","doi":"10.1109/EOSESD.2016.7592559","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592559","url":null,"abstract":"A charged electronic system failed while it was connected to a USB port. The resulting discharge current waveform had a sub-nanosecond initial peak that bypassed on-board protection devices. In this study the ESD stress waveform is analyzed with simulation and measurement methods.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122302067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592527
L. Di Biccari, L. Cerati, L. Zullino, A. Andreini
Very fast TLP stresses applied to HV ESD diodes in forward conduction are able to reproduce well known and CDM typical effects as Forward Recovery. In this work a full RLC vf-TLP model is introduced in order to investigate HV ESD diodes electrical and physical behavior using TCAD mixed-mode simulations.
{"title":"HV ESD diodes investigation under vf-TLP stresses: TCAD approach","authors":"L. Di Biccari, L. Cerati, L. Zullino, A. Andreini","doi":"10.1109/EOSESD.2016.7592527","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592527","url":null,"abstract":"Very fast TLP stresses applied to HV ESD diodes in forward conduction are able to reproduce well known and CDM typical effects as Forward Recovery. In this work a full RLC vf-TLP model is introduced in order to investigate HV ESD diodes electrical and physical behavior using TCAD mixed-mode simulations.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122790850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592529
I. Eric, T. Iben
For voltage (V) stress of TMRs, the log of the dielectric breakdown time is found to be linear in (H-γZaV/tB)/(kBT), where H, γ, Z, a, tB and kB are an activation energy, a parameter, charge, tunnel barrier lattice constant and thickness, and Boltzmann constant. T is the ambient plus Joule heating temperature of the tunnel barrier.
{"title":"Dielectric breakdown of TMR sensors and the role of Joule heating","authors":"I. Eric, T. Iben","doi":"10.1109/EOSESD.2016.7592529","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592529","url":null,"abstract":"For voltage (V) stress of TMRs, the log of the dielectric breakdown time is found to be linear in (H-γZaV/t<sub>B</sub>)/(k<sub>B</sub>T), where H, γ, Z, a, t<sub>B</sub> and k<sub>B</sub> are an activation energy, a parameter, charge, tunnel barrier lattice constant and thickness, and Boltzmann constant. T is the ambient plus Joule heating temperature of the tunnel barrier.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"388 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124207166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592558
V. Vashchenko, A. Tazzoli, A. Shibkov
A study of PMOS arrays self-protection capability, related HBM-TLP miscorrelation and HBM passing level windowing effect is presented. Based on experimental results and 2D mixed-mode numerical simulation analysis the physical mechanism of the PMOS self-protection limitation is determined to be a complex two-stage phenomenon. It is initiated by a “weak” isothermal avalanche-injection conductivity modulation followed by electro-thermal spatial current instability in the 1μs time domain due to the positive feedback between thermal carrier generation and local power dissipation. The follow-up measures to improve the PMOS array self-protection capability are discussed and validated.
{"title":"PMOS arrays self-protection capability limitation","authors":"V. Vashchenko, A. Tazzoli, A. Shibkov","doi":"10.1109/EOSESD.2016.7592558","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592558","url":null,"abstract":"A study of PMOS arrays self-protection capability, related HBM-TLP miscorrelation and HBM passing level windowing effect is presented. Based on experimental results and 2D mixed-mode numerical simulation analysis the physical mechanism of the PMOS self-protection limitation is determined to be a complex two-stage phenomenon. It is initiated by a “weak” isothermal avalanche-injection conductivity modulation followed by electro-thermal spatial current instability in the 1μs time domain due to the positive feedback between thermal carrier generation and local power dissipation. The follow-up measures to improve the PMOS array self-protection capability are discussed and validated.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124261773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592541
A. Righter, R. Ashton, B. Carn, M. Johnson, B. Reynolds, T. Smedes, S. Ward, H. Wolf
CDM standard JS-002 is introduced, including the reasons for its development and the technical issues the new standard addresses. JS-002 is compared to the JEDEC JESD22-C101, ESDA and AEC Q100 CDM standards in terms of waveforms and integrated circuit pass/fail levels. JS-002 robustness levels are similar to JEDEC CDM levels.
{"title":"JS-002 module and product CDM result comparison to JEDEC and ESDA CDM methods","authors":"A. Righter, R. Ashton, B. Carn, M. Johnson, B. Reynolds, T. Smedes, S. Ward, H. Wolf","doi":"10.1109/EOSESD.2016.7592541","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592541","url":null,"abstract":"CDM standard JS-002 is introduced, including the reasons for its development and the technical issues the new standard addresses. JS-002 is compared to the JEDEC JESD22-C101, ESDA and AEC Q100 CDM standards in terms of waveforms and integrated circuit pass/fail levels. JS-002 robustness levels are similar to JEDEC CDM levels.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124942605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592539
M. Scholz, R. Ashton, T. Smedes, R. Derikx, M. Dekker, J. Barth
The ESDA working group 5.6 has conducted single site testing to evaluate the repeatability of passfail results when using the setups in the standard practice 5.6 document. A ten times lower standard deviation is obtained in comparison to the 2011 round robin.
{"title":"HMM single site testing: Can we reproduce component failure level with the HMM document?","authors":"M. Scholz, R. Ashton, T. Smedes, R. Derikx, M. Dekker, J. Barth","doi":"10.1109/EOSESD.2016.7592539","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592539","url":null,"abstract":"The ESDA working group 5.6 has conducted single site testing to evaluate the repeatability of passfail results when using the setups in the standard practice 5.6 document. A ten times lower standard deviation is obtained in comparison to the 2011 round robin.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122117346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592532
Steve Lim, L. H. Koh, Muhammad Hamizan Bin Abdul Samad, W. F. Wong, Y. H. Goh
It was found that two vendors' steel toe ESD footwear technical specifications were inaccurate. Two of the three steel toe ESD footwear provided by vendors failed the resistance measurement as per ANSI/ESD STM9.1 and STM97.1. Additional assessment was conducted to determine the durability of the steel toe ESD footwear.
{"title":"Product qualification & degradation of steel toe ESD footwear","authors":"Steve Lim, L. H. Koh, Muhammad Hamizan Bin Abdul Samad, W. F. Wong, Y. H. Goh","doi":"10.1109/EOSESD.2016.7592532","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592532","url":null,"abstract":"It was found that two vendors' steel toe ESD footwear technical specifications were inaccurate. Two of the three steel toe ESD footwear provided by vendors failed the resistance measurement as per ANSI/ESD STM9.1 and STM97.1. Additional assessment was conducted to determine the durability of the steel toe ESD footwear.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127258487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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