Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592534
S. Maeda, Masanori Tanaka, Yoko Otsuka, Akinobu Watanabe, Masayuki Tsukuda, Y. Morishita
We propose new ESD design concept using power clamps distributed outside I/O cell ring, which enables the reduction of chip area by the removal of dead space in the chip core area with no degradation of ESD robustness. Our effective design was demonstrated with 40nm MCU test-chip.
{"title":"Area-efficient ESD design using power clamps distributed outside I/O cell ring","authors":"S. Maeda, Masanori Tanaka, Yoko Otsuka, Akinobu Watanabe, Masayuki Tsukuda, Y. Morishita","doi":"10.1109/EOSESD.2016.7592534","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592534","url":null,"abstract":"We propose new ESD design concept using power clamps distributed outside I/O cell ring, which enables the reduction of chip area by the removal of dead space in the chip core area with no degradation of ESD robustness. Our effective design was demonstrated with 40nm MCU test-chip.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592549
S. Parthasarathy, J. Salcedo, A. Jeffry, R. Gobbi, J. Hajjar
A protection circuit for larger than 80 V operation and bidirectional blocking capability is introduced. This circuit achieves a required 8,000 V HBM robustness level, a holding voltage larger than 80 V, a reverse blocking voltage higher than -20 V and 18 dBm Direct RF Power Injection (DPI) immunity between 5- to 500-MHz.
介绍了一种工作电压大于80v且具有双向阻断能力的保护电路。该电路达到了所需的8,000 V HBM稳健性水平，保持电压大于80 V，反向阻断电压高于-20 V，直接射频功率注入(DPI)抗扰度为18 dBm，范围为5至500 mhz。
{"title":"Design of ESD protection for fault tolerant interface applications with EMC immunity","authors":"S. Parthasarathy, J. Salcedo, A. Jeffry, R. Gobbi, J. Hajjar","doi":"10.1109/EOSESD.2016.7592549","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592549","url":null,"abstract":"A protection circuit for larger than 80 V operation and bidirectional blocking capability is introduced. This circuit achieves a required 8,000 V HBM robustness level, a holding voltage larger than 80 V, a reverse blocking voltage higher than -20 V and 18 dBm Direct RF Power Injection (DPI) immunity between 5- to 500-MHz.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123435548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592545
K. K. Ng, K. Yan, R. Gaertner, Stefan Seidl
An investigation was carried out on the charging voltage of deionized (DI) water during wafer cleaning at wafer sawing process, since it was supposed to be the root cause for EOS damages during semiconductor production. The charging voltage was measured using a non-contact electrostatic field meter. It was found that the positioning of the water filter influenced the amount of charging voltage of DI water.
{"title":"Influence of machine configuration on EOS damage during wafer cleaning process","authors":"K. K. Ng, K. Yan, R. Gaertner, Stefan Seidl","doi":"10.1109/EOSESD.2016.7592545","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592545","url":null,"abstract":"An investigation was carried out on the charging voltage of deionized (DI) water during wafer cleaning at wafer sawing process, since it was supposed to be the root cause for EOS damages during semiconductor production. The charging voltage was measured using a non-contact electrostatic field meter. It was found that the positioning of the water filter influenced the amount of charging voltage of DI water.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123280520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592544
J. Salisbury, V. Kraz
Excessive ground currents expose sensitive devices to electrical overstress (EOS) in a hot bar soldering process. This paper examines the process, current and voltage exposure to the devices as well as describes mitigation methods to reduce this current, which are applicable to many processes in semiconductor manufacturing and PCB assembly.
{"title":"Reducing EOS current in hot bar process in manufacturing of fiber optics components","authors":"J. Salisbury, V. Kraz","doi":"10.1109/EOSESD.2016.7592544","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592544","url":null,"abstract":"Excessive ground currents expose sensitive devices to electrical overstress (EOS) in a hot bar soldering process. This paper examines the process, current and voltage exposure to the devices as well as describes mitigation methods to reduce this current, which are applicable to many processes in semiconductor manufacturing and PCB assembly.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130601736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592547
Krishna Rajagopal, A. Appaswamy, M. Dissegna, A. Concannon, Lihui Wang, A. Gallerano
SOA (safe operating area) at subthreshold gate voltages are typically not of interest during normal operation. Under ESD conditions, however, the device could be biased in the subthreshold regime. In this paper we discuss the impact of subthreshold gate voltages on the SOA boundary of LDMOS devices and its implications to ESD design.
{"title":"Impact of sub-threshold SOA on ESD protection schemes","authors":"Krishna Rajagopal, A. Appaswamy, M. Dissegna, A. Concannon, Lihui Wang, A. Gallerano","doi":"10.1109/EOSESD.2016.7592547","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592547","url":null,"abstract":"SOA (safe operating area) at subthreshold gate voltages are typically not of interest during normal operation. Under ESD conditions, however, the device could be biased in the subthreshold regime. In this paper we discuss the impact of subthreshold gate voltages on the SOA boundary of LDMOS devices and its implications to ESD design.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134046166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592533
T. Viheriakoski, Eira Karja, J. Hillberg, P. Tamminen
Charge relaxation times of solid planar polymers were assessed with different charging methods in a controlled environment. Electrically isolated samples had relatively long relaxation periods. The longest measurement sequence was 62 hours. An electrostatic behavior of the samples under test was then characterized in a changing electrostatic field.
{"title":"Charge relaxation of slowly dissipative polymers","authors":"T. Viheriakoski, Eira Karja, J. Hillberg, P. Tamminen","doi":"10.1109/EOSESD.2016.7592533","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592533","url":null,"abstract":"Charge relaxation times of solid planar polymers were assessed with different charging methods in a controlled environment. Electrically isolated samples had relatively long relaxation periods. The longest measurement sequence was 62 hours. An electrostatic behavior of the samples under test was then characterized in a changing electrostatic field.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"34 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131171149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592556
V. Vendt, J. Willemen, K. Reiser, D. Schmitt-Landsiedel
Pnpn-structures show a sudden increase in on-state clamping voltage due to insufficient gain product of their internal BJTs at high current densities. This can be described with bipolar theory and high-current effects. High-current IV characteristics confirm a gain product decrease and critical current densities are extracted from two terminal pnpn-structures.
{"title":"Gain-product in pnpn-structures at high current densities and the impact on the IV-characteristic","authors":"V. Vendt, J. Willemen, K. Reiser, D. Schmitt-Landsiedel","doi":"10.1109/EOSESD.2016.7592556","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592556","url":null,"abstract":"Pnpn-structures show a sudden increase in on-state clamping voltage due to insufficient gain product of their internal BJTs at high current densities. This can be described with bipolar theory and high-current effects. High-current IV characteristics confirm a gain product decrease and critical current densities are extracted from two terminal pnpn-structures.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114784227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592531
J. Thurmer, J. Smallwood
Electrostatic shocks were reported by personnel manufacturing large fiber reinforced plastic wind turbine blades. Inspection and measurements confirmed these reports. We have estimated the possible discharge energy and likelihood of hazardous ESD in some production steps. Administrative and technical recommendations are given to control static to an acceptable level.
{"title":"Electrostatic shock risks in assembly of large wind turbine blades","authors":"J. Thurmer, J. Smallwood","doi":"10.1109/EOSESD.2016.7592531","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592531","url":null,"abstract":"Electrostatic shocks were reported by personnel manufacturing large fiber reinforced plastic wind turbine blades. Inspection and measurements confirmed these reports. We have estimated the possible discharge energy and likelihood of hazardous ESD in some production steps. Administrative and technical recommendations are given to control static to an acceptable level.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121817686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592542
Friedrich zur Nieden, K. Esmark, Stefan Seidl, R. Gartner
The introduction of the CDM Joint Standard has an impact on the electrical properties of the tester hardware due to updated waveform requirements. Models of different CDM discharge heads are generated using measurement data in frequency domain. Discharge currents of a device are simulated according to the different standards in time domain. In comparison to the popular but replaced JEDEC standard peak current levels have increased.
{"title":"Predict the product specific CDM stress using measurement-based models of CDM discharge heads","authors":"Friedrich zur Nieden, K. Esmark, Stefan Seidl, R. Gartner","doi":"10.1109/EOSESD.2016.7592542","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592542","url":null,"abstract":"The introduction of the CDM Joint Standard has an impact on the electrical properties of the tester hardware due to updated waveform requirements. Models of different CDM discharge heads are generated using measurement data in frequency domain. Discharge currents of a device are simulated according to the different standards in time domain. In comparison to the popular but replaced JEDEC standard peak current levels have increased.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123421685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/EOSESD.2016.7592526
Da-Wei Lai, S. Zhao, Jian Gao, T. Smedes
A novel ESD device (PNP with embedded SCR), with tunable VT1 and VH, is proposed for high voltage applications. Tuning is achieved through design and process options. The trigger mechanism is determined by the series connection of PNP(s) and diode. The holding voltage is determined by the eSCR and additional PNP(s).
{"title":"PNP-eSCR ESD protection device with tunable trigger and holding voltage for high voltage applications","authors":"Da-Wei Lai, S. Zhao, Jian Gao, T. Smedes","doi":"10.1109/EOSESD.2016.7592526","DOIUrl":"https://doi.org/10.1109/EOSESD.2016.7592526","url":null,"abstract":"A novel ESD device (PNP with embedded SCR), with tunable VT1 and VH, is proposed for high voltage applications. Tuning is achieved through design and process options. The trigger mechanism is determined by the series connection of PNP(s) and diode. The holding voltage is determined by the eSCR and additional PNP(s).","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127529728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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