Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090318
Ze-kun Zhou, Zhijian Zhang, Lichen Peng
A sub-nanosecond-delay level shifter with an above 75V/ns power supply slew tolerance is proposed in this paper. In this design, two speed-up branches are adapted to realize a sub-ns delay and high CMTI immunity circuit is proposed to ensure high dv/dt tolerance. Besides, with the control of CMTI enhanced logic, speed-up branches are reused to enhance the dv/dt immunity for a better CMTI performance. And this structure can be expended to higher voltage range of application like 80V level shifter to tolerant the large range power supply slew. The proposed level shifter simulated with 0.18µm BCD process shows delay of 700ps and 30V/ns dv/dt immunity in the 35V high voltage application and can tolerant an 75V/ns dv/dt in 80V application.
{"title":"Design of a High Voltage Level Shift with High dV/dt Immunity and High Speed","authors":"Ze-kun Zhou, Zhijian Zhang, Lichen Peng","doi":"10.1109/APCCAS55924.2022.10090318","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090318","url":null,"abstract":"A sub-nanosecond-delay level shifter with an above 75V/ns power supply slew tolerance is proposed in this paper. In this design, two speed-up branches are adapted to realize a sub-ns delay and high CMTI immunity circuit is proposed to ensure high dv/dt tolerance. Besides, with the control of CMTI enhanced logic, speed-up branches are reused to enhance the dv/dt immunity for a better CMTI performance. And this structure can be expended to higher voltage range of application like 80V level shifter to tolerant the large range power supply slew. The proposed level shifter simulated with 0.18µm BCD process shows delay of 700ps and 30V/ns dv/dt immunity in the 35V high voltage application and can tolerant an 75V/ns dv/dt in 80V application.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130113749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090402
Woobean Lee, Pangi Park, Seonghwan Cho
This paper presents correlated double sampling least mean squares (CDS-LMS) filter to reduce the motion artifacts of the PPG signal. By using red and green PPG signals as the inputs of the LMS filter, the motion artifacts with the same frequency component as PPG signals can be removed without losing information in PPG. Also, CDS is employed before the LMS filter to remove the effect of ambient light offset. With the proposed CDS-LMS filter, the RMS error in heart-beat interval is reduced by 86.49%, 87.54%, and 89.09% compared to a conventional bandpass filter when the PPG signal is measured during squatting, walking, and running. The mean absolute error in heart rate is 2.59 beats per minute while running.
{"title":"Reduction of Motion Artifact in PPG signal with CDS-LMS Filter","authors":"Woobean Lee, Pangi Park, Seonghwan Cho","doi":"10.1109/APCCAS55924.2022.10090402","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090402","url":null,"abstract":"This paper presents correlated double sampling least mean squares (CDS-LMS) filter to reduce the motion artifacts of the PPG signal. By using red and green PPG signals as the inputs of the LMS filter, the motion artifacts with the same frequency component as PPG signals can be removed without losing information in PPG. Also, CDS is employed before the LMS filter to remove the effect of ambient light offset. With the proposed CDS-LMS filter, the RMS error in heart-beat interval is reduced by 86.49%, 87.54%, and 89.09% compared to a conventional bandpass filter when the PPG signal is measured during squatting, walking, and running. The mean absolute error in heart rate is 2.59 beats per minute while running.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130179757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090355
C. Tseng, Su-Ling Lee
In this paper, an eigen-decomposition free method is presented to compute the graph Fourier transform centrality (GFTC) of complex network. For conventional computation method of GFTC, it needs to compute eigen-decomposition of graph Laplacian matrix for obtaining the transform basis of graph Fourier transform (GFT), which may not be computable for larger networks. To tackle this problem, the graph filtering method is applied to transform the spectral-domain GFTC computation task to vertex-domain one such that GFTC can be computed by using graph filter which is easily designed by the least squares (LS) method. Finally, the centrality computations of the Taipei metro network and karate-club social network are used to show the effectiveness of the proposed GFTC computation method.
{"title":"An Eigen-decomposition Free Method for Computing Graph Fourier Transform Centrality","authors":"C. Tseng, Su-Ling Lee","doi":"10.1109/APCCAS55924.2022.10090355","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090355","url":null,"abstract":"In this paper, an eigen-decomposition free method is presented to compute the graph Fourier transform centrality (GFTC) of complex network. For conventional computation method of GFTC, it needs to compute eigen-decomposition of graph Laplacian matrix for obtaining the transform basis of graph Fourier transform (GFT), which may not be computable for larger networks. To tackle this problem, the graph filtering method is applied to transform the spectral-domain GFTC computation task to vertex-domain one such that GFTC can be computed by using graph filter which is easily designed by the least squares (LS) method. Finally, the centrality computations of the Taipei metro network and karate-club social network are used to show the effectiveness of the proposed GFTC computation method.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114077819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090403
Jing Ma, Yanjin Lyu, Yuanqi Hu
The inaccuracy of residue amplification has become the major bottleneck when it comes to design pipelined analogue-to-digital converters (ADCs). High-gain and high-speed operational amplifiers (Op-Amps) usually consume too much power for a decent ADC. Therefore, we proposed a foreground calibration technique, which can correct amplification errors in cyclic-pipelined ADCs and consequently alleviate the DC gain requirement for internal amplifiers. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 5-bit sub-ADC four times, and each time 1-bit redundancy is exploited to suppress the errors due to sub-ADCs. Actual gain of each amplification can be feasibly calculated by the Fix-Point Iteration algorithm. Simulation results show the signal-to-noise-and-distortion-ratio (SINAD) to be 100.6 dB even with a 57dB-DC-Gain amplifier. The total power consumption of ADC is 30.43 mW and it occupies an active area of 1.8 mm square.
{"title":"A 16-Bit 2 MS/s Cyclic-pipelined ADC with Calibration for Inter-stage Amplification","authors":"Jing Ma, Yanjin Lyu, Yuanqi Hu","doi":"10.1109/APCCAS55924.2022.10090403","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090403","url":null,"abstract":"The inaccuracy of residue amplification has become the major bottleneck when it comes to design pipelined analogue-to-digital converters (ADCs). High-gain and high-speed operational amplifiers (Op-Amps) usually consume too much power for a decent ADC. Therefore, we proposed a foreground calibration technique, which can correct amplification errors in cyclic-pipelined ADCs and consequently alleviate the DC gain requirement for internal amplifiers. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 5-bit sub-ADC four times, and each time 1-bit redundancy is exploited to suppress the errors due to sub-ADCs. Actual gain of each amplification can be feasibly calculated by the Fix-Point Iteration algorithm. Simulation results show the signal-to-noise-and-distortion-ratio (SINAD) to be 100.6 dB even with a 57dB-DC-Gain amplifier. The total power consumption of ADC is 30.43 mW and it occupies an active area of 1.8 mm square.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114844733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090278
Mengli Zou, Xinzi Xu, Qiao Cai, Yanxing Suo, T. Wan, Jian Zhao, Yang Zhao
The extracted energy of the thermal energy harvester circuits are affected by the input and output power status. A boost and buck reconfigurable harvester circuits with store, supply, extract and recycle modes are proposed in this paper to harvest the power from TEG at any possible chances. In addition, maximum power point tracking and zero current switching are also customized for the reconfigurability. Moreover, Colpitts oscillator and Dickson charge pump based startup circuit are adopted for millivolts startup. Simulation shows that the proposed design shows end-to-end conversion efficiency of 86% in conventional boost configuration as well as 75.3% in buck configuration with minimum startup voltage of 7mV. In extract mode, up to 27% total power can be harvested from TEG even configured as buck converter.
{"title":"Store, Supply, Extract and Recycle: A Boost/Buck Reconfigurable Converter for Thermal Energy Harvesting","authors":"Mengli Zou, Xinzi Xu, Qiao Cai, Yanxing Suo, T. Wan, Jian Zhao, Yang Zhao","doi":"10.1109/APCCAS55924.2022.10090278","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090278","url":null,"abstract":"The extracted energy of the thermal energy harvester circuits are affected by the input and output power status. A boost and buck reconfigurable harvester circuits with store, supply, extract and recycle modes are proposed in this paper to harvest the power from TEG at any possible chances. In addition, maximum power point tracking and zero current switching are also customized for the reconfigurability. Moreover, Colpitts oscillator and Dickson charge pump based startup circuit are adopted for millivolts startup. Simulation shows that the proposed design shows end-to-end conversion efficiency of 86% in conventional boost configuration as well as 75.3% in buck configuration with minimum startup voltage of 7mV. In extract mode, up to 27% total power can be harvested from TEG even configured as buck converter.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090352
Yajun Lin, Haozheng Wan, Jianxin Yang, K. Leung
An ultra-low-supply output-capacitorless (OCL) low-dropout regulator is presented in this paper. The circuit is based on flipped-voltage-follower-based (FVF-based) LDO with a signal-current enhancer (SCE) and a direct voltage-spike detection part. To enable the LDO to function properly under an ultra-low supply voltage, an additional charge-pump circuit provides a higher supply to the control part of LDO to enlarge the control swing of power transistor. The proposed LDO regulator is designed in UMC 65-nm CMOS process. The threshold voltages of NMOSFET and PMOSFET are 0.374 V and −0.311 V, respectively. The achieved minimum supply voltage is 0.6 V, with output voltage of 0.5 V. The load current ranges between 100 μA and 50 mA. The figure-of-merit of proposed circuit is 0.43 ps.
{"title":"An Ultra-Low-Supply Output-Capacitorless LDO with Signal- and Transient-Enhancement","authors":"Yajun Lin, Haozheng Wan, Jianxin Yang, K. Leung","doi":"10.1109/APCCAS55924.2022.10090352","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090352","url":null,"abstract":"An ultra-low-supply output-capacitorless (OCL) low-dropout regulator is presented in this paper. The circuit is based on flipped-voltage-follower-based (FVF-based) LDO with a signal-current enhancer (SCE) and a direct voltage-spike detection part. To enable the LDO to function properly under an ultra-low supply voltage, an additional charge-pump circuit provides a higher supply to the control part of LDO to enlarge the control swing of power transistor. The proposed LDO regulator is designed in UMC 65-nm CMOS process. The threshold voltages of NMOSFET and PMOSFET are 0.374 V and −0.311 V, respectively. The achieved minimum supply voltage is 0.6 V, with output voltage of 0.5 V. The load current ranges between 100 μA and 50 mA. The figure-of-merit of proposed circuit is 0.43 ps.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"54 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134064448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090326
D. Kang, Shimeng Yu
The cryogenic silicon complementary-metal-oxide-semiconductor (CMOS) technology and its application in tensor processing unit (TPU) design are explored. Using the 22 nm fully-depleted-silicon-on-insulator (FDSOI) transistor model that was calibrated at 70 K, this study provides insights into the design/technological knobs to achieve a superior performance at cryogenic temperature (cryo-TPU) by exploiting threshold voltage (Vth) engineering, gain-cell embedded DRAM (GC-eDRAM) and true-single phase clock (TSPC) D flip-flop. Benchmark shows that cryo-TPU using GC-eDRAM based global buffer and TSPC D flip-flop based register surpasses conventional TPU architecture operating at the room temperature: over 33% chip area reduction in iso-power condition, over 94% power reduction in iso-area condition and over 40% power reduction even when the refrigerator cooling power is included.
{"title":"Design-Technology Co-optimization for Cryogenic Tensor Processing Unit","authors":"D. Kang, Shimeng Yu","doi":"10.1109/APCCAS55924.2022.10090326","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090326","url":null,"abstract":"The cryogenic silicon complementary-metal-oxide-semiconductor (CMOS) technology and its application in tensor processing unit (TPU) design are explored. Using the 22 nm fully-depleted-silicon-on-insulator (FDSOI) transistor model that was calibrated at 70 K, this study provides insights into the design/technological knobs to achieve a superior performance at cryogenic temperature (cryo-TPU) by exploiting threshold voltage (Vth) engineering, gain-cell embedded DRAM (GC-eDRAM) and true-single phase clock (TSPC) D flip-flop. Benchmark shows that cryo-TPU using GC-eDRAM based global buffer and TSPC D flip-flop based register surpasses conventional TPU architecture operating at the room temperature: over 33% chip area reduction in iso-power condition, over 94% power reduction in iso-area condition and over 40% power reduction even when the refrigerator cooling power is included.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134263390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090364
Yuxin Lin, Wenye Liu, Chip-Hong Chang
Traditional face recognition systems use RGB images as input for feature extraction and classification. However, conventional methods based on color images experience non-trivial accuracy drop under several challenging conditions like occlusion, pose variation and facial expression changes. With the gradually decreasing cost of smart sensors, RGB-Depth(D) images captured using low-cost sensors are used to provide complementary features to RGB images. Both the extracted Local Binary Pattern (LBP) features and depth map contain additional discriminative information that can guide the face recognition model to focus on the important parts of the input image. In this paper, we propose a novel end-to-end network that combines both texture and depth features for automatic attention-based face recognition. The experiment results demonstrate that the proposed method has improved recognition accuracy under diverse variations. Our proposed face recognition model has been implemented on the NVIDIA Jetson Nano device to evaluate its performance with compact feature extractors used on different branches of the model. The results show that our method can improve the FPS of face recognition on an edge-coming device from 1.6 to 3.8 with <1% accuracy degradation.
{"title":"Deep Texture-Depth-Based Attention for Face Recognition on IoT Devices","authors":"Yuxin Lin, Wenye Liu, Chip-Hong Chang","doi":"10.1109/APCCAS55924.2022.10090364","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090364","url":null,"abstract":"Traditional face recognition systems use RGB images as input for feature extraction and classification. However, conventional methods based on color images experience non-trivial accuracy drop under several challenging conditions like occlusion, pose variation and facial expression changes. With the gradually decreasing cost of smart sensors, RGB-Depth(D) images captured using low-cost sensors are used to provide complementary features to RGB images. Both the extracted Local Binary Pattern (LBP) features and depth map contain additional discriminative information that can guide the face recognition model to focus on the important parts of the input image. In this paper, we propose a novel end-to-end network that combines both texture and depth features for automatic attention-based face recognition. The experiment results demonstrate that the proposed method has improved recognition accuracy under diverse variations. Our proposed face recognition model has been implemented on the NVIDIA Jetson Nano device to evaluate its performance with compact feature extractors used on different branches of the model. The results show that our method can improve the FPS of face recognition on an edge-coming device from 1.6 to 3.8 with <1% accuracy degradation.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124778170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-11DOI: 10.1109/APCCAS55924.2022.10090314
Sae Goto, Minoru Watanabe, Nobuya Watanabe
Very large scale integrations (VLSIs) used in high radiation environments such as outer space and nuclear power plants are constantly affected by radiation. Since VLSIs are vulnerable to radiation, existing VLSIs have an inherent difficulty that temporary or permanent failures occur in high-radiation environments. In order to improve the radiation tolerance of current VLSIs, optically reconfigurable gate arrays consisting of a holographic memory, a laser array, and a programmable gate array VLSI using a standard CMOS process technology have been being developed. The radiation tolerance of the optically reconfigurable gate array has drastically been improved by exploiting its programmable capability based on a configuration function strong for radiation. However, the configuration circuit still includes common signals that decrease the radiation tolerance. This paper present a proposal of a new optically reconfigurable gate array VLSI that perfectly removes the common signals and its experimental results obtained from testing it.
{"title":"Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration","authors":"Sae Goto, Minoru Watanabe, Nobuya Watanabe","doi":"10.1109/APCCAS55924.2022.10090314","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090314","url":null,"abstract":"Very large scale integrations (VLSIs) used in high radiation environments such as outer space and nuclear power plants are constantly affected by radiation. Since VLSIs are vulnerable to radiation, existing VLSIs have an inherent difficulty that temporary or permanent failures occur in high-radiation environments. In order to improve the radiation tolerance of current VLSIs, optically reconfigurable gate arrays consisting of a holographic memory, a laser array, and a programmable gate array VLSI using a standard CMOS process technology have been being developed. The radiation tolerance of the optically reconfigurable gate array has drastically been improved by exploiting its programmable capability based on a configuration function strong for radiation. However, the configuration circuit still includes common signals that decrease the radiation tolerance. This paper present a proposal of a new optically reconfigurable gate array VLSI that perfectly removes the common signals and its experimental results obtained from testing it.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126160226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 28 nm 0.7-6 GHz programable push-pull driver power amplifier (DPA) based on dual-loop biases for Sub-6 GHz band is presented. Based on the dual-loop biases, the DPA can dynamically adjust two gate biases to ensure low output HD2 and HD3, in addition the DPA is robust over process, voltage, and temperature (PVT) variations. The DPA achieves wideband frequency coverage with off-chip matching network. The DPA consists of thermometer-weight transconductors and binary-weighted transconductors. The transmitter prototype with the DPA achieves 32 dB dynamic gain range, 0.5 dB accuracy in 1 dB step over the Sub-6 GHz band. Fabricated in 28 nm CMOS technology, the DPA shows 30.5 dBm OIP3 while consuming 62 mA from 1.8 V power supply for high gain setting.
{"title":"0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop Biases","authors":"Minghao Jiang, Chenyang Han, Weibo Li, Jiangfeng Wu, Yongzhen Chen","doi":"10.1109/APCCAS55924.2022.10090259","DOIUrl":"https://doi.org/10.1109/APCCAS55924.2022.10090259","url":null,"abstract":"A 28 nm 0.7-6 GHz programable push-pull driver power amplifier (DPA) based on dual-loop biases for Sub-6 GHz band is presented. Based on the dual-loop biases, the DPA can dynamically adjust two gate biases to ensure low output HD2 and HD3, in addition the DPA is robust over process, voltage, and temperature (PVT) variations. The DPA achieves wideband frequency coverage with off-chip matching network. The DPA consists of thermometer-weight transconductors and binary-weighted transconductors. The transmitter prototype with the DPA achieves 32 dB dynamic gain range, 0.5 dB accuracy in 1 dB step over the Sub-6 GHz band. Fabricated in 28 nm CMOS technology, the DPA shows 30.5 dBm OIP3 while consuming 62 mA from 1.8 V power supply for high gain setting.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130257746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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