Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313837
Arwa Ben Dhia, L. Naviner, Philippe Matherat
This paper proposes a method to analyze the effect of manufacturing defects and soft errors: stuck-ats and bit flips, on a cluster in a Mesh FPGA architecture. The cluster reliability is evaluated with a technique that is used in case of either a single error or multiple simultaneous faults. Simulation results show that the cluster is more robust to stuck-ats than to bit-flips, whatever the configuration memory is. Then, for selective hardening against bit flips, we propose an approach to identify the critical path and the most eligible component that is likely to improve the cluster reliability.
{"title":"Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster","authors":"Arwa Ben Dhia, L. Naviner, Philippe Matherat","doi":"10.1109/IOLTS.2012.6313837","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313837","url":null,"abstract":"This paper proposes a method to analyze the effect of manufacturing defects and soft errors: stuck-ats and bit flips, on a cluster in a Mesh FPGA architecture. The cluster reliability is evaluated with a technique that is used in case of either a single error or multiple simultaneous faults. Simulation results show that the cluster is more robust to stuck-ats than to bit-flips, whatever the configuration memory is. Then, for selective hardening against bit flips, we propose an approach to identify the critical path and the most eligible component that is likely to improve the cluster reliability.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128204540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313834
Mohammed Shayan, Virendra Singh, A. Singh, M. Fujita
The implementation of semiconductor circuits and systems in nano-technology makes it possible to achieve high speed, lower voltage level and smaller area. The unintended and undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by alpha particle or neutron hits. These events of radiation strike resulting into bit upsets referred to as single event upsets(SEU), become increasingly of concern for the reliable circuit operation in the field. Storage elements are worst hit by this phenomenon. As we further scale down, there is greater interest in reliability of the circuits and systems, apart from the performance, power and area aspects. In this paper we propose an improved 12T SEU tolerant SRAM cell design. The proposed SRAM cell is economical in terms of area overhead. It is easy to fabricate as compared to earlier designs. Simulation results show that the proposed cell is highly robust, as it does not flip even for a transient pulse with 62 times the Qcrit of a standard 6T SRAM cell.
{"title":"SEU tolerant robust memory cell design","authors":"Mohammed Shayan, Virendra Singh, A. Singh, M. Fujita","doi":"10.1109/IOLTS.2012.6313834","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313834","url":null,"abstract":"The implementation of semiconductor circuits and systems in nano-technology makes it possible to achieve high speed, lower voltage level and smaller area. The unintended and undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by alpha particle or neutron hits. These events of radiation strike resulting into bit upsets referred to as single event upsets(SEU), become increasingly of concern for the reliable circuit operation in the field. Storage elements are worst hit by this phenomenon. As we further scale down, there is greater interest in reliability of the circuits and systems, apart from the performance, power and area aspects. In this paper we propose an improved 12T SEU tolerant SRAM cell design. The proposed SRAM cell is economical in terms of area overhead. It is easy to fabricate as compared to earlier designs. Simulation results show that the proposed cell is highly robust, as it does not flip even for a transient pulse with 62 times the Qcrit of a standard 6T SRAM cell.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128486877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313859
S. Yoshimoto, T. Amashita, Masayoshi Yoshimura, Y. Matsunaga, H. Yasuura, S. Izumi, H. Kawaguchi, M. Yoshimoto
This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.
{"title":"Neutron-induced soft error rate estimation for SRAM using PHITS","authors":"S. Yoshimoto, T. Amashita, Masayoshi Yoshimura, Y. Matsunaga, H. Yasuura, S. Izumi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/IOLTS.2012.6313859","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313859","url":null,"abstract":"This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128953934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313833
Yang Lin, Mark Zwolinski
Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. SETTOFF therefore provides an increased coverage of fault tolerance with only moderate increase in overhead, hence it is suitable for building highly reliable systems at lower cost than the traditional techniques.
{"title":"SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems","authors":"Yang Lin, Mark Zwolinski","doi":"10.1109/IOLTS.2012.6313833","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313833","url":null,"abstract":"Conventional fault tolerance techniques either require big overheads or have limited reliability. We propose a novel fault tolerant flip-flop (SETTOFF) that addresses timing errors and soft errors in one cost-efficient architecture. In SETTOFF, most SEUs are detected by monitoring the illegal transitions at the output of a flip-flop and recovered by inverting the cell state. SETs, timing errors and the other SEUs are detected by a time redundancy-based architecture. For a 10% activity rate, SETTOFF consumes 35.8% and 39.7% more power than a library flip-flop in 120nm and 65nm technologies, respectively. It only consumes about 5.7% more power than the detection based RazorII flip-flop [1]. SETTOFF therefore provides an increased coverage of fault tolerance with only moderate increase in overhead, hence it is suitable for building highly reliable systems at lower cost than the traditional techniques.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127071462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313863
Yaara Neumeier, O. Keren
Robust and partially robust codes are codes used in cryptographic devices for maximizing the probability of detecting errors injected by malicious attackers. The set of errors that are masked (undetected) by all codewords form the detection-kernel of the code. Codes whose kernel contains only the zero vector, i.e. codes that can detect any nonzero error (of any multiplicity) with probability greater than zero, are called robust. Codes whose kernel is of size greater than one are considered as partially-robust codes. Partially-robust codes of rate greater than one-half can be derived from the the cubic Karpovsky-Taubin code [6]. This paper introduces a construction of robust codes of rate >; 1/2. The codes are derived from the Karpovsky-Taubin code by puncturing the redundancy bits. It is shown that if the number of remaining redundancy bits (r) is greater than one then the code is robust and any error vector is detected with probability 1, 1-2-r or 1 - 2-r+1. The number of the error vectors associated with each probability is given for robust codes having odd number of information bits.
{"title":"Punctured Karpovsky-Taubin binary robust error detecting codes for cryptographic devices","authors":"Yaara Neumeier, O. Keren","doi":"10.1109/IOLTS.2012.6313863","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313863","url":null,"abstract":"Robust and partially robust codes are codes used in cryptographic devices for maximizing the probability of detecting errors injected by malicious attackers. The set of errors that are masked (undetected) by all codewords form the detection-kernel of the code. Codes whose kernel contains only the zero vector, i.e. codes that can detect any nonzero error (of any multiplicity) with probability greater than zero, are called robust. Codes whose kernel is of size greater than one are considered as partially-robust codes. Partially-robust codes of rate greater than one-half can be derived from the the cubic Karpovsky-Taubin code [6]. This paper introduces a construction of robust codes of rate >; 1/2. The codes are derived from the Karpovsky-Taubin code by puncturing the redundancy bits. It is shown that if the number of remaining redundancy bits (r) is greater than one then the code is robust and any error vector is detected with probability 1, 1-2-r or 1 - 2-r+1. The number of the error vectors associated with each probability is given for robust codes having odd number of information bits.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125244794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313835
S. Pandey, Klaas Brink
This paper is about a single event upset resilient logic design optimization technique for sub-100nm technology nodes. The proposed technique can be used for both combinational as well as sequential circuits. In order to make a logic circuit robust for a transient error, the well known gate sizing technique is used. A 65nm inverters based master slave flip flop is considered for the case study. The result shows a trade off between the robustness and the performance (power consumption and operational speed) while performing design optimization for a single event upset. Furthermore, it shows that the width of devices cannot be increased arbitrarily in order to make a flip flop resilient since it can result in timing violation. The proposed design optimization technique incorporates the timing aspects and finds the optimal widths that make a gate robust against a single event upset.
{"title":"Soft-errors resilient logic optimization for low power","authors":"S. Pandey, Klaas Brink","doi":"10.1109/IOLTS.2012.6313835","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313835","url":null,"abstract":"This paper is about a single event upset resilient logic design optimization technique for sub-100nm technology nodes. The proposed technique can be used for both combinational as well as sequential circuits. In order to make a logic circuit robust for a transient error, the well known gate sizing technique is used. A 65nm inverters based master slave flip flop is considered for the case study. The result shows a trade off between the robustness and the performance (power consumption and operational speed) while performing design optimization for a single event upset. Furthermore, it shows that the width of devices cannot be increased arbitrarily in order to make a flip flop resilient since it can result in timing violation. The proposed design optimization technique incorporates the timing aspects and finds the optimal widths that make a gate robust against a single event upset.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123831270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313848
O. Sinanoglu
Scalability, power-efficiency and shorter time-to-market due to design re-use have favored the adoption of homogeneous multi-core chips with identical processing units (cores) integrated together, offering enhanced computational power. Furthermore, chips with identical cores help cope with increasing defect rates in delivering reasonable yield levels via the utilization of spare cores. In this paper, we propose a comparison-based TAM that is capable of handling spare identical cores; the proposed TAM guarantees the test of a chip through minimum bandwidth in minimum test time, while ensuring no yield loss in the presence of spare identical cores, as its design is driven by the number of spare cores on the chip. The proposed solution also enables the identification of all the good cores in usable chips, supporting models where chips are priced based on number of good cores. We also extend the proposed TAM by adding efficient diagnostic features.
{"title":"Test access mechanism for chips with spare identical cores","authors":"O. Sinanoglu","doi":"10.1109/IOLTS.2012.6313848","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313848","url":null,"abstract":"Scalability, power-efficiency and shorter time-to-market due to design re-use have favored the adoption of homogeneous multi-core chips with identical processing units (cores) integrated together, offering enhanced computational power. Furthermore, chips with identical cores help cope with increasing defect rates in delivering reasonable yield levels via the utilization of spare cores. In this paper, we propose a comparison-based TAM that is capable of handling spare identical cores; the proposed TAM guarantees the test of a chip through minimum bandwidth in minimum test time, while ensuring no yield loss in the presence of spare identical cores, as its design is driven by the number of spare cores on the chip. The proposed solution also enables the identification of all the good cores in usable chips, supporting models where chips are priced based on number of good cores. We also extend the proposed TAM by adding efficient diagnostic features.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125927069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313865
Rakesh Kumar
Summary form only given. Much recent research suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints have often been referred to as stochastic processors. In this talk, I will discuss three approaches for building applications for such processors. The first approach relies on relaxing the correctness of the application based upon an analysis of application characteristics. The second approach relies upon detecting and then correcting faults within the application as they arise. The third approach transforms applications into more error tolerant forms. In this paper, we show how these techniques that enhance or exploit the error tolerance of applications can yield significant power and energy benefits when computed on stochastic processors.
{"title":"Algorithmic techniques for robust applications","authors":"Rakesh Kumar","doi":"10.1109/IOLTS.2012.6313865","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313865","url":null,"abstract":"Summary form only given. Much recent research suggests significant power and energy benefits of relaxing correctness constraints in future processors. Such processors with relaxed constraints have often been referred to as stochastic processors. In this talk, I will discuss three approaches for building applications for such processors. The first approach relies on relaxing the correctness of the application based upon an analysis of application characteristics. The second approach relies upon detecting and then correcting faults within the application as they arise. The third approach transforms applications into more error tolerant forms. In this paper, we show how these techniques that enhance or exploit the error tolerance of applications can yield significant power and energy benefits when computed on stochastic processors.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123250411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313832
N. Julai, A. Yakovlev, A. Bystrov
Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits. In this paper, our investigations focus on the vulnerability of different latch types based on C-elements with respect to soft errors. Our aim is to design single event upset (SEU) tolerant latch that has the capability of both detecting and correcting soft errors based on converting single rail to dual-rail configuration and Razor flip flop implementation. In the event of an SEU hitting sensitive nodes and causing the state to temporarily change, an error is generated and a shadow latch restores the correct data. We have demonstrated the functionality of our proposed latch by simulating the design using UMC90nm technology. We also measured error rate of our proposed latch by using an Altera Cyclone II FPGA board. We have obtained the voltage dependence of the error rates. The results show that our proposed latch has less than 1.5% faults propagated at the output.
软错误在状态保持电路中是一个严重的问题，因为它们可能导致暂时的故障。c -元件是异步电路中广泛使用的一种状态保持器。本文主要研究了基于c元的不同锁存器类型在软误差方面的脆弱性。我们的目标是设计单事件干扰(SEU)容忍锁存器，该锁存器具有检测和纠正软错误的能力，基于将单轨转换为双轨配置和Razor触发器实现。如果SEU击中敏感节点并导致状态临时改变，则会生成一个错误，影子锁存器将恢复正确的数据。我们通过使用UMC90nm技术模拟设计，展示了我们提出的锁存器的功能。我们还通过使用Altera Cyclone II FPGA板测量了我们提出的锁存器的错误率。我们得到了错误率与电压的关系。结果表明，我们提出的锁存器在输出端传播的故障小于1.5%。
{"title":"Error detection and correction of single event upset (SEU) tolerant latch","authors":"N. Julai, A. Yakovlev, A. Bystrov","doi":"10.1109/IOLTS.2012.6313832","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313832","url":null,"abstract":"Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits. In this paper, our investigations focus on the vulnerability of different latch types based on C-elements with respect to soft errors. Our aim is to design single event upset (SEU) tolerant latch that has the capability of both detecting and correcting soft errors based on converting single rail to dual-rail configuration and Razor flip flop implementation. In the event of an SEU hitting sensitive nodes and causing the state to temporarily change, an error is generated and a shadow latch restores the correct data. We have demonstrated the functionality of our proposed latch by simulating the design using UMC90nm technology. We also measured error rate of our proposed latch by using an Altera Cyclone II FPGA board. We have obtained the voltage dependence of the error rates. The results show that our proposed latch has less than 1.5% faults propagated at the output.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131301880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-27DOI: 10.1109/IOLTS.2012.6313846
Michele Riga, E. Sánchez, M. Reorda
Caches are crucial components in today's processors (both stand-alone or integrated into SoCs) and they account for a growing percentage of the occupied silicon area. Therefore, their test (both at the end of the manufacturing and on-line) is crucial for the quality and reliability of the whole product. While in many cases cache test is based on Design for Testability (DfT) techniques, there are situations in which the functional approach is the only viable one. Previous papers addressed the issue of developing test programs for testing caches: since the constant trend is to organize them in different levels, in this paper we address the test of second level caches (L2). To the best of our knowledge, the paper presents the first functional test method for L2 caches: some experimental results also are provided to assess its effectiveness on the OpenSPARC T1 processor.
{"title":"On the functional test of L2 caches","authors":"Michele Riga, E. Sánchez, M. Reorda","doi":"10.1109/IOLTS.2012.6313846","DOIUrl":"https://doi.org/10.1109/IOLTS.2012.6313846","url":null,"abstract":"Caches are crucial components in today's processors (both stand-alone or integrated into SoCs) and they account for a growing percentage of the occupied silicon area. Therefore, their test (both at the end of the manufacturing and on-line) is crucial for the quality and reliability of the whole product. While in many cases cache test is based on Design for Testability (DfT) techniques, there are situations in which the functional approach is the only viable one. Previous papers addressed the issue of developing test programs for testing caches: since the constant trend is to organize them in different levels, in this paper we address the test of second level caches (L2). To the best of our knowledge, the paper presents the first functional test method for L2 caches: some experimental results also are provided to assess its effectiveness on the OpenSPARC T1 processor.","PeriodicalId":246222,"journal":{"name":"2012 IEEE 18th International On-Line Testing Symposium (IOLTS)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127698693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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