Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802137
L. Tan, Cheng Yanhuan, Weijia Duan, Zhengquan Li
A coplanar waveguide fed roof-shaped multiband antenna is proposed for Wireless Personal Area Network applications. To operate effectively at the desired multi bands, the antenna consists of a roof-shaped radiation unit, a right microstrip radiation unit, a left microstrip radiation unit and an independent inverted L-shaped microstrip radiation unit. The roof-shaped radiation unit is connected with the coplanar waveguide feed. There are two symmetrical antennae on the top of the roof-shaped radiation unit to play the role of coupling. The right independent inverted L-shape microstrip unit is the main radiation unit at 900 MHz, which is composed of two mutually perpendicularly connected microstrip lines. The left microstrip radiation unit connected with the roof-shaped radiation unit is the main radiation unit at 500 MHz. The measured results prove the antenna operates at multiple frequency bands of 500/900/1500/2400 MHz.
{"title":"Coplanar Waveguide Fed Roof-Shaped Multiband Antenna for WPAN Applications","authors":"L. Tan, Cheng Yanhuan, Weijia Duan, Zhengquan Li","doi":"10.1109/iccss55260.2022.9802137","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802137","url":null,"abstract":"A coplanar waveguide fed roof-shaped multiband antenna is proposed for Wireless Personal Area Network applications. To operate effectively at the desired multi bands, the antenna consists of a roof-shaped radiation unit, a right microstrip radiation unit, a left microstrip radiation unit and an independent inverted L-shaped microstrip radiation unit. The roof-shaped radiation unit is connected with the coplanar waveguide feed. There are two symmetrical antennae on the top of the roof-shaped radiation unit to play the role of coupling. The right independent inverted L-shape microstrip unit is the main radiation unit at 900 MHz, which is composed of two mutually perpendicularly connected microstrip lines. The left microstrip radiation unit connected with the roof-shaped radiation unit is the main radiation unit at 500 MHz. The measured results prove the antenna operates at multiple frequency bands of 500/900/1500/2400 MHz.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"2011 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131356518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802344
Siwan Dong, Sen Bu
A high linearity and low load regulation LDO with SATEC and TIR compensation is proposed in this paper. The sub-amplifier transconductance-enhancement compensation (SATEC) and transistor impedance regulation (TIR) structures are proposed to improve the linearity and load regulation. The LDO loop gain and phase margin (PM) are enhanced mainly by compensating and increasing the transconductance. The verification of design is completed under a standard 0.1Sμm CMOS process. The simulation results show that within the scope of output voltage ranges from 1. 0V to 1. 6V and input ranges from 1. 2V to 1.SV. The proposed LDO structure has linear regulation rate of 0.301mV/V and load regulation rate of 0. 000023mV/A, with withstands load current transients up to 120mA and remain over 60dB PSR at 10kHz.
{"title":"A High Linearity and Low Load Regulation LDO with SATEC and TIR Compensation","authors":"Siwan Dong, Sen Bu","doi":"10.1109/iccss55260.2022.9802344","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802344","url":null,"abstract":"A high linearity and low load regulation LDO with SATEC and TIR compensation is proposed in this paper. The sub-amplifier transconductance-enhancement compensation (SATEC) and transistor impedance regulation (TIR) structures are proposed to improve the linearity and load regulation. The LDO loop gain and phase margin (PM) are enhanced mainly by compensating and increasing the transconductance. The verification of design is completed under a standard 0.1Sμm CMOS process. The simulation results show that within the scope of output voltage ranges from 1. 0V to 1. 6V and input ranges from 1. 2V to 1.SV. The proposed LDO structure has linear regulation rate of 0.301mV/V and load regulation rate of 0. 000023mV/A, with withstands load current transients up to 120mA and remain over 60dB PSR at 10kHz.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116434639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The storage capacity of NAND Flash memory has increased by scaling down to smaller cell size and using multi-level storage technology, but data reliability is degraded by severer retention errors. As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays NAND Flash memory, Low Density Parity Check (LDPC) codes are recently proposed due to their outstanding error correcting capability. Herein, a novel construction scheme of LDPC for NAND Flash memory is proposed. By using the proposed scheme, a high code-rate, high performance of Bit Error Rate (BER), low error floor Quasi Cyclic Low Density Parity Check (QC-LDPC) code is constructed to meet the needs of NAND Flash memory. In the proposed LDPC construction scheme, iterative cycle elimination technique is introduced to ensure that the checksum matrix is cycle-4 free and has minimal cycle-6, which is beneficial to achive high performance of BER and low error floor for high code-rate LDPC. A diagonal coding structure is used in the QC-LDPC code to achieve linear-time coding and meet the high throughput requirements of NAND Flash memory. Simulation results show that NAND Flash memory can be used more 1800 times for Program/Erase (P/E) cycle by using the proposed QC-LDPC codes compared with Euclidean-Geometry LDPC codes. The error floor of the constructed QC-LDPC codes is below 1$0^{-12}$.
{"title":"A Novel LDPC Construction Scheme for NAND Flash Memory","authors":"Hongyuan Li, Xiaobo Jiang, Zhenghong Yu, Wanjun Zheng","doi":"10.1109/iccss55260.2022.9802213","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802213","url":null,"abstract":"The storage capacity of NAND Flash memory has increased by scaling down to smaller cell size and using multi-level storage technology, but data reliability is degraded by severer retention errors. As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays NAND Flash memory, Low Density Parity Check (LDPC) codes are recently proposed due to their outstanding error correcting capability. Herein, a novel construction scheme of LDPC for NAND Flash memory is proposed. By using the proposed scheme, a high code-rate, high performance of Bit Error Rate (BER), low error floor Quasi Cyclic Low Density Parity Check (QC-LDPC) code is constructed to meet the needs of NAND Flash memory. In the proposed LDPC construction scheme, iterative cycle elimination technique is introduced to ensure that the checksum matrix is cycle-4 free and has minimal cycle-6, which is beneficial to achive high performance of BER and low error floor for high code-rate LDPC. A diagonal coding structure is used in the QC-LDPC code to achieve linear-time coding and meet the high throughput requirements of NAND Flash memory. Simulation results show that NAND Flash memory can be used more 1800 times for Program/Erase (P/E) cycle by using the proposed QC-LDPC codes compared with Euclidean-Geometry LDPC codes. The error floor of the constructed QC-LDPC codes is below 1$0^{-12}$.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131357037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802390
{"title":"ICCSS 2022 Cover Page","authors":"","doi":"10.1109/iccss55260.2022.9802390","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802390","url":null,"abstract":"","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125526461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802228
Ahmad Raza, Fawad Saeed, Sajid Hussain, Abida Perveen, A. Asghar, N. Din, Qasim Khan, W. Lei
Research towards Quantum Dots (QDs) derived from CdSe/ZnS has attracted worldwide attention because of its exceptional optoelectronic properties and use in quantum dots-based light emitting diodes. Usually, a highly conductive electron-transport layer along with hole-transporting layers (HTLs) having low-mobility, and a vacuum-deposited opaque metal electrode are used in the inverted CdSe/ZnS-based QLED. Because of this structure, unbalanced charge injection into the emissive layer occurs, affecting the device's output luminance and stability. Additionally, the fabrication process is more challenging, costly, and time-consuming when using the vacuum-deposition approach. In order to address all of these issues, we used a non-vacuum technique for fabricating an all-solution processable double-sided emitting inverted QLED with a cascade structure and a transparent gold nanowire (AuNW) electrode to obtain emission at the top-side. According to the results, the fabricated QLED had a low turn-on voltage of 2.2 V, luminance of 3905 cd m-2, high current efficiency of 5.9 cd A-1 and a 3.4 % external quantum efficiency. Double-sided QLED devices with AuNW electrode might lead to new lighting and display technologies, according to the findings of this study.
CdSe/ZnS衍生的量子点(QDs)由于其优异的光电性能和在量子点发光二极管中的应用而引起了全世界的关注。通常，高导电性的电子传输层和低迁移率的空穴传输层(HTLs)以及真空沉积的不透明金属电极被用于反向CdSe/ zns基QLED。由于这种结构，会产生不平衡的电荷注入发射层，影响器件的输出亮度和稳定性。此外，当使用真空沉积方法时，制造过程更具挑战性，成本高，耗时长。为了解决所有这些问题，我们使用了一种非真空技术来制造具有级联结构和透明金纳米线(AuNW)电极的全溶液可加工双面发射倒置QLED，以获得顶部发射。结果表明，所制备的QLED具有低导通电压2.2 V、亮度3905 cd - m-2、高电流效率5.9 cd - a -1和3.4 %的外量子效率。根据这项研究的发现，带有AuNW电极的双面QLED设备可能会带来新的照明和显示技术。
{"title":"Double-sided Emission of Inverted Quantum-dot Light Emitting Diode by Using Gold Nanowires (AuNW)","authors":"Ahmad Raza, Fawad Saeed, Sajid Hussain, Abida Perveen, A. Asghar, N. Din, Qasim Khan, W. Lei","doi":"10.1109/iccss55260.2022.9802228","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802228","url":null,"abstract":"Research towards Quantum Dots (QDs) derived from CdSe/ZnS has attracted worldwide attention because of its exceptional optoelectronic properties and use in quantum dots-based light emitting diodes. Usually, a highly conductive electron-transport layer along with hole-transporting layers (HTLs) having low-mobility, and a vacuum-deposited opaque metal electrode are used in the inverted CdSe/ZnS-based QLED. Because of this structure, unbalanced charge injection into the emissive layer occurs, affecting the device's output luminance and stability. Additionally, the fabrication process is more challenging, costly, and time-consuming when using the vacuum-deposition approach. In order to address all of these issues, we used a non-vacuum technique for fabricating an all-solution processable double-sided emitting inverted QLED with a cascade structure and a transparent gold nanowire (AuNW) electrode to obtain emission at the top-side. According to the results, the fabricated QLED had a low turn-on voltage of 2.2 V, luminance of 3905 cd m-2, high current efficiency of 5.9 cd A-1 and a 3.4 % external quantum efficiency. Double-sided QLED devices with AuNW electrode might lead to new lighting and display technologies, according to the findings of this study.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127939288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802313
Zhao Jin, Zhuoya Zhu, Wei Lei, Yi Xie
Vertical channel vacuum transistors are concerned due to high electron mobility, environmental resistance and compatibility with semiconductor processes. A new cross-shaped vertical channel vacuum transistor is proposed in this paper. The structure can effectively reduce gate leakage current and inter-electrode capacitance. Compared to previous structures of this type of device, cross-shaped structure has better emission efficiency and high-frequency performance.
{"title":"A Cross-shaped Vertical Vacuum Channel Transistor","authors":"Zhao Jin, Zhuoya Zhu, Wei Lei, Yi Xie","doi":"10.1109/iccss55260.2022.9802313","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802313","url":null,"abstract":"Vertical channel vacuum transistors are concerned due to high electron mobility, environmental resistance and compatibility with semiconductor processes. A new cross-shaped vertical channel vacuum transistor is proposed in this paper. The structure can effectively reduce gate leakage current and inter-electrode capacitance. Compared to previous structures of this type of device, cross-shaped structure has better emission efficiency and high-frequency performance.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117268756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802341
Young Suh Song, Shubham Tayal, Dr. Shiromani Balmukund Rahi, J. Kim, A. Upadhyay, Byung-Gook Park
The high integration of integrated circuit (IC) chip design has made thermal-aware design as one of the first priorities of the modern IC chip industry. Even though the modern IC chip technologies have aimed to achieve thermal stability by optimizing circuit design, the rapidly growing integration requires thermal-aware design not only in circuit level but also in transistor level. Such thermal-aware design with bottom-up (from the transistor level to the packaging level) can be used to reliable IC chips. Moreover, since aluminum oxide (Al2O3, also known as alumina) is compatible with CMOS fabrication process and has excellent thermal conductivity, it is possible to efficiently accomplish the improved thermal-aware design. Specifically, Al2O3 has 59 times thermal conductivity compared to HfO2, and 19 times thermal conductivity compared to SiO2. In this paper, considering the outstanding thermal characteristics of Al2O3 we propose a comprehensive improvement including thermal characteristics by combining Al2O3 and GAA MOSFET. As a result, the maximum lattice temperature ($T_{max}$) in transistor has been significantly improved from 624 K to 518 K. In addition, capacitance of transistor could be also decreased, which will give benefits to inverter delay and three-stage ring oscillator (RO3) delay in IC chip.
{"title":"Thermal-Aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET","authors":"Young Suh Song, Shubham Tayal, Dr. Shiromani Balmukund Rahi, J. Kim, A. Upadhyay, Byung-Gook Park","doi":"10.1109/iccss55260.2022.9802341","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802341","url":null,"abstract":"The high integration of integrated circuit (IC) chip design has made thermal-aware design as one of the first priorities of the modern IC chip industry. Even though the modern IC chip technologies have aimed to achieve thermal stability by optimizing circuit design, the rapidly growing integration requires thermal-aware design not only in circuit level but also in transistor level. Such thermal-aware design with bottom-up (from the transistor level to the packaging level) can be used to reliable IC chips. Moreover, since aluminum oxide (Al2O3, also known as alumina) is compatible with CMOS fabrication process and has excellent thermal conductivity, it is possible to efficiently accomplish the improved thermal-aware design. Specifically, Al2O3 has 59 times thermal conductivity compared to HfO2, and 19 times thermal conductivity compared to SiO2. In this paper, considering the outstanding thermal characteristics of Al2O3 we propose a comprehensive improvement including thermal characteristics by combining Al2O3 and GAA MOSFET. As a result, the maximum lattice temperature ($T_{max}$) in transistor has been significantly improved from 624 K to 518 K. In addition, capacitance of transistor could be also decreased, which will give benefits to inverter delay and three-stage ring oscillator (RO3) delay in IC chip.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115393952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802272
Yier Xia, Wenqian Li, Shengshun Duan, Wei Lei, Jun Wu
In the new coming era of metaverse, natural and continuous interactions between human beings and XR devices is vital. Yet, the current rigid wearable devices come with bulky occupation, heavy weight, and high cost. Herein, based on thermal transfer printing techniques, we proposed a more skin-compatible soft electronic glove with low cost ($sim {$}13.5$ per unit), light weight (~25.5g), and scalability for mass production. Through monitoring bending states of five fingers, the electronic glove can recognize hand gesture, and, as a demonstration, control a customized VR shooting game.
{"title":"Low-cost, Light-weight Scalable Soft Data Glove for VR Applications","authors":"Yier Xia, Wenqian Li, Shengshun Duan, Wei Lei, Jun Wu","doi":"10.1109/iccss55260.2022.9802272","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802272","url":null,"abstract":"In the new coming era of metaverse, natural and continuous interactions between human beings and XR devices is vital. Yet, the current rigid wearable devices come with bulky occupation, heavy weight, and high cost. Herein, based on thermal transfer printing techniques, we proposed a more skin-compatible soft electronic glove with low cost ($sim {$}13.5$ per unit), light weight (~25.5g), and scalability for mass production. Through monitoring bending states of five fingers, the electronic glove can recognize hand gesture, and, as a demonstration, control a customized VR shooting game.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131150029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802338
Xueting Zhao, Xinpeng Xing, Gaofeng Luan, Zhengzhong Wu, Zhihua Wang
This paper presents a high-precision and low-power two-stage miller-compensated instrumentation amplifier for sensor readout circuits. Folded-cascode structure with complementary input differential pairs and translinear-loop-based class AB circuit are adopted as the amplifier first and second stages respectively, to achieve rail-to-rail input and output ranges. The presented instrumentation amplifier is implemented in a 0.18μm BCD technology. Measurement results show that with a load of 100pF and 100kΩ, the presented amplifier achieves 79. 79dB gain, 1. 35MHz gain-bandwidth product (GBW) and 92. 3dB power supply rejection ratio (PSRR). The measured amplifier gain error is 0.11%; and its input offset voltage is 0. 3mV. This amplifier totally consumes 0. 19mW power from a 3V supply voltage.
{"title":"Design and Implementation of A High-Precision Low-Power Instrumentation Amplifier","authors":"Xueting Zhao, Xinpeng Xing, Gaofeng Luan, Zhengzhong Wu, Zhihua Wang","doi":"10.1109/iccss55260.2022.9802338","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802338","url":null,"abstract":"This paper presents a high-precision and low-power two-stage miller-compensated instrumentation amplifier for sensor readout circuits. Folded-cascode structure with complementary input differential pairs and translinear-loop-based class AB circuit are adopted as the amplifier first and second stages respectively, to achieve rail-to-rail input and output ranges. The presented instrumentation amplifier is implemented in a 0.18μm BCD technology. Measurement results show that with a load of 100pF and 100kΩ, the presented amplifier achieves 79. 79dB gain, 1. 35MHz gain-bandwidth product (GBW) and 92. 3dB power supply rejection ratio (PSRR). The measured amplifier gain error is 0.11%; and its input offset voltage is 0. 3mV. This amplifier totally consumes 0. 19mW power from a 3V supply voltage.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128845282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-05-13DOI: 10.1109/iccss55260.2022.9802412
Kefan Qin, Wei Ma, Chang-chen Hu, Guobin Shuai, Weibo Hu
This paper presents a wireless universal brain-machine interface (BMI) system. The proposed system integrates three main modules, including an electroencephalogram (EEG) signal analyzer, a neural stimulator, and a PC user interface. Its functionalities include EEG signal acquisition, digital signal processing, electrical stimulation and so on. It can continuously monitor EEG signal status in real time, quickly diagnose brain abnormal activities and correctly generate a proper stimulation if needed. In the EEG signal analyzer, the EEG signal acquisition pathway consists of a four-channel analog front-end featuring high gain and high CMRR. Under the control of an MCU, EEG data are transmitted to the PC in real time through a Bluetooth connection. Then the PC analyzes the EEG signals through the algorithm based on the new Teager energy operator and multiscale entropy. The neural stimulator can provide both positive and negative current stimulations which have programmable pulse width and frequency. Experiment results show that the neural stimulator can generate ±1 mA stimulation current output at ±5 V supply voltage.
{"title":"A Wireless Universal Brain-Machine Interface (BMI) System for Epileptic Diseases","authors":"Kefan Qin, Wei Ma, Chang-chen Hu, Guobin Shuai, Weibo Hu","doi":"10.1109/iccss55260.2022.9802412","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802412","url":null,"abstract":"This paper presents a wireless universal brain-machine interface (BMI) system. The proposed system integrates three main modules, including an electroencephalogram (EEG) signal analyzer, a neural stimulator, and a PC user interface. Its functionalities include EEG signal acquisition, digital signal processing, electrical stimulation and so on. It can continuously monitor EEG signal status in real time, quickly diagnose brain abnormal activities and correctly generate a proper stimulation if needed. In the EEG signal analyzer, the EEG signal acquisition pathway consists of a four-channel analog front-end featuring high gain and high CMRR. Under the control of an MCU, EEG data are transmitted to the PC in real time through a Bluetooth connection. Then the PC analyzes the EEG signals through the algorithm based on the new Teager energy operator and multiscale entropy. The neural stimulator can provide both positive and negative current stimulations which have programmable pulse width and frequency. Experiment results show that the neural stimulator can generate ±1 mA stimulation current output at ±5 V supply voltage.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128191521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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