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ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.最新文献

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Low power SRAM techniques for handheld products 用于手持产品的低功耗SRAM技术
R. Islam, A. Brand, Dave Lippincott
SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse bias techniques for leakage reduction are implemented in a 2MByte SRAM testchip built with low power 90nm technology. Sophisticated analog regulators were implemented to precisely control the PMOS and NMOS reverse bias levels. The application of the reverse bias led to a 16X reduction in total array standby leakage and a cell leakage of only 20pA/bit. Excellent data retention for these bias conditions was demonstrated with detailed Vccmin mesurements.
SRAM泄漏构成了用于手持应用(如PDA和蜂窝电话)的现代SoC产品的待机功率预算的重要部分。NMOS和PMOS反向偏置技术用于减少泄漏,在采用低功耗90nm技术构建的2MByte SRAM测试芯片上实现。采用复杂的模拟调节器来精确控制PMOS和NMOS的反向偏置电平。反向偏置的应用导致总阵列待机泄漏减少16倍,单元泄漏仅为20pA/bit。通过详细的Vccmin测量,证明了这些偏置条件下的出色数据保留。
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引用次数: 16
A GHz-class charge recovery logic 一个ghz级电荷恢复逻辑
V. Sathe, M. Papaefthymiou, C. Ziesler
This paper describes Boost Logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery, to achieve high energy efficiency at GHz frequencies. The key feature of our design is an energy recovering "boost" stage that provides a high gate overdrive to an aggressively voltage-scaled logic at near-threshold supply voltage. We have evaluated Boost Logic through post-layout simulation of an 8-bit carry-save multiplier in a 0.13/spl mu/m CMOS process with V/sub th/=340mV. At 1.6GHz and 1.3V supply voltage, the Boost multiplier dissipates 8.11pJ per computation, yielding 68% energy savings over its pipelined, voltage-scaled static CMOS counterpart. Using low V/sub th/ devices, the Boost Logic multiplier has been verified to operate at 2GHz with a 1.25V voltage supply and 8.50pJ energy dissipation per cycle.
Boost Logic是一种依赖于电压缩放、栅极超速驱动和能量回收的逻辑系列,可在GHz频率下实现高能效。我们设计的关键特征是一个能量回收“升压”级,它在接近阈值的电源电压下为积极的电压缩放逻辑提供高栅极超速驱动。我们通过在0.13/spl mu/m CMOS工艺(V/sub /=340mV)中8位进位节省乘法器的布局后仿真来评估Boost Logic。在1.6GHz和1.3V供电电压下,Boost乘法器每次计算耗散8.11pJ,比其流水线、电压缩放的静态CMOS对应物节省68%的能量。使用低V/sub /器件,Boost Logic乘法器已被验证工作在2GHz下,电压为1.25V,每周期能量消耗为8.50pJ。
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引用次数: 3
Two efficient methods to reduce power and testing time 两种降低功耗和测试时间的有效方法
Il-soo Lee, T. Ambler
Reducing power dissipation and testing time is accomplished by forming two clusters of don't-care bit inside an input and a response test cube. New reordering scheme of scan latches is proposed to create the clusters of don't-care bit, and two proposed reconfigured scan architecture guarantee to remove the clusters from the scan operation. The size of these clusters is directly proportional to the amount of power and testing time that is reduced. Results with ISCAS'89 benchmark circuits show good improvement in both power consumption and test time.
通过在输入和响应测试立方体内形成两组无关钻头,可以降低功耗和测试时间。提出了一种新的扫描锁存器重新排序方案,以创建不关心位的簇,并提出了两种重新配置的扫描结构,以保证在扫描操作中消除簇。这些集群的大小与减少的功耗和测试时间成正比。ISCAS’89基准电路的测试结果表明,在功耗和测试时间方面都有很好的改善。
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引用次数: 6
The need for a full-chip and package thermal model for thermally optimized IC designs 对于热优化IC设计的全芯片和封装热模型的需求
Wei Huang, Eric Humenay, K. Skadron, M. Stan
Modeling and analyzing detailed die temperature with a full-chip thermal model at early design stages is important to discover and avoid potential thermal hazards. However, omitting important aspects of package details in a thermal model can result in significant temperature estimation errors. In this paper, we discuss the applications of an existing compact thermal model that models both die and package temperature details. As an example, a thermally self-consistent leakage power calculation of a POWER4-like microprocessor design is presented. We then demonstrate the importance of including detailed package information in the thermal model by several examples considering the impact of thermal interface material (TIM), which glues the die to the heat spreader. The fact that detailed package information is needed to build an accurate compact thermal model implies a design flow, in which the chip- and package-level compact thermal model acts as a convenient medium for more productive collaborations among circuit designers, computer architects and package designers, leading to early and efficient evaluations of different design tradeoffs for an optimal design from a thermal point of view.
在设计初期利用全芯片热模型对模具温度进行建模和分析,对于发现和避免潜在的热危害具有重要意义。然而,在热模型中忽略封装细节的重要方面可能导致显著的温度估计误差。在本文中,我们讨论了现有的紧凑热模型的应用,该模型可以模拟模具和封装的温度细节。以类似power4的微处理器设计为例,给出了热自洽泄漏功率的计算方法。然后,我们通过考虑热界面材料(TIM)的影响的几个例子,证明了在热模型中包含详细封装信息的重要性,热界面材料将模具粘合到散热器上。构建精确的紧凑热模型需要详细的封装信息,这意味着需要一个设计流程,其中芯片和封装级紧凑热模型作为电路设计师、计算机架构师和封装设计师之间更有效合作的方便媒介,从而从热的角度对不同的设计权衡进行早期和有效的评估,以实现最佳设计。
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引用次数: 57
Complexity reduction in an nRERL microprocessor 降低nrel微处理器的复杂性
Seokkee Kim, S. Chae
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL (Lim et al., 2000). We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers required for the phase aligning in the adiabatic microprocessor. Furthermore, by breaking the logic reversibility with self-energy recovery circuits, we also reduced its complexity as well as its energy consumption. We integrated an 8-bit nRERL microprocessor with an 8-phase clocked power generator into a chip with 0.25/spl mu/m CMOS technology. Its minimum energy consumption of 4.67/spl mu/A/MHz was measured at V/sub dd/=2.4V and f=651kHz, which was about 40% compared to the previous 6-phase version. Its circuit complexity was also reduced down to 65% that of its 6-phase version.
我们描述了一种用可逆逻辑实现的绝热微处理器,nerrl (Lim等人,2000)。我们采用了8相时钟电源而不是6相电源,以减少绝热微处理器中相位对准所需的缓冲区数量。此外,我们还利用自能量恢复电路打破了逻辑可逆性,降低了其复杂性和能量消耗。我们将8位nrel微处理器与8相时钟电源集成到0.25/spl mu/m CMOS技术的芯片中。在V/sub dd/=2.4V, f=651kHz时,其最小能耗为4.67/spl mu/A/MHz,比之前的6相版本降低了约40%。它的电路复杂性也降低到6相版本的65%。
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引用次数: 4
Snug set-associative caches. Reducing leakage power while improving performance 舒适的集关联缓存。在提高性能的同时减少泄漏功率
Jia-Jhe Li, Yuan-Shin Hwang
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Several techniques have already been proposed to reduce leakage power by turning off unused cache lines. However, they all have to pay the price of performance degradation. This paper presents a cache architecture, the snug set-associative (SSA) cache, that does not only cut most of static power dissipation but also reduces execution times. The SSA cache reduces leakage power by implementing the minimum set-associative scheme, which only activates the minimal numbers of ways in each cache set, while the performance losses incurred by this scheme are compensated by the base-offset load/store queues. These two techniques are both developed based on the principle of locality and they work together nicely - experimental results show that the minimum set-associative scheme can cut static power consumption of the L1 data cache by 90% on average for SPECint2000 benchmarks, while the execution times are reduced by 3% when the default 8-entry load/store queue is modified to the base-offset design. Furthermore, the SSA cache can trim the leakage power of L2 data cache by 96% on average while still accomplishing a 3% reduction in execution times.
随着晶体管的不断缩小和片上数据缓存的不断增长,由于缓存泄漏引起的静态功耗在处理器总功耗中所占的比例越来越大。已经提出了几种通过关闭未使用的缓存线路来减少泄漏功率的技术。然而,它们都必须付出性能下降的代价。本文提出了一种既能减少静态功耗又能减少执行时间的缓存结构,即SSA缓存。SSA缓存通过实现最小集关联方案来降低泄漏功率,该方案在每个缓存集中只激活最小数量的方法,而该方案所造成的性能损失由基本偏移的负载/存储队列补偿。这两种技术都是基于局域性原理开发的,它们可以很好地协同工作——实验结果表明,对于SPECint2000基准测试,最小集关联方案可以将L1数据缓存的静态功耗平均降低90%,而当将默认的8条目负载/存储队列修改为基本偏移设计时,执行时间减少了3%。此外,SSA缓存可以将L2数据缓存的泄漏功率平均减少96%,同时仍然可以减少3%的执行时间。
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引用次数: 9
Analysis and mitigation of variability in subthreshold design 亚阈值设计中可变性的分析与缓解
Bo Zhai, S. Hanson, D. Blaauw, D. Sylvester
Subthreshold circuit design is a compelling method for ultra-low power applications. However, subthreshold designs show dramatically increased sensitivity to process variations due to the exponential relationship of subthreshold drive current with V/sub th/ variation. In this paper, we present an analysis of subthreshold energy efficiency considering process variation, and propose methods to mitigate its impact. We show that, unlike superthreshold circuits, random dopant fluctuation is the dominant component of variation in subthreshold operation. We investigate how this variability can be ameliorated with proper circuit sizing and choice of circuit logic depth. We then present a statistical analysis of the energy efficiency of subthreshold circuits considering process variations. We show that the energy optimal supply voltage increases due to process variations and study its dependence on circuit parameters. We verify our analytical models against Monte Carlo SPICE simulations and show that they accurately predict the minimum energy and energy optimal supply voltage. Finally, we use the developed statistical energy model to determine the optimal pipelining depth in subthreshold designs.
亚阈值电路设计是超低功耗应用的一种引人注目的方法。然而,由于亚阈值驱动电流与V/sub /变化呈指数关系,亚阈值设计对工艺变化的灵敏度显着增加。在本文中,我们提出了考虑过程变化的亚阈值能源效率分析,并提出了减轻其影响的方法。我们表明,与超阈电路不同,随机掺杂波动是亚阈操作变化的主要组成部分。我们研究了如何通过适当的电路尺寸和电路逻辑深度的选择来改善这种可变性。然后,我们对考虑工艺变化的亚阈值电路的能量效率进行了统计分析。我们证明了能量最优电源电压随工艺变化而增加,并研究了其与电路参数的依赖关系。通过Monte Carlo SPICE仿真验证了分析模型的正确性,结果表明该模型准确地预测了最小能量和能量最优供电电压。最后,我们利用所建立的统计能量模型来确定亚阈值设计中的最佳管道深度。
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引用次数: 285
Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage MOSFET阈值电压固有波动的测量和建模
A. Keshavarzi, G. Schrom, Stephen Tang, Sean Ma, K. Bowman, S. Tyagi, Kevin Zhang, T. Linton, N. Hakim, S. Duvall, J. Brews, V. De
Fluctuations in intrinsic linear V/sub T/, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic /spl rho/V/sub T/, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.
在150nm逻辑技术的测试芯片上,测量了大型NMOS和PMOS器件阵列的内在线性V/sub T/波动,不受寄生影响。局部本征/spl rho/V/下标T/,不受外在过程、长度和宽度变化的影响,是随机的,并随着反向体偏而恶化。虽然传统的面积依赖组件占主导地位,但小型器件的波动的重要组成部分仅取决于器件宽度或长度。
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引用次数: 56
FinFET-based SRAM design 基于finfet的SRAM设计
Z. Guo, S. Balasubramanian, R. Zlatanovici, T. King, B. Nikolić
Intrinsic variations and challenging leakage control in today's bulk-Si MOSFETs limit the scaling of SRAM. Design tradeoffs in six-transistor (6-T) and four-transistor (4-T) SRAM cells are presented in this work. It is found that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty. Up to 2/spl times/ improvement in SNM can be achieved in 6-T FinFET-based SRAM cells. A 4-T FinFET-based SRAM cell with built-in feedback can achieve sub-100pA per-cell standby current and offer the similar improvements in SNM as the 6-T cell with feedback, making them attractive for low-power, low-voltage applications.
当今体积硅mosfet的固有变化和具有挑战性的泄漏控制限制了SRAM的缩放。本文介绍了六晶体管(6-T)和四晶体管(4-T) SRAM单元的设计权衡。研究发现,采用内置反馈设计的6-T和4-T finfet SRAM单元在没有面积损失的情况下显著改善了单元静态噪声裕度(SNM)。在基于6-T finfet的SRAM单元中,SNM可以实现高达2/spl倍的改进。带有内置反馈的基于4-T finfet的SRAM单元可以实现每个单元低于100pa的待机电流,并且在SNM方面提供与带有反馈的6-T单元类似的改进,使其对低功耗、低电压应用具有吸引力。
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引用次数: 169
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs 基于代数决策图(ADD)的组合设计泄漏直方图查找技术
Kanupriya Gulati, N. Jayakumar, S. Khatri
In this paper, we present an algebraic decision diagram (ADD) based approach to determine and implicitly represent the leakage value for all input vectors of a combinational circuit. In its exact form, our technique can compute the leakage value of each input vector. To broaden the applicability of our technique, we present an approximate version of our algorithm as well. The approximation is done by limiting the total number of discriminant nodes in any ADD. Previous sleep vector computation techniques can find either the maximum or minimum sleep vector. Our technique computes the leakages for all vectors, storing them implicitly in an ADD structure. We experimentally demonstrate that these approximate techniques produce results which have reasonable errors. We also show that limiting the number of discriminants to a value between 12 and 16 is practical, allowing for good accuracy and lowered memory utilization.
本文提出了一种基于代数决策图(ADD)的方法来确定和隐式表示组合电路的所有输入向量的泄漏值。在其精确形式中,我们的技术可以计算每个输入向量的泄漏值。为了扩大我们的技术的适用性,我们也提出了我们算法的近似版本。该近似是通过限制任何ADD中判别节点的总数来完成的。以前的睡眠向量计算技术可以找到最大或最小睡眠向量。我们的技术计算所有向量的泄漏,将它们隐式地存储在ADD结构中。实验证明,这些近似技术所产生的结果具有合理的误差。我们还表明,将判别符的数量限制在12到16之间的值是实用的,允许良好的准确性和降低内存利用率。
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引用次数: 3
期刊
ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.
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