Approximate computing in hardware is generally aimed at power or energy optimization as the primary target. We suggest that hardware approximate computing can be more beneficial when area reduction is the primary target. Additionally, we advocate that the hardware approximation schemes which allow usage of high-level libraries for their sub-components can leverage the power offered by modern synthesis tools. We demonstrate using experimental results that such approximations therefore achieve more efficient synthesis than the deeply hierarchical approximations.
{"title":"Hardware approximate computing: how, why, when and where? (special session)","authors":"Hassaan Saadat, S. Parameswaran","doi":"10.1145/3125501.3125518","DOIUrl":"https://doi.org/10.1145/3125501.3125518","url":null,"abstract":"Approximate computing in hardware is generally aimed at power or energy optimization as the primary target. We suggest that hardware approximate computing can be more beneficial when area reduction is the primary target. Additionally, we advocate that the hardware approximation schemes which allow usage of high-level libraries for their sub-components can leverage the power offered by modern synthesis tools. We demonstrate using experimental results that such approximations therefore achieve more efficient synthesis than the deeply hierarchical approximations.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133912940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The memory subsystem is a major contributor to the overall performance and energy consumption of embedded computing platforms. The emergence of "killer" applications such as data-intensive recognition, mining, and synthesis (RMS) applications puts even more stress on the memory subsystem and exacerbates its energy consumption. Traditional mechanisms to ensure data integrity deploy overdesign (e.g., redundancy and error detection/correction) and/or guard-banding that consumes a significant part of the energy consumed in the memory subsystem. We explore opportunities for energy efficiency by exploiting the intrinsic tolerance of a vast class of approximate computing applications to some level of error in the on-chip memory hierarchy. We present two exemplars outlining the typical software and hardware mechanisms that are required for different components in the memory hierarchy, implemented in varying technologies such as SRAM and STT-MRAM.
{"title":"Quality-configurable memory hierarchy through approximation: special session","authors":"Majid Namaki-Shoushtari, A. Rahmani, N. Dutt","doi":"10.1145/3125501.3125525","DOIUrl":"https://doi.org/10.1145/3125501.3125525","url":null,"abstract":"The memory subsystem is a major contributor to the overall performance and energy consumption of embedded computing platforms. The emergence of \"killer\" applications such as data-intensive recognition, mining, and synthesis (RMS) applications puts even more stress on the memory subsystem and exacerbates its energy consumption. Traditional mechanisms to ensure data integrity deploy overdesign (e.g., redundancy and error detection/correction) and/or guard-banding that consumes a significant part of the energy consumed in the memory subsystem. We explore opportunities for energy efficiency by exploiting the intrinsic tolerance of a vast class of approximate computing applications to some level of error in the on-chip memory hierarchy. We present two exemplars outlining the typical software and hardware mechanisms that are required for different components in the memory hierarchy, implemented in varying technologies such as SRAM and STT-MRAM.","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132147669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","authors":"","doi":"10.1145/3125501","DOIUrl":"https://doi.org/10.1145/3125501","url":null,"abstract":"","PeriodicalId":259093,"journal":{"name":"Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125954606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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