Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451776
T. Zahner
Summary form given only. The junction temperature of Light Emitting Diodes (LEDs) is a primary reliability parameter. Exceeding the maximum rated junction temperature could lead to accelerated light output degradation and sometimes even to catastrophic failures. Besides that junction temperature influences the desired LED properties in applications like light output efficiency, dominant wavelength and forward voltage. Therefore thermal management and proper thermal characterisation of high power LEDs is very important for a reliable product with good performance. By measuring the thermal resistance of a high power LED it has to take into account that the power applied to the device is converted into heat and light (-20-40% efficiency). This means that the thermal resistance of a LED can not be determined without knowing the energy flux emitted as light. Therefore in general the interpretation of a given thermal resistance of an optoelectronic device is not well defined. Establishing of a standard on how to do thermal resistance measurement for light emitting devices is necessary.
{"title":"Thermal management and thermal resistance of high power LEDs","authors":"T. Zahner","doi":"10.1109/THERMINIC.2007.4451776","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451776","url":null,"abstract":"Summary form given only. The junction temperature of Light Emitting Diodes (LEDs) is a primary reliability parameter. Exceeding the maximum rated junction temperature could lead to accelerated light output degradation and sometimes even to catastrophic failures. Besides that junction temperature influences the desired LED properties in applications like light output efficiency, dominant wavelength and forward voltage. Therefore thermal management and proper thermal characterisation of high power LEDs is very important for a reliable product with good performance. By measuring the thermal resistance of a high power LED it has to take into account that the power applied to the device is converted into heat and light (-20-40% efficiency). This means that the thermal resistance of a LED can not be determined without knowing the energy flux emitted as light. Therefore in general the interpretation of a given thermal resistance of an optoelectronic device is not well defined. Establishing of a standard on how to do thermal resistance measurement for light emitting devices is necessary.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126315399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451778
D. Mitrani, J. Salazar, A. Turó, M.J. Garcia, J. Chávez
Based on simplified one-dimensional steady-state analysis of thermoelectric phenomena and on analogies between thermal and electrical domains, we propose both lumped and distributed parameter electrical models for thermoelectric devices. For lumped parameter models, constant values for material properties are extracted from polynomial fit curves evaluated at different module temperatures (hot side, cold side, average, and mean module temperature). For the case of distributed parameter models, material properties are calculated according to the mean temperature at each segment of a sectioned device. A couple of important advantages of the presented models are that temperature dependence of material properties is considered and that they can be easily simulated using an electronic simulation tool such as SPICE. Comparisons are made between SPICE simulations for a single-pellet module using the proposed models and with numerical simulations carried out with Mathematica software. Results illustrate accuracy of the distributed parameter models and show how inappropriate is to assume, in some cases, constant material parameters for an entire thermoelectric element.
{"title":"Lumped and distributed parameter SPICE models of TE devices considering temperature dependent material properties","authors":"D. Mitrani, J. Salazar, A. Turó, M.J. Garcia, J. Chávez","doi":"10.1109/THERMINIC.2007.4451778","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451778","url":null,"abstract":"Based on simplified one-dimensional steady-state analysis of thermoelectric phenomena and on analogies between thermal and electrical domains, we propose both lumped and distributed parameter electrical models for thermoelectric devices. For lumped parameter models, constant values for material properties are extracted from polynomial fit curves evaluated at different module temperatures (hot side, cold side, average, and mean module temperature). For the case of distributed parameter models, material properties are calculated according to the mean temperature at each segment of a sectioned device. A couple of important advantages of the presented models are that temperature dependence of material properties is considered and that they can be easily simulated using an electronic simulation tool such as SPICE. Comparisons are made between SPICE simulations for a single-pellet module using the proposed models and with numerical simulations carried out with Mathematica software. Results illustrate accuracy of the distributed parameter models and show how inappropriate is to assume, in some cases, constant material parameters for an entire thermoelectric element.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124641584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451745
C. Lee, A. Robinson, C. Ching
In this investigation, the numerical simulation of electrohydrodynamic (EHD) ion-drag micropumps with micropillar electrode geometries have been performed. The effect of micropillar height and electrode spacing on the performance of the micropumps was investigated. The performance of the EHD micropump improved with increased applied voltage and decreased electrode spacing. The optimum micropillar height for the micropump with electrode spacing of 40 mum and channel height of 100 mum at 200 V was 40 mum, where a maximum mass flow rate of 0.18g/min was predicted. Compared to that of planar electrodes, the 3D micropillar electrode geometry enhanced the overall performance of the EHD micropumps.
{"title":"Development of EHD ion-drag micropump for microscale electronics cooling","authors":"C. Lee, A. Robinson, C. Ching","doi":"10.1109/THERMINIC.2007.4451745","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451745","url":null,"abstract":"In this investigation, the numerical simulation of electrohydrodynamic (EHD) ion-drag micropumps with micropillar electrode geometries have been performed. The effect of micropillar height and electrode spacing on the performance of the micropumps was investigated. The performance of the EHD micropump improved with increased applied voltage and decreased electrode spacing. The optimum micropillar height for the micropump with electrode spacing of 40 mum and channel height of 100 mum at 200 V was 40 mum, where a maximum mass flow rate of 0.18g/min was predicted. Compared to that of planar electrodes, the 3D micropillar electrode geometry enhanced the overall performance of the EHD micropumps.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131660129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451738
B. Smith, T. Brunschwiler, B. Michel
This paper analyzes a transient method for the characterization of low-resistance thermal interfaces of microelectronic packages. The transient method can yield additional information about the package not available with traditional static methods at the cost of greater numerical complexity, hardware requirements, and sensitivity to noise. While the method is established for package-level thermal analysis of mounted and assembled parts, its ability to measure the relatively minor thermal impedance of thin thermal interface material (TIM) layers has not yet been fully studied. We combine the transient thermal test with displacement measurements of the bond line thickness to fully characterize the interface.
{"title":"Utility of transient testing to characterize thermal interface materials","authors":"B. Smith, T. Brunschwiler, B. Michel","doi":"10.1109/THERMINIC.2007.4451738","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451738","url":null,"abstract":"This paper analyzes a transient method for the characterization of low-resistance thermal interfaces of microelectronic packages. The transient method can yield additional information about the package not available with traditional static methods at the cost of greater numerical complexity, hardware requirements, and sensitivity to noise. While the method is established for package-level thermal analysis of mounted and assembled parts, its ability to measure the relatively minor thermal impedance of thin thermal interface material (TIM) layers has not yet been fully studied. We combine the transient thermal test with displacement measurements of the bond line thickness to fully characterize the interface.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134043764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451765
M. Sabry
The flexible profile approach proposed earlier to create CTM (compact or reduced order thermal models) is extended to cover the area of conjugate heat transfer. The flexible profile approach is a methodology that allows building a highly boundary conditions independent CTM, with any desired degree of accuracy, that may adequately replace detailed 3D models for the whole spectrum of applications in which the modeled object may be used. The extension to conjugate problems radically solves the problem of interfacing two different domains. Each domain, fluid or solid, can be "compacted" independently creating two CTM that can be joined together to produce reliable results for any arbitrary set of external boundary conditions.
{"title":"Flexible profile approach to the steady conjugate heat transfer problem","authors":"M. Sabry","doi":"10.1109/THERMINIC.2007.4451765","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451765","url":null,"abstract":"The flexible profile approach proposed earlier to create CTM (compact or reduced order thermal models) is extended to cover the area of conjugate heat transfer. The flexible profile approach is a methodology that allows building a highly boundary conditions independent CTM, with any desired degree of accuracy, that may adequately replace detailed 3D models for the whole spectrum of applications in which the modeled object may be used. The extension to conjugate problems radically solves the problem of interfacing two different domains. Each domain, fluid or solid, can be \"compacted\" independently creating two CTM that can be joined together to produce reliable results for any arbitrary set of external boundary conditions.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134552252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451752
K. Nakabayashi, T. Nakabayashi, K. Nakajima
We present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.
{"title":"Very fast chip-level thermal analysis","authors":"K. Nakabayashi, T. Nakabayashi, K. Nakajima","doi":"10.1109/THERMINIC.2007.4451752","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451752","url":null,"abstract":"We present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133898311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451759
A. Petropoulos, G. Kaltsas, D. Goustouridis, A. Nassiopoulou
A thermal position sensor was fabricated and evaluated. The device consists of an array of temperature sensing elements, fabricated entirely on a plastic substrate. A novel fabrication technology was implemented which allows direct integration with read out electronics and communication to the macro-world without the use of wire bonding. The fabricated sensing elements are temperature sensitive Pt resistors with an average TCR of 0.0024/C. The device realizes the detection of the position and the motion of a heating source by monitoring the resistance variation of the thermistor array. The application field of such a cost-effective position sensor is considered quite extensive.
{"title":"A novel thermal position sensor integrated on a plastic substrate","authors":"A. Petropoulos, G. Kaltsas, D. Goustouridis, A. Nassiopoulou","doi":"10.1109/THERMINIC.2007.4451759","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451759","url":null,"abstract":"A thermal position sensor was fabricated and evaluated. The device consists of an array of temperature sensing elements, fabricated entirely on a plastic substrate. A novel fabrication technology was implemented which allows direct integration with read out electronics and communication to the macro-world without the use of wire bonding. The fabricated sensing elements are temperature sensitive Pt resistors with an average TCR of 0.0024/C. The device realizes the detection of the position and the motion of a heating source by monitoring the resistance variation of the thermistor array. The application field of such a cost-effective position sensor is considered quite extensive.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122563781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thermal management for high performance of miniaturized electronic devices using microchannel heat sinks has recently become of interest to researchers and industry. Obtaining heat sink designs with uniform flow distribution is strongly desired. A number of experimental studies have been conducted to seek appropriate designs for microchannel heat sinks. However, pursuing this goal experimentally can be an expensive endeavor. The present work investigates the effect of cross-links on adiabatic two-phase flow in an array of parallel channels. It is carried out using the three-dimensional mixture model from the computational fluid dynamics (CFD) software, Fluent 6.3. A straight channel and two cross-linked channel models were simulated. The cross-links were located at 1/3 and 2/3's of the channel length, their width varied by one and two times the channel width. All test models had 45 parallel rectangular channels, with a hydraulic diameter of 1.59 mm. The results showed that the trend of flow distribution agrees with experimental results. A new design, with cross-links incorporated, was proposed and the results showed a significant improvement, up to 55%, on flow distribution, compared to the standard straight channel configuration without a penalty in the pressure drop. The effect of cross-links on flow distribution, flow structure, and pressure drop was also documented.
{"title":"Numerically investigating the effects of cross links in scaled microchannel heat sinks","authors":"M. Dang, I. Hassan, S.I. Kim","doi":"10.1115/1.3001093","DOIUrl":"https://doi.org/10.1115/1.3001093","url":null,"abstract":"Thermal management for high performance of miniaturized electronic devices using microchannel heat sinks has recently become of interest to researchers and industry. Obtaining heat sink designs with uniform flow distribution is strongly desired. A number of experimental studies have been conducted to seek appropriate designs for microchannel heat sinks. However, pursuing this goal experimentally can be an expensive endeavor. The present work investigates the effect of cross-links on adiabatic two-phase flow in an array of parallel channels. It is carried out using the three-dimensional mixture model from the computational fluid dynamics (CFD) software, Fluent 6.3. A straight channel and two cross-linked channel models were simulated. The cross-links were located at 1/3 and 2/3's of the channel length, their width varied by one and two times the channel width. All test models had 45 parallel rectangular channels, with a hydraulic diameter of 1.59 mm. The results showed that the trend of flow distribution agrees with experimental results. A new design, with cross-links incorporated, was proposed and the results showed a significant improvement, up to 55%, on flow distribution, compared to the standard straight channel configuration without a penalty in the pressure drop. The effect of cross-links on flow distribution, flow structure, and pressure drop was also documented.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122673378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451757
V. Kosel, R. Sleik, M. Glavanovics
Thermal FEM (Finite Element Method) simulations can be used to predict the thermal behavior of power semiconductors in application. Most power semiconductors are made of silicon. Silicon thermal material properties are significantly temperature dependent. In this paper, validity of a common non-linear silicon material model is verified by transient non-linear thermal FEM simulations of Smart Power Switches and measurements. For verification, over-temperature protection behavior of Smart Power Switches is employed. This protection turns off the switch at a predefined temperature which is used as a temperature reference in the investigation. Power dissipation generated during a thermal overload event of two Smart Power devices is measured and used as an input stimulus to transient thermal FEM simulations. The duration time of the event together with the temperature reference is confronted with simulation results and thus the validity of the silicon model is proved. In addition, the impact of non-linear thermal properties of silicon on the thermal impedance of power semiconductors is shown.
{"title":"Transient non-linear thermal FEM simulation of smart power switches and verification by measurements","authors":"V. Kosel, R. Sleik, M. Glavanovics","doi":"10.1109/THERMINIC.2007.4451757","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451757","url":null,"abstract":"Thermal FEM (Finite Element Method) simulations can be used to predict the thermal behavior of power semiconductors in application. Most power semiconductors are made of silicon. Silicon thermal material properties are significantly temperature dependent. In this paper, validity of a common non-linear silicon material model is verified by transient non-linear thermal FEM simulations of Smart Power Switches and measurements. For verification, over-temperature protection behavior of Smart Power Switches is employed. This protection turns off the switch at a predefined temperature which is used as a temperature reference in the investigation. Power dissipation generated during a thermal overload event of two Smart Power devices is measured and used as an input stimulus to transient thermal FEM simulations. The duration time of the event together with the temperature reference is confronted with simulation results and thus the validity of the silicon model is proved. In addition, the impact of non-linear thermal properties of silicon on the thermal impedance of power semiconductors is shown.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133233045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451739
P. Szabó, M. Rencz
Thermal qualification of the die attach of semiconductor devices is a very important element in the device characterization as the temperature of the chip is strongly affected by the quality of the die attach. Voids or delaminations in this layer may cause higher temperature elevation and thus damage or shorter lifetime. Thermal test of each device in the manufacturing process would be the best solution for eliminating the devices with wrong die attach layer. In this paper we will present the short time thermal transient measurement method and the structure function evaluation through simulations and measurements for die attach characterization. We will also present a method for eliminating the very time consuming calibration process. Using the proposed methods even the in-line testing of LEDs can be accomplished.
{"title":"Short time die attach characterization of semiconductor devices","authors":"P. Szabó, M. Rencz","doi":"10.1109/THERMINIC.2007.4451739","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451739","url":null,"abstract":"Thermal qualification of the die attach of semiconductor devices is a very important element in the device characterization as the temperature of the chip is strongly affected by the quality of the die attach. Voids or delaminations in this layer may cause higher temperature elevation and thus damage or shorter lifetime. Thermal test of each device in the manufacturing process would be the best solution for eliminating the devices with wrong die attach layer. In this paper we will present the short time thermal transient measurement method and the structure function evaluation through simulations and measurements for die attach characterization. We will also present a method for eliminating the very time consuming calibration process. Using the proposed methods even the in-line testing of LEDs can be accomplished.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126169748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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