Pub Date : 2007-12-01DOI: 10.1109/THERMINIC.2007.4451781
Z. Szűcs, G. Nagy, S. Hodossy, M. Rencz, A. Poppe
In this paper vibration combined high temperature cycle tests for packaged capacitive SOI-MEMS accelerometers are presented. The aim of these tests is to provide useful Design for reliability information for MEMS designers. A high temperature test chamber and a chopper-stabilized read-out circuitry were designed and realized at BME-DED. Twenty thermal cycles of combined temperature cycle test and fatigue vibration test has been carried out on 5 samples. Statistical evaluation of the test results showed that degradation has started in 3 out of the 5 samples.
{"title":"Vibration combined high Temperature Cycle Tests for capacitive MEMS accelerometers","authors":"Z. Szűcs, G. Nagy, S. Hodossy, M. Rencz, A. Poppe","doi":"10.1109/THERMINIC.2007.4451781","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451781","url":null,"abstract":"In this paper vibration combined high temperature cycle tests for packaged capacitive SOI-MEMS accelerometers are presented. The aim of these tests is to provide useful Design for reliability information for MEMS designers. A high temperature test chamber and a chopper-stabilized read-out circuitry were designed and realized at BME-DED. Twenty thermal cycles of combined temperature cycle test and fatigue vibration test has been carried out on 5 samples. Statistical evaluation of the test results showed that degradation has started in 3 out of the 5 samples.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116259832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-01DOI: 10.1109/THERMINIC.2007.4451741
S. Kondo, Qiang Yu, T. Shibutani, M. Shiratori
As the integration and the miniaturization of electronics devices, design space become narrower and interactions between design factors affect their reliability. This paper presents a methodology of quantifying the interaction of each design factor in electronics devices. Thermal fatigue reliability of BGA assembly was assessed with the consideration of the interaction between design factors. Sensitivity analysis shows the influence of each design factor to inelastic strain range of a solder joint characterizing the thermal fatigue life if no interaction occurs. However, there is the interaction in BGA assembly since inelastic strain range depends on not only a mismatch in CTE but also a warpage of components. Clustering can help engineers to clarify the relation between design factors. The variation in the influence was taken to quantify the interaction of each design factor. Based on the interaction, simple evaluating approach of inelastic strain range for the BGA assembly was also developed. BGA package was simplified into a homogeneous component and equivalent CTE was calculated from the warpage of BGA and PCB. The estimated equation was derived by using the response surface method as a function of design factors. Based upon these analytical results, design engineers can rate each factor's effect on reliability and assess the reliability of their basic design plan at the concept design stage.
{"title":"New reliability assessment method for solder joints in BGA package by considering the interaction between design factors","authors":"S. Kondo, Qiang Yu, T. Shibutani, M. Shiratori","doi":"10.1109/THERMINIC.2007.4451741","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451741","url":null,"abstract":"As the integration and the miniaturization of electronics devices, design space become narrower and interactions between design factors affect their reliability. This paper presents a methodology of quantifying the interaction of each design factor in electronics devices. Thermal fatigue reliability of BGA assembly was assessed with the consideration of the interaction between design factors. Sensitivity analysis shows the influence of each design factor to inelastic strain range of a solder joint characterizing the thermal fatigue life if no interaction occurs. However, there is the interaction in BGA assembly since inelastic strain range depends on not only a mismatch in CTE but also a warpage of components. Clustering can help engineers to clarify the relation between design factors. The variation in the influence was taken to quantify the interaction of each design factor. Based on the interaction, simple evaluating approach of inelastic strain range for the BGA assembly was also developed. BGA package was simplified into a homogeneous component and equivalent CTE was calculated from the warpage of BGA and PCB. The estimated equation was derived by using the response surface method as a function of design factors. Based upon these analytical results, design engineers can rate each factor's effect on reliability and assess the reliability of their basic design plan at the concept design stage.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129156409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-01DOI: 10.1109/THERMINIC.2007.4451742
H. Miyauchi, Qiang Yu, T. Shibutani, M. Shiratori
Recently, the electronic device equipments using a lot of semiconductors are widespread to all industrial fields. Solder joints are used to mount the electronic chips, such as ceramic resistors and capacitors, on the printed-circuit boards in almost all electronic devices. However, since in many cases the thermal expansion coefficients of electronic parts and PCBs have mismatch, cyclic thermal stress and strain causes solder fatigue. Especially in the power electronic module and car electric module, the evaluation of thermal fatigue life for the chip components is important. It is understood that the fatigue lives of some electronic devices show big scatter in the thermal cycle test, even if their design is the same. The dispersion of main design factors of solder joints is thought as one of these reasons. Moreover, the influence of the dispersion grows when the lead-free solder materials are used in the devices. Therefore, it cannot be bypassed as the main issue for the reliability evaluation in the solder joints. In this study, how the dispersion of design factors and the interacting effect between the design factors influences the failure life in lead-free solder joint was investigated by the analytical approach. Sensitivity analyses were carried out to study the main effect of the dispersion of each factor on solder joints. And then, the interacting effect between the factors on the reliability was studied by considering the structural asymmetry due to the unbalanced solder joints. As a result, a practical evaluating technique for the failure life scatter of solder joints was proposed.
{"title":"Evaluation technique for the failure life scatter of lead-free solder joints in electronic device","authors":"H. Miyauchi, Qiang Yu, T. Shibutani, M. Shiratori","doi":"10.1109/THERMINIC.2007.4451742","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451742","url":null,"abstract":"Recently, the electronic device equipments using a lot of semiconductors are widespread to all industrial fields. Solder joints are used to mount the electronic chips, such as ceramic resistors and capacitors, on the printed-circuit boards in almost all electronic devices. However, since in many cases the thermal expansion coefficients of electronic parts and PCBs have mismatch, cyclic thermal stress and strain causes solder fatigue. Especially in the power electronic module and car electric module, the evaluation of thermal fatigue life for the chip components is important. It is understood that the fatigue lives of some electronic devices show big scatter in the thermal cycle test, even if their design is the same. The dispersion of main design factors of solder joints is thought as one of these reasons. Moreover, the influence of the dispersion grows when the lead-free solder materials are used in the devices. Therefore, it cannot be bypassed as the main issue for the reliability evaluation in the solder joints. In this study, how the dispersion of design factors and the interacting effect between the design factors influences the failure life in lead-free solder joint was investigated by the analytical approach. Sensitivity analyses were carried out to study the main effect of the dispersion of each factor on solder joints. And then, the interacting effect between the factors on the reliability was studied by considering the structural asymmetry due to the unbalanced solder joints. As a result, a practical evaluating technique for the failure life scatter of solder joints was proposed.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451756
B. Wunderle, T. Braun, D. May, A. mazloum, M. Bouazza, H. Walter, O. Wittier, R. Schacht, K. Becker, M. Schneider-Ramelow, B. Michel, H. Reichl
The use of multi-layer ceramic chip capacitors as integrated passive in e. g. system in package applications needs methods to examine and predict their reliability. Therefore, a nondestructive failure analytical technique is described to detect cracks in the ceramic and the metallic layers within encapsulated 0402 SMD capacitors. After choosing from techniques to reproducibly generate cracks, it is shown that an in-situ capacitance measurement is a convenient method to detect these failures unambiguously. Finite Element simulations support the experimental results. A reliability estimate for capacitor integrity under given loading conditions is given.
{"title":"Non-destructive failure analysis and modeling of encapsulated miniature SMD ceramic chip capacitors under thermal and mechanical loading","authors":"B. Wunderle, T. Braun, D. May, A. mazloum, M. Bouazza, H. Walter, O. Wittier, R. Schacht, K. Becker, M. Schneider-Ramelow, B. Michel, H. Reichl","doi":"10.1109/THERMINIC.2007.4451756","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451756","url":null,"abstract":"The use of multi-layer ceramic chip capacitors as integrated passive in e. g. system in package applications needs methods to examine and predict their reliability. Therefore, a nondestructive failure analytical technique is described to detect cracks in the ceramic and the metallic layers within encapsulated 0402 SMD capacitors. After choosing from techniques to reproducibly generate cracks, it is shown that an in-situ capacitance measurement is a convenient method to detect these failures unambiguously. Finite Element simulations support the experimental results. A reliability estimate for capacitor integrity under given loading conditions is given.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127438994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451768
D. May, Bernhard Wunderle, Florian Schindler-Saefkow, B. Nguyen, R. Schacht, Bruno Michel, Herbert Reichl
Prime concerns in designing liquid cooling solutions are performance, reliability and price. To that end a one-phase liquid cooling concept is proposed, where all pumps, valves and piping are fully integrated on board level. Only low-cost organic board technology and SMT processes are used in the design. This paper addresses the key issues of such a concept together with some numerical and first experimental results. It is highlighted that for such a concept a special type of membrane pump with adequate valve technology is especially suitable. Design guidelines as to its performance are given. Eventually, the obtained results are evaluated with respect to the requirements and necessary further developments are commented on to make the concept eligible for the cost-performance-sector.
{"title":"Fully integrated one phase liquid cooling system for organic boards","authors":"D. May, Bernhard Wunderle, Florian Schindler-Saefkow, B. Nguyen, R. Schacht, Bruno Michel, Herbert Reichl","doi":"10.1109/THERMINIC.2007.4451768","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451768","url":null,"abstract":"Prime concerns in designing liquid cooling solutions are performance, reliability and price. To that end a one-phase liquid cooling concept is proposed, where all pumps, valves and piping are fully integrated on board level. Only low-cost organic board technology and SMT processes are used in the design. This paper addresses the key issues of such a concept together with some numerical and first experimental results. It is highlighted that for such a concept a special type of membrane pump with adequate valve technology is especially suitable. Design guidelines as to its performance are given. Eventually, the obtained results are evaluated with respect to the requirements and necessary further developments are commented on to make the concept eligible for the cost-performance-sector.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125518596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451753
C. Yu, W. Wei, S.W. Kang
Micro Porosity Sintered wick is made from metal injection molding processes, which provides a wick density with micro scale. It can keep more than 53% working fluid inside the wick structure, and presents good pumping ability on working fluid transmission by fine infiltrated effect. Capillary pumping ability is the important factor in heat pipe design, and those general applications on wick structure are manufactured with groove type or screen type. Gravity affects capillary of these two types more than a sintered wick structure does, and mass heat transfer through vaporized working fluid determines the thermal performance of a vapor chamber. First of all, high density of porous wick supports high transmission ability of working fluid. The wick porosity is sintered in micro scale, which limits the bubble size while working fluid vaporizing on vapor section. Maximum heat transfer capacity increases dramatically as thermal resistance of wick decreases. This study on permeability design of wick structure is 0.5-0.7, especially permeability (R)=0.5 can have the best performance, and its heat conductivity is 20 times to a heat pipe with diameter (Phi)=10 mm. Test data of this vapor chamber shows thermal performance increases over 33 %.
{"title":"Investigation of micro porosity sintered wick in vapor chamber for fan less design","authors":"C. Yu, W. Wei, S.W. Kang","doi":"10.1109/THERMINIC.2007.4451753","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451753","url":null,"abstract":"Micro Porosity Sintered wick is made from metal injection molding processes, which provides a wick density with micro scale. It can keep more than 53% working fluid inside the wick structure, and presents good pumping ability on working fluid transmission by fine infiltrated effect. Capillary pumping ability is the important factor in heat pipe design, and those general applications on wick structure are manufactured with groove type or screen type. Gravity affects capillary of these two types more than a sintered wick structure does, and mass heat transfer through vaporized working fluid determines the thermal performance of a vapor chamber. First of all, high density of porous wick supports high transmission ability of working fluid. The wick porosity is sintered in micro scale, which limits the bubble size while working fluid vaporizing on vapor section. Maximum heat transfer capacity increases dramatically as thermal resistance of wick decreases. This study on permeability design of wick structure is 0.5-0.7, especially permeability (R)=0.5 can have the best performance, and its heat conductivity is 20 times to a heat pipe with diameter (Phi)=10 mm. Test data of this vapor chamber shows thermal performance increases over 33 %.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125559738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451766
W. Habra, P. Tounsi, F. Madrid, P. Dupuy, C. Barbot, J. Dorkel
An innovative and accurate dynamic compact thermal model extraction method is proposed for multi-chip power electronics systems. It accounts for thermal coupling between multiple heat sources. Transient electro-thermal coupling can easily be taken into account by system designers. The method is based on a definition of the optimal thermal coupling point, which is proven to be valid even for transient modelling. Compared to the existing methods, the number of needed 3D thermal simulations or measurements is significantly reduced.
{"title":"A new methodology for extraction of dynamic compact thermal models","authors":"W. Habra, P. Tounsi, F. Madrid, P. Dupuy, C. Barbot, J. Dorkel","doi":"10.1109/THERMINIC.2007.4451766","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451766","url":null,"abstract":"An innovative and accurate dynamic compact thermal model extraction method is proposed for multi-chip power electronics systems. It accounts for thermal coupling between multiple heat sources. Transient electro-thermal coupling can easily be taken into account by system designers. The method is based on a definition of the optimal thermal coupling point, which is proven to be valid even for transient modelling. Compared to the existing methods, the number of needed 3D thermal simulations or measurements is significantly reduced.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122750153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451749
H. Chen, L. Hsu, Xiaojin Wei
This paper describes a novel integrated circuit technology to manufacture high-density thermoelectric devices on a semiconductor wafer. With no moving parts, a thermoelectric cooler operates quietly, allows cooling below ambient temperature, and may be used for temperature control or heating if the direction of current flow is reversed. By using a monolithic process to increase the number of thermoelectric couples, the proposed solid-state cooling technology can be combined with traditional air cooling, liquid cooling, and phase-change cooling to yield greater heat flux and provide better cooling capability.
{"title":"A novel VLSI technology to manufacture high-density thermoelectric cooling devices","authors":"H. Chen, L. Hsu, Xiaojin Wei","doi":"10.1109/THERMINIC.2007.4451749","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451749","url":null,"abstract":"This paper describes a novel integrated circuit technology to manufacture high-density thermoelectric devices on a semiconductor wafer. With no moving parts, a thermoelectric cooler operates quietly, allows cooling below ambient temperature, and may be used for temperature control or heating if the direction of current flow is reversed. By using a monolithic process to increase the number of thermoelectric couples, the proposed solid-state cooling technology can be combined with traditional air cooling, liquid cooling, and phase-change cooling to yield greater heat flux and provide better cooling capability.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122835780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451769
D. Gerty, David W. Gerlach, Yogendra Joshi, Ari Glezer
A design for cooling 3D stacked chip electronics is proposed using solid heat spreaders of high thermal conductivity interleaved between the chip layers. The spreaders conduct heat to the base of an advanced synthetic jet cooled heat sink. A prior computational study showed that for moderate power dissipations, 5 W in each 27times38 mm layer, a 250 mum thick copper heat spreader would conduct heat adequately. However, the mismatch in coefficient of thermal expansion between copper and silicon required large holes through the copper layer for electrical vias. The current study investigates the design of a thermal prototype for experimental testing. Each active layer will incorporate a thermal test die to simulate an FPGA and a smaller one to simulate a DRAM. The spreader layer will be silicon with no via holes. The heat sink will contact only three of the stack sides to allow wirebond connections on the fourth side. The effect of the power dissipated and the heat transfer coefficient applied to the peripheral surface are studied. In order to remove the heat from the edges of a multi-layer stack and transfer it to the ambient air, a novel active heat sink design has been implemented using a matrix of integrated synthetic jets. In previous synthetic jet heat sink designs, cooling air is entrained upstream of the heat sink and is driven along the length of the fins. In the new design, synthetic jets emanate from the base of the fins so that the induced jets and entrained (cooling) ambient air flow along the fin height. The velocity field of the active heat sink is mapped using particle image velocimetry (PIV). Thermal performance is characterized using a surrogate heater and embedded thermocouple sensors. The thermal performance of identical heat sinks cooled by the two synthetic jet approaches is compared. An improved third heat sink solution is introduced and compared to previous results
{"title":"Development of a prototype thermal management solution for 3-D stacked chip electronics by interleaved solid spreaders and synthetic jets","authors":"D. Gerty, David W. Gerlach, Yogendra Joshi, Ari Glezer","doi":"10.1109/THERMINIC.2007.4451769","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451769","url":null,"abstract":"A design for cooling 3D stacked chip electronics is proposed using solid heat spreaders of high thermal conductivity interleaved between the chip layers. The spreaders conduct heat to the base of an advanced synthetic jet cooled heat sink. A prior computational study showed that for moderate power dissipations, 5 W in each 27times38 mm layer, a 250 mum thick copper heat spreader would conduct heat adequately. However, the mismatch in coefficient of thermal expansion between copper and silicon required large holes through the copper layer for electrical vias. The current study investigates the design of a thermal prototype for experimental testing. Each active layer will incorporate a thermal test die to simulate an FPGA and a smaller one to simulate a DRAM. The spreader layer will be silicon with no via holes. The heat sink will contact only three of the stack sides to allow wirebond connections on the fourth side. The effect of the power dissipated and the heat transfer coefficient applied to the peripheral surface are studied. In order to remove the heat from the edges of a multi-layer stack and transfer it to the ambient air, a novel active heat sink design has been implemented using a matrix of integrated synthetic jets. In previous synthetic jet heat sink designs, cooling air is entrained upstream of the heat sink and is driven along the length of the fins. In the new design, synthetic jets emanate from the base of the fins so that the induced jets and entrained (cooling) ambient air flow along the fin height. The velocity field of the active heat sink is mapped using particle image velocimetry (PIV). Thermal performance is characterized using a surrogate heater and embedded thermocouple sensors. The thermal performance of identical heat sinks cooled by the two synthetic jet approaches is compared. An improved third heat sink solution is introduced and compared to previous results","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114054143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-09-01DOI: 10.1109/THERMINIC.2007.4451782
W. Szczesniak
This paper presents a BPD (balanced power dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.
{"title":"Reducing average and peak temperatures of VLSI CMOS digital circuits by means of heuristic scheduling algorithm","authors":"W. Szczesniak","doi":"10.1109/THERMINIC.2007.4451782","DOIUrl":"https://doi.org/10.1109/THERMINIC.2007.4451782","url":null,"abstract":"This paper presents a BPD (balanced power dissipation) heuristic scheduling algorithm applied to VLSI CMOS digital circuits/systems in order to reduce the global computational demand and provide balanced power dissipation of computational units of the designed digital VLSI CMOS system during the task assignment stage. It results in reduction of the average and peak temperatures of VLSI CMOS digital circuits. The elaborated algorithm is based on balanced power dissipation of local computational (processing) units and does not deteriorate the throughput of the whole VLSI CMOS digital system.","PeriodicalId":264943,"journal":{"name":"2007 13th International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124008783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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