Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807914
S. Paul, B. Bandyopadhyay
Image compression is one of the most important step in image transmission and storage. Most of the state-of-art image compression techniques are spatial based. In this paper, a histogram based image compression technique is proposed based on multi-level image thresholding. The gray scale of the image is divided into crisp group of probabilistic partition. Shannon's Entropy is used to measure the randomness of the crisp grouping. The entropy function is maximized using a popular metaheuristic named Differential Evolution to reduce the computational time and standard deviation of optimized objective value. Some images from popular image database of UC Berkeley and CMU are used as benchmark images. Important image quality metrics-PSNR, WPSNR and storage size of the compressed image file are used for comparison and testing. Comparison of Shannon's entropy with Tsallis Entropy is also provided. Some specific applications of the proposed image compression algorithm are also pointed out.
{"title":"A novel approach for image compression based on multi-level image thresholding using Shannon Entropy and Differential Evolution","authors":"S. Paul, B. Bandyopadhyay","doi":"10.1109/TECHSYM.2014.6807914","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807914","url":null,"abstract":"Image compression is one of the most important step in image transmission and storage. Most of the state-of-art image compression techniques are spatial based. In this paper, a histogram based image compression technique is proposed based on multi-level image thresholding. The gray scale of the image is divided into crisp group of probabilistic partition. Shannon's Entropy is used to measure the randomness of the crisp grouping. The entropy function is maximized using a popular metaheuristic named Differential Evolution to reduce the computational time and standard deviation of optimized objective value. Some images from popular image database of UC Berkeley and CMU are used as benchmark images. Important image quality metrics-PSNR, WPSNR and storage size of the compressed image file are used for comparison and testing. Comparison of Shannon's entropy with Tsallis Entropy is also provided. Some specific applications of the proposed image compression algorithm are also pointed out.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125624268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807930
Ananya Mukherjee, S. K. Mandal, G. K. Mahanti, R. Ghatak
In this paper, sideband radiations which are generally regarded as the undesired effects of time-modulated antenna arrays (TMAAs), are exploited to design multi-beam antenna arrays. Time modulation (TM) is applied into uniformly excited linear array of half wave dipole radiators to generate low side-lobe sum and difference patterns at the center frequency and first sideband respectively while the maximum power level at the higher sidebands are suppressed significantly by optimizing the periodical on-off switching instants of the antenna elements by using fire-fly algorithm (FA). The FA optimized pattern as realized in MATLAB platform is validated by designing the uniformly excited time modulated linear array (UE-TMLA) in CST-MWS with the same on-time sequence as obtained by using FA and the patterns are compared.
{"title":"Synthesis of simultaneous sum and difference patterns in uniformly excited time-modulated linear arrays using firefly algorithm","authors":"Ananya Mukherjee, S. K. Mandal, G. K. Mahanti, R. Ghatak","doi":"10.1109/TECHSYM.2014.6807930","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807930","url":null,"abstract":"In this paper, sideband radiations which are generally regarded as the undesired effects of time-modulated antenna arrays (TMAAs), are exploited to design multi-beam antenna arrays. Time modulation (TM) is applied into uniformly excited linear array of half wave dipole radiators to generate low side-lobe sum and difference patterns at the center frequency and first sideband respectively while the maximum power level at the higher sidebands are suppressed significantly by optimizing the periodical on-off switching instants of the antenna elements by using fire-fly algorithm (FA). The FA optimized pattern as realized in MATLAB platform is validated by designing the uniformly excited time modulated linear array (UE-TMLA) in CST-MWS with the same on-time sequence as obtained by using FA and the patterns are compared.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"36 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116484147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1007/978-81-322-1817-3_36
Chandan Bandyopadhyay, S. Roy, L. Biswal, H. Rahaman
{"title":"Synthesis of ESOP-based reversible logic using negative polarity reed-muller form","authors":"Chandan Bandyopadhyay, S. Roy, L. Biswal, H. Rahaman","doi":"10.1007/978-81-322-1817-3_36","DOIUrl":"https://doi.org/10.1007/978-81-322-1817-3_36","url":null,"abstract":"","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"296 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116873913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808063
Gaurav Purohit, V. K. Chaubey, K. Raju, D. Vyas
This paper presents FPGA based implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions i.e. Walsh function. The paper further compares Parameterized `Serial In Serial Out' architectures based on classical counter approach. The investigation consider FPGA parameters like Area, Speed and Power and shows that using Gray-increment based architecture instead of Binary saves 6mW of power per symbol (64 Walsh chips per symbol) with 30% reduction in area. The design is implemented in VHDL code, simulated in MATLAB System Generator environment and validated with MATLAB Simulink Model. The design targeted Xilinx Virtex-5 “XC5VLX50T-1ff1136” FPGA device for the implementation and comparison. The design found their uses in many popular applications like Software Define Radio (SDR) including multiuser communications such as CDMA, WCDMA, VLSI testing, pattern recognition as well as image and signal processing.
本文提出了用一组正交函数即Walsh函数代替一般正弦余弦函数的FPGA实现理论。本文进一步比较了基于经典计数器方法的参数化“串行进串行出”体系结构。该研究考虑了FPGA的面积、速度和功耗等参数，结果表明，使用基于灰度增量的架构代替二进制，每个符号节省6mW的功耗(每个符号64个Walsh芯片)，面积减少30%。用VHDL代码实现了该设计，在MATLAB System Generator环境中进行了仿真，并用MATLAB Simulink模型进行了验证。本设计针对赛灵思Virtex-5“XC5VLX50T-1ff1136”FPGA器件进行了实现和比较。该设计在许多流行的应用中得到了应用，如软件定义无线电(SDR)，包括多用户通信，如CDMA, WCDMA, VLSI测试，模式识别以及图像和信号处理。
{"title":"FPGA based implementation & power analysis of parameterized Walsh sequences","authors":"Gaurav Purohit, V. K. Chaubey, K. Raju, D. Vyas","doi":"10.1109/TECHSYM.2014.6808063","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808063","url":null,"abstract":"This paper presents FPGA based implementation of the theory which replaces a general Sine and cosine function by set of orthogonal functions i.e. Walsh function. The paper further compares Parameterized `Serial In Serial Out' architectures based on classical counter approach. The investigation consider FPGA parameters like Area, Speed and Power and shows that using Gray-increment based architecture instead of Binary saves 6mW of power per symbol (64 Walsh chips per symbol) with 30% reduction in area. The design is implemented in VHDL code, simulated in MATLAB System Generator environment and validated with MATLAB Simulink Model. The design targeted Xilinx Virtex-5 “XC5VLX50T-1ff1136” FPGA device for the implementation and comparison. The design found their uses in many popular applications like Software Define Radio (SDR) including multiuser communications such as CDMA, WCDMA, VLSI testing, pattern recognition as well as image and signal processing.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121991520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807910
K. Sirisha, N. George
With an objective to improve the convergence characteristics of nonlinear active noise control (ANC) systems, this paper proposes a discrete cosine transform based adaptive algorithm for ANC. The performance of the new algorithm in terms of speed of convergence has been compared with that of the filtered-s least mean square algorithm. The improved convergence of the new algorithm is evident from the simulation experiments.
{"title":"Improving convergence of nonlinear active noise control systems","authors":"K. Sirisha, N. George","doi":"10.1109/TECHSYM.2014.6807910","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807910","url":null,"abstract":"With an objective to improve the convergence characteristics of nonlinear active noise control (ANC) systems, this paper proposes a discrete cosine transform based adaptive algorithm for ANC. The performance of the new algorithm in terms of speed of convergence has been compared with that of the filtered-s least mean square algorithm. The improved convergence of the new algorithm is evident from the simulation experiments.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"140 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113939807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807911
Dandu Sriram Raju, M. Manikandan, Ramkumar Barathram
In this paper, we present an automatic method for determining time-location of systolic peak in arterial blood pressure (ABP) signals. The method consists of four major steps: Gaussian derivative filtering, nonlinear peak amplification, Gaussian derivative based peak finding scheme, and peak position adjustment procedure. The method is tested and validated using the standard MIT-BIR Polysomnographic database containing a wide range of ABP signals, artifacts and high-frequency noises. Our results demonstrate that the proposed method can achieve better peak detection performance while maintaining very small detection error rates for both clean and noisy ABP signals. The method achieves an average sensitivity of 99.89% and positive predictivity of 99.59% on test ABP datasets consisting of 67,125 beats. Unlike other existing methods, our method is quite straightforward and simple in the sense that it does not use search-back algorithms with secondary thresholds.
{"title":"An automated method for detecting systolic peaks from arterial blood pressure signals","authors":"Dandu Sriram Raju, M. Manikandan, Ramkumar Barathram","doi":"10.1109/TECHSYM.2014.6807911","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807911","url":null,"abstract":"In this paper, we present an automatic method for determining time-location of systolic peak in arterial blood pressure (ABP) signals. The method consists of four major steps: Gaussian derivative filtering, nonlinear peak amplification, Gaussian derivative based peak finding scheme, and peak position adjustment procedure. The method is tested and validated using the standard MIT-BIR Polysomnographic database containing a wide range of ABP signals, artifacts and high-frequency noises. Our results demonstrate that the proposed method can achieve better peak detection performance while maintaining very small detection error rates for both clean and noisy ABP signals. The method achieves an average sensitivity of 99.89% and positive predictivity of 99.59% on test ABP datasets consisting of 67,125 beats. Unlike other existing methods, our method is quite straightforward and simple in the sense that it does not use search-back algorithms with secondary thresholds.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808042
P. M. Shereef, G. Shiny
A simplified space-vector pulse width modulation (SVPWM) scheme for any N-level inverter is presented. The method involves the conversion of space vector diagram of NN-level inverter to that of a 2-level inverter. 60° coordinate system is used to represent space vectors instead of using cartesian coordinate system. In 60° coordinate system only integer coordinates are involved. So the computational complexity is reduced. The proposed scheme is experimentally verified for a three level inverter realised by cascading two 2-level inverters.
{"title":"A simplified space vector PWM scheme for any N-level inverter","authors":"P. M. Shereef, G. Shiny","doi":"10.1109/TECHSYM.2014.6808042","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808042","url":null,"abstract":"A simplified space-vector pulse width modulation (SVPWM) scheme for any N-level inverter is presented. The method involves the conversion of space vector diagram of NN-level inverter to that of a 2-level inverter. 60° coordinate system is used to represent space vectors instead of using cartesian coordinate system. In 60° coordinate system only integer coordinates are involved. So the computational complexity is reduced. The proposed scheme is experimentally verified for a three level inverter realised by cascading two 2-level inverters.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125058189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808075
Rajendra Ku. Khadanga, J. K. Satapathy
This paper demonstrated an efficient approach for designing a static synchronous series compensator (SSSC)based supplementary controllers for damping low frequency oscillations. The SSSC is mainly GTO based which can control different parameters of power system. A supplementary damping controller for a SSSC is designed for power system dynamic performance enhancement. The lead-lag structure of damping controller is used for the damping of power system oscillation. The proposed controllers design problem is formulated as an optimization problem. The Gravitational Search Algorithm (GSA) is employed to optimize the damping controller parameters. To demonstrate the effectiveness of the proposed adaptive SSSC based supplementary damping controller, computer simulations are performed on a power system considering a single machine infinite bus installed with SSSC. The Simulation results are presented and these results are compared with a conventional method of tuning the damping controller parameters. This will analyze the effectiveness and robustness of the proposed design approach.
{"title":"Gravitational search algorithm for the static synchronous series compensator based damping controller design","authors":"Rajendra Ku. Khadanga, J. K. Satapathy","doi":"10.1109/TECHSYM.2014.6808075","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808075","url":null,"abstract":"This paper demonstrated an efficient approach for designing a static synchronous series compensator (SSSC)based supplementary controllers for damping low frequency oscillations. The SSSC is mainly GTO based which can control different parameters of power system. A supplementary damping controller for a SSSC is designed for power system dynamic performance enhancement. The lead-lag structure of damping controller is used for the damping of power system oscillation. The proposed controllers design problem is formulated as an optimization problem. The Gravitational Search Algorithm (GSA) is employed to optimize the damping controller parameters. To demonstrate the effectiveness of the proposed adaptive SSSC based supplementary damping controller, computer simulations are performed on a power system considering a single machine infinite bus installed with SSSC. The Simulation results are presented and these results are compared with a conventional method of tuning the damping controller parameters. This will analyze the effectiveness and robustness of the proposed design approach.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129382396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807932
Atin Mukherjee, A. Dhar
In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off between area overhead and number of faults tolerated. This paper presents fault tolerant architecture design for a ripple carry adder and a conditional sum adder as fast adder assuming single and double faults. The philosophy can be generalized for any other system which has structural regularity within it.
{"title":"Double-fault tolerant architecture design for digital adder","authors":"Atin Mukherjee, A. Dhar","doi":"10.1109/TECHSYM.2014.6807932","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807932","url":null,"abstract":"In the era of deep sub-micron technology, probability of chip failure has been increased with increase in chip density. A system must be fault tolerant to decrease the failure rate and increase the reliability of it. Multiple faults can affect a system simultaneously and there is a trade-off between area overhead and number of faults tolerated. This paper presents fault tolerant architecture design for a ripple carry adder and a conditional sum adder as fast adder assuming single and double faults. The philosophy can be generalized for any other system which has structural regularity within it.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127924820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807913
Soumyadeep Ghosh, Soumen Bag
Thinning which is an important preprocessing step for character recognition is often subject to several kinds of distortion. Junction point distortion is a major imperfection in thinned images especially for handwritten Indian scripts due to the presence of large number of complicated junctions in them. Such distortion does allow the optical character recognition (OCR) systems to exploit the properties of these junctions for character recognition. We present a novel methodology to reduce distortion at junction regions adjoining the matra for BangIa script. Our method uses geometric properties of the junctions to solve the problem. We have tested our approach on our own data set consisting of a variety of isolated handwritten character images by different writers and have got promising results.
{"title":"A modified thinning strategy to handle junction point distortion for Bangla characters","authors":"Soumyadeep Ghosh, Soumen Bag","doi":"10.1109/TECHSYM.2014.6807913","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807913","url":null,"abstract":"Thinning which is an important preprocessing step for character recognition is often subject to several kinds of distortion. Junction point distortion is a major imperfection in thinned images especially for handwritten Indian scripts due to the presence of large number of complicated junctions in them. Such distortion does allow the optical character recognition (OCR) systems to exploit the properties of these junctions for character recognition. We present a novel methodology to reduce distortion at junction regions adjoining the matra for BangIa script. Our method uses geometric properties of the junctions to solve the problem. We have tested our approach on our own data set consisting of a variety of isolated handwritten character images by different writers and have got promising results.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127911585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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