Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807927
Rajan Kapoor, S. Sundar, Preetam Kumar
The traditional model of DS-CDMA transmitter is not efficient when spreading codes are complex since complex multiplications needed for spreading would consume more power, require more area for implementation and incur more delays. In this paper, a novel architecture for DS-CDMA/CI transmitter is proposed which uses CORDIC algorithm to generate carrier whose phase offset is controlled by Carrier Interferometry (CI) codes. The architecture is based on the principle that product of two exponential is essentially an exponential with angle equal to sum of angle of product components. Furthermore, the architecture is reconfigurable in the sense that the spreading codes can be dynamically assigned during transmission and therefore can be used for designing communication systems for cognitive radio applications. The maximum frequency of operation was found to be 22 MHz from timing analysis results for given model for SPARTAN 3E FPGA.
传统的DS-CDMA发射机模型在传播码复杂的情况下效率不高，因为传播时需要进行复杂的乘法运算，会消耗更多的功率、占用更大的实现面积和产生更大的延迟。提出了一种新的DS-CDMA/CI发射机结构，利用CORDIC算法生成载波，载波的相位偏移由载波干涉码控制。该体系结构基于两个指数的乘积本质上是一个指数，其角度等于乘积分量的角度之和。此外，该体系结构是可重构的，即在传输过程中可以动态分配扩展码，因此可以用于设计认知无线电应用的通信系统。对给定型号的SPARTAN 3E FPGA进行时序分析，得到最大工作频率为22 MHz。
{"title":"CORDIC based reconfigurable architecture for DS-CDMA/CI transmitter","authors":"Rajan Kapoor, S. Sundar, Preetam Kumar","doi":"10.1109/TECHSYM.2014.6807927","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807927","url":null,"abstract":"The traditional model of DS-CDMA transmitter is not efficient when spreading codes are complex since complex multiplications needed for spreading would consume more power, require more area for implementation and incur more delays. In this paper, a novel architecture for DS-CDMA/CI transmitter is proposed which uses CORDIC algorithm to generate carrier whose phase offset is controlled by Carrier Interferometry (CI) codes. The architecture is based on the principle that product of two exponential is essentially an exponential with angle equal to sum of angle of product components. Furthermore, the architecture is reconfigurable in the sense that the spreading codes can be dynamically assigned during transmission and therefore can be used for designing communication systems for cognitive radio applications. The maximum frequency of operation was found to be 22 MHz from timing analysis results for given model for SPARTAN 3E FPGA.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121770103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808068
L. Tripathy, M. K. Jena, S. Samantaray, D. Dash
In this paper the authors suggest a novel protection scheme for a tapped transmission line connected to wind-farm in presence of UPFC. The powerful analyzing and decomposing features of Wavelet Transform(WT) along with the accurate phasor extraction feature of Discrete Fourier Transform(DFT) has been combined to develop this useful and effective protection scheme. The whole idea of the proposed scheme is to extract third level decomposed current signals at each substation using Wavelet Transform. Then third level approximate coefficients(CA3) are reconstructed for each line current at every substation to derive operating and restraining quantities after extracting the respective fundamental phasors by using DFT. The proposed scheme has been tested on a 500 kV, teed-transmission line in the presence of UPFC and Wind Farm (as one of the substation) under various fault and operating conditions on MATLAB environment. The results given in section-V shows the feasibility of the proposed relaying scheme. To compare effectiveness of the proposed differential relaying scheme along with the conventional relaying scheme, different types of faults have been simulated at different location of the transmission line by considering three statistical metrics (i.e Dependability, Security and Yield) and result has been compared and shown in table-1.
{"title":"A differential protection scheme for tapped transmission line containing UPFC and wind farm","authors":"L. Tripathy, M. K. Jena, S. Samantaray, D. Dash","doi":"10.1109/TECHSYM.2014.6808068","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808068","url":null,"abstract":"In this paper the authors suggest a novel protection scheme for a tapped transmission line connected to wind-farm in presence of UPFC. The powerful analyzing and decomposing features of Wavelet Transform(WT) along with the accurate phasor extraction feature of Discrete Fourier Transform(DFT) has been combined to develop this useful and effective protection scheme. The whole idea of the proposed scheme is to extract third level decomposed current signals at each substation using Wavelet Transform. Then third level approximate coefficients(CA3) are reconstructed for each line current at every substation to derive operating and restraining quantities after extracting the respective fundamental phasors by using DFT. The proposed scheme has been tested on a 500 kV, teed-transmission line in the presence of UPFC and Wind Farm (as one of the substation) under various fault and operating conditions on MATLAB environment. The results given in section-V shows the feasibility of the proposed relaying scheme. To compare effectiveness of the proposed differential relaying scheme along with the conventional relaying scheme, different types of faults have been simulated at different location of the transmission line by considering three statistical metrics (i.e Dependability, Security and Yield) and result has been compared and shown in table-1.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129673989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808071
B. Pradhan, B. Gupta
A novel tunable band reject filter is designed and simulated using metamaterials and RF MEMS technology. CSRR on CPW line are used to achieve filter characteristics, while tunability is ensured through incorporation of a MEMS variable capacitor, enabling compatibility with planar IC technology. The CSRRs are etched on both the signal line and ground planes of the CPW with different CSRR structures. Tunability of the band reject filter is achieved by putting the MEMS bridge in either up or down state. The designed band stop filter rejection of stop bands are around -19.87 dB for down state around the centre frequency 29.719GHz and -17.96dB for up state around the centre frequency 33.172GHz. The proposed device structure is simulated using ANSOFT HFSS v13® for RF analysis.
{"title":"Novel tunable band reject filter using RF MEMS technology","authors":"B. Pradhan, B. Gupta","doi":"10.1109/TECHSYM.2014.6808071","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808071","url":null,"abstract":"A novel tunable band reject filter is designed and simulated using metamaterials and RF MEMS technology. CSRR on CPW line are used to achieve filter characteristics, while tunability is ensured through incorporation of a MEMS variable capacitor, enabling compatibility with planar IC technology. The CSRRs are etched on both the signal line and ground planes of the CPW with different CSRR structures. Tunability of the band reject filter is achieved by putting the MEMS bridge in either up or down state. The designed band stop filter rejection of stop bands are around -19.87 dB for down state around the centre frequency 29.719GHz and -17.96dB for up state around the centre frequency 33.172GHz. The proposed device structure is simulated using ANSOFT HFSS v13® for RF analysis.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131716731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807907
Manjira Sinha, Tirthankar Dasgupta, Surabhi Agrawal, Sneha S. Jain, Nidhi Bagaria, A. Basu
In this paper we present an open framework that can be used to develop applications related to entertainment and social interaction in order to improve the QoL of people with Cerebral Palsy. The framework targets to provide easy access to different entertainment mediums like, reading book, listening to music, watching videos, and accessing social network sites like Facebook and Gmail. People with CP lack motor control that causes full or partial malfunctioning of body parts responsible for generating speech and limb movements. This restricts them to use standard computer peripherals like, keyboard and mouse. The proposed framework is integrated with an easily accessible auto scanning mechanisms that helps people with motor disorders to access computer applications. We have evaluated the system with a set of six CP patients. Our initial evaluation results revealed that the proposed system is increasingly becoming popular among the target population.
{"title":"Development of entertainment and social interaction applications to improve Quality of Life (QoL) of people with Cerebral Palsy","authors":"Manjira Sinha, Tirthankar Dasgupta, Surabhi Agrawal, Sneha S. Jain, Nidhi Bagaria, A. Basu","doi":"10.1109/TECHSYM.2014.6807907","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807907","url":null,"abstract":"In this paper we present an open framework that can be used to develop applications related to entertainment and social interaction in order to improve the QoL of people with Cerebral Palsy. The framework targets to provide easy access to different entertainment mediums like, reading book, listening to music, watching videos, and accessing social network sites like Facebook and Gmail. People with CP lack motor control that causes full or partial malfunctioning of body parts responsible for generating speech and limb movements. This restricts them to use standard computer peripherals like, keyboard and mouse. The proposed framework is integrated with an easily accessible auto scanning mechanisms that helps people with motor disorders to access computer applications. We have evaluated the system with a set of six CP patients. Our initial evaluation results revealed that the proposed system is increasingly becoming popular among the target population.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132179343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808070
A. Goyal, K. Singh, S. Singh
In this paper, an ultra-thin LC resonator structure operating in X-band is designed which is intended to be used as a shield to reduce the radar cross section of a conducting plate. The proposed structure is simulated using Ansoft HFSS software which shows an absorption peak at 8.125 GHz with reflection coefficient of -34.2 dB. The LC structure constructed from resistive/low conductivity material is backed by a grounded foam material. The results show that the proposed absorber offers reduction in radar cross section (RCS) for the conducting plate over the frequency range 7.38-9.45 GHz. Moreover, the structure has the thickness of 3 mm which is only 0.0738λ and 0.0945λ at the lowest and highest frequencies respectively. The real and imaginary parts of the normalized impedance are unity and zero respectively at the resonant frequency. We can shift the absorption frequencies by varying the gap as well as length-segment of the Meander line structure.
{"title":"An ultra-thin LC resonator structure for radar cross section reduction","authors":"A. Goyal, K. Singh, S. Singh","doi":"10.1109/TECHSYM.2014.6808070","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808070","url":null,"abstract":"In this paper, an ultra-thin LC resonator structure operating in X-band is designed which is intended to be used as a shield to reduce the radar cross section of a conducting plate. The proposed structure is simulated using Ansoft HFSS software which shows an absorption peak at 8.125 GHz with reflection coefficient of -34.2 dB. The LC structure constructed from resistive/low conductivity material is backed by a grounded foam material. The results show that the proposed absorber offers reduction in radar cross section (RCS) for the conducting plate over the frequency range 7.38-9.45 GHz. Moreover, the structure has the thickness of 3 mm which is only 0.0738λ and 0.0945λ at the lowest and highest frequencies respectively. The real and imaginary parts of the normalized impedance are unity and zero respectively at the resonant frequency. We can shift the absorption frequencies by varying the gap as well as length-segment of the Meander line structure.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117338327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808060
Bibek Kabi, Ramanarayan Mohanty, Subhasmita Sahoo, A. Routray
Predominantly all signal processing algorithms are developed with floating-point arithmetic. However for low power and real-time applications they are finally implemented on embedded systems with fixed-point arithmetic. Implementation of signal processing algorithm in fixed-point arithmetic involves a floating-point to fixed-point conversion process. Wordlength optimization plays a significant role in this conversion process, reducing area, power and latency while maintaining the accuracy constraint. Simulation and analytical approaches are two techniques used for optimizing the wordlengths. In simulation based approach a new fixed-point simulation is required to run for every modified wordlength. Bit true (fixed-point) simulations are not necessary to run for analytical based wordlength optimization methods. Therefore this approach requires the derivation of the cost model and the performance (signal to quantization noise ratio) as a function of wordlengths of different variables of the algorithm. Hence in this paper we have carried out a detailed study on the derivation of the cost model for fixed-point FFT algorithm. Cost models under various quantization modes are discussed and compared.
{"title":"An analytical framework for area and switching power optimization of a fixed-point FFT algorithm","authors":"Bibek Kabi, Ramanarayan Mohanty, Subhasmita Sahoo, A. Routray","doi":"10.1109/TECHSYM.2014.6808060","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808060","url":null,"abstract":"Predominantly all signal processing algorithms are developed with floating-point arithmetic. However for low power and real-time applications they are finally implemented on embedded systems with fixed-point arithmetic. Implementation of signal processing algorithm in fixed-point arithmetic involves a floating-point to fixed-point conversion process. Wordlength optimization plays a significant role in this conversion process, reducing area, power and latency while maintaining the accuracy constraint. Simulation and analytical approaches are two techniques used for optimizing the wordlengths. In simulation based approach a new fixed-point simulation is required to run for every modified wordlength. Bit true (fixed-point) simulations are not necessary to run for analytical based wordlength optimization methods. Therefore this approach requires the derivation of the cost model and the performance (signal to quantization noise ratio) as a function of wordlengths of different variables of the algorithm. Hence in this paper we have carried out a detailed study on the derivation of the cost model for fixed-point FFT algorithm. Cost models under various quantization modes are discussed and compared.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115299022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807923
Subhajit Das, S. Bhattacharya, Debaprasad Das, H. Rahaman
The work in this paper presents analysis of graphene nanoribbon (GNR) as nano-interconnect for radio-frequency (RF) VLSI circuits for 16 nm technology node. A frequency dependent electrical equivalent model is developed by calculating the circuit parameters based on interconnect geometry. Using the developed model the RF performance of GNR based interconnects is investigated and compared to that of copper based interconnects for 16 nm technology node. It is shown that GNR based interconnect shows better performance for operating in and beyond 1000 THz frequency range for shorter interconnect length.
{"title":"RF performance analysis of graphene nanoribbon interconnect","authors":"Subhajit Das, S. Bhattacharya, Debaprasad Das, H. Rahaman","doi":"10.1109/TECHSYM.2014.6807923","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807923","url":null,"abstract":"The work in this paper presents analysis of graphene nanoribbon (GNR) as nano-interconnect for radio-frequency (RF) VLSI circuits for 16 nm technology node. A frequency dependent electrical equivalent model is developed by calculating the circuit parameters based on interconnect geometry. Using the developed model the RF performance of GNR based interconnects is investigated and compared to that of copper based interconnects for 16 nm technology node. It is shown that GNR based interconnect shows better performance for operating in and beyond 1000 THz frequency range for shorter interconnect length.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115750052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808086
Jyotirmayee Dalei, K. Mohanty
This paper derives the mathematical expression for the minimum excitation capacitance of self excited induction generator under different types of load and speed, and also studies the performance of a self-excited induction generator (SEIG) driven by a prime mover. Mathematical model of the isolated SEIG under balanced loading conditions in d-q stationary reference frame is developed to study the behavior of the system. The developed mathematical model is validated by comparing simulation and experimental results at no load and for balanced load cases.
{"title":"A novel method to determine minimum capacitance of the self-excited induction generator","authors":"Jyotirmayee Dalei, K. Mohanty","doi":"10.1109/TECHSYM.2014.6808086","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808086","url":null,"abstract":"This paper derives the mathematical expression for the minimum excitation capacitance of self excited induction generator under different types of load and speed, and also studies the performance of a self-excited induction generator (SEIG) driven by a prime mover. Mathematical model of the isolated SEIG under balanced loading conditions in d-q stationary reference frame is developed to study the behavior of the system. The developed mathematical model is validated by comparing simulation and experimental results at no load and for balanced load cases.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127595861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6808040
S. Kundu, P. Mandal
This paper presents an efficient approach to model Phase Margin (PM) of high performance amplifiers. In this approach, effects of higher order poles and zeros are modeled into an equivalent secondary pole, referred as Effective Second Pole (ESP). The notion of ESP is very useful, particularly, for designing a high bandwidth amplifier where a number of parasitic poles and zeros simultaneously influence the phase margin. Moreover, a model of the ESP can be developed empirically without tracking the relative positions of poles and zeros across different corners of the design of experiments. Effectiveness of the empirically modeled ESP has been demonstrated by sizing two high performance CMOS amplifiers and comparing the predicted results (using the proposed models) to those obtained from transistor level simulations using SPICE.
{"title":"A generic and efficient modeling of phase margin of high performance CMOS OpAmps","authors":"S. Kundu, P. Mandal","doi":"10.1109/TECHSYM.2014.6808040","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6808040","url":null,"abstract":"This paper presents an efficient approach to model Phase Margin (PM) of high performance amplifiers. In this approach, effects of higher order poles and zeros are modeled into an equivalent secondary pole, referred as Effective Second Pole (ESP). The notion of ESP is very useful, particularly, for designing a high bandwidth amplifier where a number of parasitic poles and zeros simultaneously influence the phase margin. Moreover, a model of the ESP can be developed empirically without tracking the relative positions of poles and zeros across different corners of the design of experiments. Effectiveness of the empirically modeled ESP has been demonstrated by sizing two high performance CMOS amplifiers and comparing the predicted results (using the proposed models) to those obtained from transistor level simulations using SPICE.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121826258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-05-01DOI: 10.1109/TECHSYM.2014.6807916
Vijay Kumar, S. Sengupta
In this paper, we propose the Side Information refinement scheme for the Transform Domain Wyner-Ziv video codec. As the quality of Side Information affects the Rate-Distortion performance of the Wyner-Ziv coding scheme, recent schemes are based on the refinement of the Side Information in the Wyner-Ziv decoding loop to improve the Rate-Distortion performance. But the schemes are not competitive compared to the low complexity conventional coding schemes(H.264 intra and zero motion codecs) and the conventional H.264 inter coding schemes. As the codec requires huge bit rate to decode the DC band using the initial motion compensated temporal interpolated Side Information, we propose the scheme, by forming the layers with in the DC band and Side Information refinement is applied after decoding coefficients in each layer. The proposed scheme improves the Rate-Distortion performance and results in the WZ bit rate savings upto 7.78 % compared to the recent schemes.
{"title":"Side information refinement scheme in Transform Domain Distributed Video Coding","authors":"Vijay Kumar, S. Sengupta","doi":"10.1109/TECHSYM.2014.6807916","DOIUrl":"https://doi.org/10.1109/TECHSYM.2014.6807916","url":null,"abstract":"In this paper, we propose the Side Information refinement scheme for the Transform Domain Wyner-Ziv video codec. As the quality of Side Information affects the Rate-Distortion performance of the Wyner-Ziv coding scheme, recent schemes are based on the refinement of the Side Information in the Wyner-Ziv decoding loop to improve the Rate-Distortion performance. But the schemes are not competitive compared to the low complexity conventional coding schemes(H.264 intra and zero motion codecs) and the conventional H.264 inter coding schemes. As the codec requires huge bit rate to decode the DC band using the initial motion compensated temporal interpolated Side Information, we propose the scheme, by forming the layers with in the DC band and Side Information refinement is applied after decoding coefficients in each layer. The proposed scheme improves the Rate-Distortion performance and results in the WZ bit rate savings upto 7.78 % compared to the recent schemes.","PeriodicalId":265072,"journal":{"name":"Proceedings of the 2014 IEEE Students' Technology Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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