Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411173
Jacob A. Bower
This project covers the development of a self-contained 'system-on-a-chip' (SoC) design which allows the lossy compression of digital audio data. Primarily, this is achieved by the creation of a general purpose extensible SoC framework, based around an off-the-shelf central processing unit (CPU) core. The framework allows extension of the CPU by adding custom instructions and data processors which are supported by a collection of customisable fractional arithmetic units. The goal of this design is to allow easy and rapid exploration of the hardware design space when running and accelerating the open-source 'Ogg Vorbis' audio encoding algorithm. By creating custom acceleration hardware using the framework, a speed increase of around 33%, compared to an unmodified refence encoder, is achieved in an FPGA prototype implementation. This project is the only work we are aware of so far that considers the use of 'Ogg Vorbis' for encoding in an embedded system.
{"title":"A system-on-a-chip for audio encoding","authors":"Jacob A. Bower","doi":"10.1109/ISSOC.2004.1411173","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411173","url":null,"abstract":"This project covers the development of a self-contained 'system-on-a-chip' (SoC) design which allows the lossy compression of digital audio data. Primarily, this is achieved by the creation of a general purpose extensible SoC framework, based around an off-the-shelf central processing unit (CPU) core. The framework allows extension of the CPU by adding custom instructions and data processors which are supported by a collection of customisable fractional arithmetic units. The goal of this design is to allow easy and rapid exploration of the hardware design space when running and accelerating the open-source 'Ogg Vorbis' audio encoding algorithm. By creating custom acceleration hardware using the framework, a speed increase of around 33%, compared to an unmodified refence encoder, is achieved in an FPGA prototype implementation. This project is the only work we are aware of so far that considers the use of 'Ogg Vorbis' for encoding in an embedded system.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114957485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411131
P. Metzgen
Summary form only given. Altera's SOPC Builder Tool enables engineers to create tailor-made systems in an FPGA with a short development cycle; one of the most popular components in SOPC Builder is Altera's NIOS II processor. As well as ease of use and flexibility, the NIOS II family of processors offers up to 200 DMIPs of performance and can cost as little as 35 cents worth of programmable logic. This high level of performance has been achieved by tailoring the processor architecture to fully exploit the FPGA resources used. Logic, registers, memory, and multipliers have different relative costs in an FPGA when compared to an ASIC; in an FPGA, registers and memories are relatively cheap, whereas logic and in particular, the implementation of multiplexers can be of relatively high cost. These cost differences have an influence on how engineers should design for FPGAs, and defined the design of NIOS II at the architectural level. This paper presents some novel techniques for implementing multiplexers and barrel-shifters efficiently, using the NIOS II processor as an example. These techniques are useful for improving FPGA designs in general, and have typically lead to area reductions and performance improvements of 20%.
{"title":"Optimizing a high performance 32-bit processor for programmable logic","authors":"P. Metzgen","doi":"10.1109/ISSOC.2004.1411131","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411131","url":null,"abstract":"Summary form only given. Altera's SOPC Builder Tool enables engineers to create tailor-made systems in an FPGA with a short development cycle; one of the most popular components in SOPC Builder is Altera's NIOS II processor. As well as ease of use and flexibility, the NIOS II family of processors offers up to 200 DMIPs of performance and can cost as little as 35 cents worth of programmable logic. This high level of performance has been achieved by tailoring the processor architecture to fully exploit the FPGA resources used. Logic, registers, memory, and multipliers have different relative costs in an FPGA when compared to an ASIC; in an FPGA, registers and memories are relatively cheap, whereas logic and in particular, the implementation of multiplexers can be of relatively high cost. These cost differences have an influence on how engineers should design for FPGAs, and defined the design of NIOS II at the architectural level. This paper presents some novel techniques for implementing multiplexers and barrel-shifters efficiently, using the NIOS II processor as an example. These techniques are useful for improving FPGA designs in general, and have typically lead to area reductions and performance improvements of 20%.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128270129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411177
Iosif Antochi, B. Juurlink, S. Vassiliadis, P. Liuha
Tile-based rendering appears to be a promising technique for low-cost, low-power 3D graphics platforms. This technique decomposes a scene into tiles and renders the tiles independently. It requires, however, that the primitives are sorted into bins that correspond to the tiles, which can be very time-consuming and may require a lot of memory bandwidth. The most often used test to determine if a primitive and a tile overlap is the bounding box test. This test checks if the 2D axis aligned bounding box of the primitive overlaps the tile and comprises four comparisons in the worst case. In this paper, we show that the efficiency of the bounding box test can be improved significantly by adaptively varying the order in which the comparisons are performed, depending on the position of the current tile. Experimental results obtained using several 3D graphics workloads show that the dynamic bounding box test reduces the average number of comparisons per primitive by 26% on average compared to the best performing static version in which the order of the comparisons is fixed.
{"title":"Efficient tile-aware bounding-box overlap test for tile-based rendering","authors":"Iosif Antochi, B. Juurlink, S. Vassiliadis, P. Liuha","doi":"10.1109/ISSOC.2004.1411177","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411177","url":null,"abstract":"Tile-based rendering appears to be a promising technique for low-cost, low-power 3D graphics platforms. This technique decomposes a scene into tiles and renders the tiles independently. It requires, however, that the primitives are sorted into bins that correspond to the tiles, which can be very time-consuming and may require a lot of memory bandwidth. The most often used test to determine if a primitive and a tile overlap is the bounding box test. This test checks if the 2D axis aligned bounding box of the primitive overlaps the tile and comprises four comparisons in the worst case. In this paper, we show that the efficiency of the bounding box test can be improved significantly by adaptively varying the order in which the comparisons are performed, depending on the position of the current tile. Experimental results obtained using several 3D graphics workloads show that the dynamic bounding box test reduces the average number of comparisons per primitive by 26% on average compared to the best performing static version in which the order of the comparisons is fixed.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125069367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411171
Chun-Yen Chang
Summary form only given. Over the past 20 years, Taiwan's private and public sectors have joined hands to establish a highly efficient electronics manufacturing environment with global logistics capabilities. The semiconductor industry enjoys a worldwide reputation as one of the most dynamic locations for electronics innovation and service provision. To continue her crucial role in the worldwide semiconductor industry, yet evolve from a capital intensive to knowledge intensive industry, Taiwan has set up a National SoC Program (NSoC) to coordinate efforts from private and public sectors. In this presentation, we outline the theme, the approaches, and the achievement of the 1st phase NSoC program, from 2003 to 2005. In addition, the planning for the 2nd phase is revealed.
{"title":"Development of NSoC program in Taiwan","authors":"Chun-Yen Chang","doi":"10.1109/ISSOC.2004.1411171","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411171","url":null,"abstract":"Summary form only given. Over the past 20 years, Taiwan's private and public sectors have joined hands to establish a highly efficient electronics manufacturing environment with global logistics capabilities. The semiconductor industry enjoys a worldwide reputation as one of the most dynamic locations for electronics innovation and service provision. To continue her crucial role in the worldwide semiconductor industry, yet evolve from a capital intensive to knowledge intensive industry, Taiwan has set up a National SoC Program (NSoC) to coordinate efforts from private and public sectors. In this presentation, we outline the theme, the approaches, and the achievement of the 1st phase NSoC program, from 2003 to 2005. In addition, the planning for the 2nd phase is revealed.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114172529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411184
J. Plosila, P. Liljeberg, J. Isoaho
We present a formal systematic approach to model and stepwise refine on-chip communication channels. The approach is based on the formal framework of action systems. We show how an abstract channel, modeled as a remote procedure, is first refined into an intermediate form and then further into a concrete implementable model based on boolean communication variables.
{"title":"Refinement of on-chip communication channels","authors":"J. Plosila, P. Liljeberg, J. Isoaho","doi":"10.1109/ISSOC.2004.1411184","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411184","url":null,"abstract":"We present a formal systematic approach to model and stepwise refine on-chip communication channels. The approach is based on the formal framework of action systems. We show how an abstract channel, modeled as a remote procedure, is first refined into an intermediate form and then further into a concrete implementable model based on boolean communication variables.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123532432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411183
R. Pelliconi, F. Campi, L. Salsa, C. Mucci, S. Macchiavelli
A fundamental feature common to all SOC projects is the inclusion of one or more embedded microprocessors in the design space. As the complexity of algorithms mapped on embedded processors and their interaction with the surrounding SOC resources increase, the availability of reliable software verification means becomes a serious design issue, especially when more than one processor is included in the design. Many existing processor-debugger interfaces are based on specific technology or architectural features such as JTAG interfaces or scan-chains. On the other hand, embedded microprocessor cores are often HDL suites, quite parametric and technology independent, and need to be reused in a very different design environment. In this paper, an in-circuit software debug environment is presented, that can be utilized for single- or multi-processor SOCs. The described methodology, only based on VHDL blocks and software routines, is independent from the chosen technology support, and processor memory or bus architecture configuration.
{"title":"An in-circuit debug environment for multiprocessor SOCs based on a HDL RISC soft-core","authors":"R. Pelliconi, F. Campi, L. Salsa, C. Mucci, S. Macchiavelli","doi":"10.1109/ISSOC.2004.1411183","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411183","url":null,"abstract":"A fundamental feature common to all SOC projects is the inclusion of one or more embedded microprocessors in the design space. As the complexity of algorithms mapped on embedded processors and their interaction with the surrounding SOC resources increase, the availability of reliable software verification means becomes a serious design issue, especially when more than one processor is included in the design. Many existing processor-debugger interfaces are based on specific technology or architectural features such as JTAG interfaces or scan-chains. On the other hand, embedded microprocessor cores are often HDL suites, quite parametric and technology independent, and need to be reused in a very different design environment. In this paper, an in-circuit software debug environment is presented, that can be utilized for single- or multi-processor SOCs. The described methodology, only based on VHDL blocks and software routines, is independent from the chosen technology support, and processor memory or bus architecture configuration.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124985985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411149
E. Salminen, Kimmo Kuusilinna, T. Hämäläinen
This work presents a brief comparison of both academic and commercial intellectual property (IP) components. The aim is to gain insight to contemporary IP components regarding their application domains and cost in terms of area and energy. It has been estimated that in the future the maximum size of components must be in the range of 50-100 kilogates. According to this study, contemporary IP components mostly conform to this size limit. Selecting the most appropriate IP candidates is crucial for successful SoC design. However, IP comparison and selection is hard since even basic information is often missing.
{"title":"Comparison of hardware IP components for system-on-chip","authors":"E. Salminen, Kimmo Kuusilinna, T. Hämäläinen","doi":"10.1109/ISSOC.2004.1411149","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411149","url":null,"abstract":"This work presents a brief comparison of both academic and commercial intellectual property (IP) components. The aim is to gain insight to contemporary IP components regarding their application domains and cost in terms of area and energy. It has been estimated that in the future the maximum size of components must be in the range of 50-100 kilogates. According to this study, contemporary IP components mostly conform to this size limit. Selecting the most appropriate IP candidates is crucial for successful SoC design. However, IP comparison and selection is hard since even basic information is often missing.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131201949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411157
F. Dielacher
Summary form only given. Decreasing feature size and increasing system complexity enables to map complex systems onto one die (SoC - system on chip) or into one package (SiP - system in package). This reduces development, production and packaging costs of the integrated circuit, increases integration density of the customer products by consuming less board space and optimizes the bill of material by reducing the number of external components. This paper looks at the design challenges posed by broadband transceiver design, including hardware/software reuse, validation and verification effort, and platform design, using the context of the SoC-Mobinet research project.
{"title":"SoC-Mobinet: broadband transceiver design challenges","authors":"F. Dielacher","doi":"10.1109/ISSOC.2004.1411157","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411157","url":null,"abstract":"Summary form only given. Decreasing feature size and increasing system complexity enables to map complex systems onto one die (SoC - system on chip) or into one package (SiP - system in package). This reduces development, production and packaging costs of the integrated circuit, increases integration density of the customer products by consuming less board space and optimizes the bill of material by reducing the number of external components. This paper looks at the design challenges posed by broadband transceiver design, including hardware/software reuse, validation and verification effort, and platform design, using the context of the SoC-Mobinet research project.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133135203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411050
H. Meyr
Summary form only given. The next generation of wireless communication systems will be cognitive to efficiently use the available bandwidth. For a given criterion, these systems will adaptively select the transmission method, protocol and the services which are optimal at any given time. Sophisticated signal processing algorithms of ultra high complexity must be executed to perform this adaptation. To meet conflicting goals such as energy efficiency and flexibility together with cost, time-to-market and reusability constraints a radically different, truly innovative architectural approach is necessary for SoCs applied to wireless communications. These future SoCs can be viewed as heterogeneous multiprocessor systems (MP-SoC). They will contain an increasing number of application specific instruction-set processors (ASIPs) combined with complex memory hierarchies and on-chip communication networks (NoC). The success of the proposed MP-SoC is ultimately linked to the availability of an equally innovative system-level design (SLD) methodology together with the corresponding SLD tool suite. In this presentation, we address this innovative SLD design flow in the context of wireless communications. The focus of this presentation is primarily on one crucial aspect of this process: the spatial mapping of application tasks onto ASIPs.
{"title":"Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility","authors":"H. Meyr","doi":"10.1109/ISSOC.2004.1411050","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411050","url":null,"abstract":"Summary form only given. The next generation of wireless communication systems will be cognitive to efficiently use the available bandwidth. For a given criterion, these systems will adaptively select the transmission method, protocol and the services which are optimal at any given time. Sophisticated signal processing algorithms of ultra high complexity must be executed to perform this adaptation. To meet conflicting goals such as energy efficiency and flexibility together with cost, time-to-market and reusability constraints a radically different, truly innovative architectural approach is necessary for SoCs applied to wireless communications. These future SoCs can be viewed as heterogeneous multiprocessor systems (MP-SoC). They will contain an increasing number of application specific instruction-set processors (ASIPs) combined with complex memory hierarchies and on-chip communication networks (NoC). The success of the proposed MP-SoC is ultimately linked to the availability of an equally innovative system-level design (SLD) methodology together with the corresponding SLD tool suite. In this presentation, we address this innovative SLD design flow in the context of wireless communications. The focus of this presentation is primarily on one crucial aspect of this process: the spatial mapping of application tasks onto ASIPs.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124733974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411176
H. Kadim
In analogue circuits, parameter fluctuations trigger variations in functional behaviour. However, such fluctuations may not result in faulty behaviour and, hence, the circuit may still function satisfactorily. Therefore, it is necessary to estimate a maximum bound of fluctuations that retains satisfactory functional behaviour. A method is presented which integrates design and test and is based on analytical modelling equations to estimate the sensitivity and determine the reliability of analogue circuits in the presence of parameter fluctuations. The proposed method enables two outcomes to be satisfied: (i) during the design process, the designer will need to consider the extent to which changes in circuit parameters will affect behaviour in order to determine the robustness of the design and the range of signatures within the bound which prove satisfactory behaviour; (ii) during operation, parameter fluctuations outside a predefined bound can be used to generate a warning condition.
{"title":"Estimation of a maximum bound of uncertain parameter fluctuations with applications to analogue IP-cores","authors":"H. Kadim","doi":"10.1109/ISSOC.2004.1411176","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411176","url":null,"abstract":"In analogue circuits, parameter fluctuations trigger variations in functional behaviour. However, such fluctuations may not result in faulty behaviour and, hence, the circuit may still function satisfactorily. Therefore, it is necessary to estimate a maximum bound of fluctuations that retains satisfactory functional behaviour. A method is presented which integrates design and test and is based on analytical modelling equations to estimate the sensitivity and determine the reliability of analogue circuits in the presence of parameter fluctuations. The proposed method enables two outcomes to be satisfied: (i) during the design process, the designer will need to consider the extent to which changes in circuit parameters will affect behaviour in order to determine the robustness of the design and the range of signatures within the bound which prove satisfactory behaviour; (ii) during operation, parameter fluctuations outside a predefined bound can be used to generate a warning condition.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124510582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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