Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411154
K. Virk, J. Madsen
We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework.
{"title":"A system-level multiprocessor system-on-chip modeling framework","authors":"K. Virk, J. Madsen","doi":"10.1109/ISSOC.2004.1411154","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411154","url":null,"abstract":"We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128957695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411130
Yong Luo, Anatoly Moskalev, Laurence E. Bays, B. Petryna
This paper reports a high linearity low power analog front end (AFE) subsystem composed of a contact image sensor (CIS) input amplifier, a programmable gain amplifier (PGA), a 10-bit pipelined analog-to-digital converter (ADC) and a 10-bit offset calibration digital-to-analog converter (DAC). The AFE was integrated into a mixed-signal multiprocessor system-on-chip (SOC) by using conventional ASIC flow. This SOC is fabricated in 0.14 /spl mu/m CMOS process with 3.3 V/1.5 V power supplies. The AFE runs up to 20 Ms/s sampling rate, ATE measurement shows on-chip performance of /spl plusmn/0.8LSB DNL and /spl plusmn/0.9LSB INL with less than 38 mW power dissipation. Timing, functional and behavior models are developed to support ASIC design flow and tools.
{"title":"A high linearity analog front end for multiprocessor SOC integration","authors":"Yong Luo, Anatoly Moskalev, Laurence E. Bays, B. Petryna","doi":"10.1109/ISSOC.2004.1411130","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411130","url":null,"abstract":"This paper reports a high linearity low power analog front end (AFE) subsystem composed of a contact image sensor (CIS) input amplifier, a programmable gain amplifier (PGA), a 10-bit pipelined analog-to-digital converter (ADC) and a 10-bit offset calibration digital-to-analog converter (DAC). The AFE was integrated into a mixed-signal multiprocessor system-on-chip (SOC) by using conventional ASIC flow. This SOC is fabricated in 0.14 /spl mu/m CMOS process with 3.3 V/1.5 V power supplies. The AFE runs up to 20 Ms/s sampling rate, ATE measurement shows on-chip performance of /spl plusmn/0.8LSB DNL and /spl plusmn/0.9LSB INL with less than 38 mW power dissipation. Timing, functional and behavior models are developed to support ASIC design flow and tools.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132456670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411146
Shaojun Wu
A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond wire VCO is proposed. The inductance compensation control circuit combined with the switched-capacitor array is used to automatically compensate the bond wire inductance variation. A novel lock detector that adoptively controls the loop bandwidth is employed. Implemented in a 0.18 /spl mu/m CMOS technology and at a 1.8 V supply voltage, the PLL frequency synthesizer dissipates 24 mW and occupies a chip area of 2.6 mm/spl times/1.6 mm. The simulation results show that phase noise of the synthesizer is -122.6 dBc/Hz at 1 MHz offset frequency and the settling time is 70 /spl mu/s.
{"title":"A low-noise fast-settling PLL frequency synthesizer for CDMA receivers","authors":"Shaojun Wu","doi":"10.1109/ISSOC.2004.1411146","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411146","url":null,"abstract":"A 1.8-2 GHz fully integrated CMOS phase-locked-loop (PLL) frequency synthesizer for CDMA receivers is presented. The design focuses on the voltage controlled oscillator (VCO) and loop bandwidth adaptation technique, which determine the out-of-band phase noise and the speed of the PLL frequency synthesizer, respectively. A low power low phase noise bond wire VCO is proposed. The inductance compensation control circuit combined with the switched-capacitor array is used to automatically compensate the bond wire inductance variation. A novel lock detector that adoptively controls the loop bandwidth is employed. Implemented in a 0.18 /spl mu/m CMOS technology and at a 1.8 V supply voltage, the PLL frequency synthesizer dissipates 24 mW and occupies a chip area of 2.6 mm/spl times/1.6 mm. The simulation results show that phase noise of the synthesizer is -122.6 dBc/Hz at 1 MHz offset frequency and the settling time is 70 /spl mu/s.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131103003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411140
Mehmet Derin Harmanci, Nuria Pazos Escudero, Y. Leblebici, P. Ienne
QoS is not intrinsic in most current NoC solutions, although it is crucial for global predictability and design reuse. Therefore, the current work presents a novel approach that borrows several concepts of DiffServ technology from Internet networks and adapts them to NoCs. This novel implementation based on connection-less communication improves the compromise between guaranteeing different traffic requirements and resource utilization, which is not efficiently granted in connection-oriented techniques, and provides a better scalability than the previous ones.
{"title":"Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities","authors":"Mehmet Derin Harmanci, Nuria Pazos Escudero, Y. Leblebici, P. Ienne","doi":"10.1109/ISSOC.2004.1411140","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411140","url":null,"abstract":"QoS is not intrinsic in most current NoC solutions, although it is crucial for global predictability and design reuse. Therefore, the current work presents a novel approach that borrows several concepts of DiffServ technology from Internet networks and adapts them to NoCs. This novel implementation based on connection-less communication improves the compromise between guaranteeing different traffic requirements and resource utilization, which is not efficiently granted in connection-oriented techniques, and provides a better scalability than the previous ones.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115624390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411151
Tero Rissa, W. Luk
Summary form only given. Our work alms to accelerate FPGA application development by raising the level of abstraction and facilitating design reuse. We propose a solution based on network of nodes, communicating using a packet-based protocol. This network of nodes is known as customisable modular platform (CMP). A node is a computational unit, which can be hardware core running on an FPGA, or a thread running on a processor or a DSP. Hardware nodes can span over several FPGAs or there can be several nodes on a single FPGA. The packet-based communication protocol is implemented using an interchangeable interface. This interface provides a seamless data interchange between the nodes, independent of the implementation target architecture or abstraction. The communication packets of this protocol include control information and data, i.e. header and payload.
{"title":"Reduction of design complexity using virtual hardware platforms","authors":"Tero Rissa, W. Luk","doi":"10.1109/ISSOC.2004.1411151","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411151","url":null,"abstract":"Summary form only given. Our work alms to accelerate FPGA application development by raising the level of abstraction and facilitating design reuse. We propose a solution based on network of nodes, communicating using a packet-based protocol. This network of nodes is known as customisable modular platform (CMP). A node is a computational unit, which can be hardware core running on an FPGA, or a thread running on a processor or a DSP. Hardware nodes can span over several FPGAs or there can be several nodes on a single FPGA. The packet-based communication protocol is implemented using an interchangeable interface. This interface provides a seamless data interchange between the nodes, independent of the implementation target architecture or abstraction. The communication packets of this protocol include control information and data, i.e. header and payload.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130173077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411133
M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra
Summary form only given. The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packet-based communication (A. Jantsch and H. Tenhunen, "Networks on Chip", Kluwer Academic Publishers, 2003). We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summary presents the low cost, high performance on-chip communication network, called Spidergon, developed by the AST (Advanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.
{"title":"Spidergon: a novel on-chip communication network","authors":"M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra","doi":"10.1109/ISSOC.2004.1411133","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411133","url":null,"abstract":"Summary form only given. The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource. In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packet-based communication (A. Jantsch and H. Tenhunen, \"Networks on Chip\", Kluwer Academic Publishers, 2003). We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future. This summary presents the low cost, high performance on-chip communication network, called Spidergon, developed by the AST (Advanced System Technology) of STMicroelectronics as the possible evolution of STBus technology.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128771665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411145
C. C. Wells, E. Duncan, D. Renshaw
This work describes some of the issues faced when integrating a CMOS image sensor into a system-on-chip (SoC). A simple method is proposed for estimating the manufacturing costs of imaging SoCs at several silicon processes using readily available information sources. A low-cost imaging SoC with integral DSP is presented and its manufacturing cost calculated. The results indicated that for the example given, processes of 0.18 /spl mu/m or smaller only start to become more economical than older processes at $2.80 per unit for 500k units.
{"title":"A model for imaging system-on-chip manufacturing costs","authors":"C. C. Wells, E. Duncan, D. Renshaw","doi":"10.1109/ISSOC.2004.1411145","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411145","url":null,"abstract":"This work describes some of the issues faced when integrating a CMOS image sensor into a system-on-chip (SoC). A simple method is proposed for estimating the manufacturing costs of imaging SoCs at several silicon processes using readily available information sources. A low-cost imaging SoC with integral DSP is presented and its manufacturing cost calculated. The results indicated that for the example given, processes of 0.18 /spl mu/m or smaller only start to become more economical than older processes at $2.80 per unit for 500k units.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123719391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-01DOI: 10.1109/ISSOC.2004.1411168
R. Weerasekera, Lirong Zheng, D. Pamunuwa, H. Tenhunen
The effect of crosstalk noise becomes increasingly significant as geometries continue to shrink into the deep sub-micrometer regime and clock-frequency increases into the multi GHz domain. Dynamic delay caused by coupling capacitance between adjacent interconnections is a critical problem, as it cannot accurately be estimated in static timing analysis. This work presents a new driver circuit scheme called the crosstalk immune interconnect driver (XTIID), for capacitively coupled interconnects, which eliminates pattern-dependent coupling noise. Also, such an interconnect drive technology has the potential to facilitate the dynamic timing problem in deep submicrometer VLSI design.
{"title":"Crosstalk immune interconnect driver design","authors":"R. Weerasekera, Lirong Zheng, D. Pamunuwa, H. Tenhunen","doi":"10.1109/ISSOC.2004.1411168","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411168","url":null,"abstract":"The effect of crosstalk noise becomes increasingly significant as geometries continue to shrink into the deep sub-micrometer regime and clock-frequency increases into the multi GHz domain. Dynamic delay caused by coupling capacitance between adjacent interconnections is a critical problem, as it cannot accurately be estimated in static timing analysis. This work presents a new driver circuit scheme called the crosstalk immune interconnect driver (XTIID), for capacitively coupled interconnects, which eliminates pattern-dependent coupling noise. Also, such an interconnect drive technology has the potential to facilitate the dynamic timing problem in deep submicrometer VLSI design.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126888836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/issoc.2004.1411191
{"title":"Accepted papers by country","authors":"","doi":"10.1109/issoc.2004.1411191","DOIUrl":"https://doi.org/10.1109/issoc.2004.1411191","url":null,"abstract":"","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129152448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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