Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411182
G. Andrijevic, H. Magnusson, Henrik Olsson
We propose a fully integrated DVB-T receiver architecture for low cost CMOS implementation. The receiver uses a dual-IF architecture to cover the receive bands from 170 MHz to 862 MHz and a low-IF of 4.57 MHz. Key performance values meet the DVB-T requirements with competitive performance (sensitivity 72.5 dBm, noise figure 6.6 dB, adjacent channel protection ratio (ACPR)= -43 dB, available SNR=28 dB) and suggest that low cost receivers are realistic in volume for the coming digital broadcasting systems.
{"title":"A fully integrated low-IF DVB-T receiver architecture","authors":"G. Andrijevic, H. Magnusson, Henrik Olsson","doi":"10.1109/ISSOC.2004.1411182","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411182","url":null,"abstract":"We propose a fully integrated DVB-T receiver architecture for low cost CMOS implementation. The receiver uses a dual-IF architecture to cover the receive bands from 170 MHz to 862 MHz and a low-IF of 4.57 MHz. Key performance values meet the DVB-T requirements with competitive performance (sensitivity 72.5 dBm, noise figure 6.6 dB, adjacent channel protection ratio (ACPR)= -43 dB, available SNR=28 dB) and suggest that low cost receivers are realistic in volume for the coming digital broadcasting systems.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121083025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411050
H. Meyr
Summary form only given. The next generation of wireless communication systems will be cognitive to efficiently use the available bandwidth. For a given criterion, these systems will adaptively select the transmission method, protocol and the services which are optimal at any given time. Sophisticated signal processing algorithms of ultra high complexity must be executed to perform this adaptation. To meet conflicting goals such as energy efficiency and flexibility together with cost, time-to-market and reusability constraints a radically different, truly innovative architectural approach is necessary for SoCs applied to wireless communications. These future SoCs can be viewed as heterogeneous multiprocessor systems (MP-SoC). They will contain an increasing number of application specific instruction-set processors (ASIPs) combined with complex memory hierarchies and on-chip communication networks (NoC). The success of the proposed MP-SoC is ultimately linked to the availability of an equally innovative system-level design (SLD) methodology together with the corresponding SLD tool suite. In this presentation, we address this innovative SLD design flow in the context of wireless communications. The focus of this presentation is primarily on one crucial aspect of this process: the spatial mapping of application tasks onto ASIPs.
{"title":"Application specific instruction-set processors (ASIP's) for wireless communications: design, cost, and energy efficiency vs. flexibility","authors":"H. Meyr","doi":"10.1109/ISSOC.2004.1411050","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411050","url":null,"abstract":"Summary form only given. The next generation of wireless communication systems will be cognitive to efficiently use the available bandwidth. For a given criterion, these systems will adaptively select the transmission method, protocol and the services which are optimal at any given time. Sophisticated signal processing algorithms of ultra high complexity must be executed to perform this adaptation. To meet conflicting goals such as energy efficiency and flexibility together with cost, time-to-market and reusability constraints a radically different, truly innovative architectural approach is necessary for SoCs applied to wireless communications. These future SoCs can be viewed as heterogeneous multiprocessor systems (MP-SoC). They will contain an increasing number of application specific instruction-set processors (ASIPs) combined with complex memory hierarchies and on-chip communication networks (NoC). The success of the proposed MP-SoC is ultimately linked to the availability of an equally innovative system-level design (SLD) methodology together with the corresponding SLD tool suite. In this presentation, we address this innovative SLD design flow in the context of wireless communications. The focus of this presentation is primarily on one crucial aspect of this process: the spatial mapping of application tasks onto ASIPs.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124733974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411051
S. Angioni, F. Lazare
The much-heralded concept of creating a single-processor cellular modem has now become reality. TTPCom's latest version of their cellular baseband engine (CBE 2000) combines both digital signal processor and microcontroller functions on a single processor, resulting in a greatly simplified programming model. This provides a more flexible way to partition tasks for easier maintenance and higher programming efficiency. In this paper, we present an innovation that demonstrates a new system architecture. StarCore's VLES (variable-length execution set) technology allows software developers to develop both signal processing and control code entirely in C and compile it into a seamlessly integrated application.
{"title":"Implementing a single-processor cellular modem on an SC1000-family core","authors":"S. Angioni, F. Lazare","doi":"10.1109/ISSOC.2004.1411051","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411051","url":null,"abstract":"The much-heralded concept of creating a single-processor cellular modem has now become reality. TTPCom's latest version of their cellular baseband engine (CBE 2000) combines both digital signal processor and microcontroller functions on a single processor, resulting in a greatly simplified programming model. This provides a more flexible way to partition tasks for easier maintenance and higher programming efficiency. In this paper, we present an innovation that demonstrates a new system architecture. StarCore's VLES (variable-length execution set) technology allows software developers to develop both signal processing and control code entirely in C and compile it into a seamlessly integrated application.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117219842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411176
H. Kadim
In analogue circuits, parameter fluctuations trigger variations in functional behaviour. However, such fluctuations may not result in faulty behaviour and, hence, the circuit may still function satisfactorily. Therefore, it is necessary to estimate a maximum bound of fluctuations that retains satisfactory functional behaviour. A method is presented which integrates design and test and is based on analytical modelling equations to estimate the sensitivity and determine the reliability of analogue circuits in the presence of parameter fluctuations. The proposed method enables two outcomes to be satisfied: (i) during the design process, the designer will need to consider the extent to which changes in circuit parameters will affect behaviour in order to determine the robustness of the design and the range of signatures within the bound which prove satisfactory behaviour; (ii) during operation, parameter fluctuations outside a predefined bound can be used to generate a warning condition.
{"title":"Estimation of a maximum bound of uncertain parameter fluctuations with applications to analogue IP-cores","authors":"H. Kadim","doi":"10.1109/ISSOC.2004.1411176","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411176","url":null,"abstract":"In analogue circuits, parameter fluctuations trigger variations in functional behaviour. However, such fluctuations may not result in faulty behaviour and, hence, the circuit may still function satisfactorily. Therefore, it is necessary to estimate a maximum bound of fluctuations that retains satisfactory functional behaviour. A method is presented which integrates design and test and is based on analytical modelling equations to estimate the sensitivity and determine the reliability of analogue circuits in the presence of parameter fluctuations. The proposed method enables two outcomes to be satisfied: (i) during the design process, the designer will need to consider the extent to which changes in circuit parameters will affect behaviour in order to determine the robustness of the design and the range of signatures within the bound which prove satisfactory behaviour; (ii) during operation, parameter fluctuations outside a predefined bound can be used to generate a warning condition.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124510582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411159
H. Kariniemi, J. Nurmi
Platform-based design flows are coming into use in system-on-chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same platform, use also reusable interconnect IP (IIP) blocks as communication infrastructures. This work presents a new layout scheme named Backbone layout where a new extended-generalized-fat-tree (XGFT) IIP can be used as a single large block. It is especially usable on such SoC circuits where IP blocks which communicate across the XGFT IIP are approximately of the same size. This paper presents also two different implementations of the XGFT HP and compares their performance. These two networks are also compared to a two-dimensional mesh which will be commonly used in network-on-chip (NOC) implementations. The results of the performance simulations and logic syntheses show that XGFTs are able to produce approximately the same performance as the mesh with considerably smaller area consumption. In addition, they show that XGFTs are more scalable for different performance requirements and different traffic patterns than meshes, and that the performance of the XGFTs and meshes can be improved by suitable placement of communicating blocks or software processes.
{"title":"Reusable XGFT interconnect IP for network-on-chip implementations","authors":"H. Kariniemi, J. Nurmi","doi":"10.1109/ISSOC.2004.1411159","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411159","url":null,"abstract":"Platform-based design flows are coming into use in system-on-chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same platform, use also reusable interconnect IP (IIP) blocks as communication infrastructures. This work presents a new layout scheme named Backbone layout where a new extended-generalized-fat-tree (XGFT) IIP can be used as a single large block. It is especially usable on such SoC circuits where IP blocks which communicate across the XGFT IIP are approximately of the same size. This paper presents also two different implementations of the XGFT HP and compares their performance. These two networks are also compared to a two-dimensional mesh which will be commonly used in network-on-chip (NOC) implementations. The results of the performance simulations and logic syntheses show that XGFTs are able to produce approximately the same performance as the mesh with considerably smaller area consumption. In addition, they show that XGFTs are more scalable for different performance requirements and different traffic patterns than meshes, and that the performance of the XGFTs and meshes can be improved by suitable placement of communicating blocks or software processes.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"695 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411139
M. Forsell
Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming, even in step synchronous emulated shared memory machines (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper, we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.
{"title":"Efficient barrier synchronization mechanism for emulated shared memory NOCs","authors":"M. Forsell","doi":"10.1109/ISSOC.2004.1411139","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411139","url":null,"abstract":"Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming, even in step synchronous emulated shared memory machines (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper, we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114289596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411137
S. Sathe, D. Wiklund, Dake Liu
The complexity of system-on-chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. On-chip networks (OCNs) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router We present a prototype design of a 5-input, 5-output, scalable guaranteed throughput (GT) router The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN. The router supports wormhole routing, and is characterized by an area of 0.1 mm/sup 2/ in 0.18 micron CMOS technology.
{"title":"Design of a guaranteed throughput router for on-chip networks","authors":"S. Sathe, D. Wiklund, Dake Liu","doi":"10.1109/ISSOC.2004.1411137","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411137","url":null,"abstract":"The complexity of system-on-chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. On-chip networks (OCNs) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router We present a prototype design of a 5-input, 5-output, scalable guaranteed throughput (GT) router The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN. The router supports wormhole routing, and is characterized by an area of 0.1 mm/sup 2/ in 0.18 micron CMOS technology.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124951493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411178
S. Gomi, K. Nakamura, Hiroyuki Ito, H. Sugita, K. Okada, K. Masu
This work presents a high speed and low power on-chip micro network circuit with differential transmission line for seamless intra- and inter-chip communication. A 4 Gbps pulse signal transmission was confirmed and an 8 Gbps pulse signal was confirmed at the receiver circuit in 0.35 /spl mu/m and 0.18 /spl mu/m CMOS process technologies, respectively. It is expected that over 10 Gbps signal transmission can be achieved by using sub-100 nm CMOS technologies. From the simulated results, the RLC differential transmission line is faster and has lower power consumption than the RC line.
{"title":"High speed and low power on-chip micro network circuit with differential transmission line","authors":"S. Gomi, K. Nakamura, Hiroyuki Ito, H. Sugita, K. Okada, K. Masu","doi":"10.1109/ISSOC.2004.1411178","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411178","url":null,"abstract":"This work presents a high speed and low power on-chip micro network circuit with differential transmission line for seamless intra- and inter-chip communication. A 4 Gbps pulse signal transmission was confirmed and an 8 Gbps pulse signal was confirmed at the receiver circuit in 0.35 /spl mu/m and 0.18 /spl mu/m CMOS process technologies, respectively. It is expected that over 10 Gbps signal transmission can be achieved by using sub-100 nm CMOS technologies. From the simulated results, the RLC differential transmission line is faster and has lower power consumption than the RC line.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411144
Jouni Riihimäki, Petri Kukkala, E. Salminen, Marko Hännikäinen, Kimmo Kuusilinna, T. Hämäläinen
Simulation with detailed register transfer-level models is crucial for many verification strategies. Thorough verification of a wireless network formed from several RTL WLAN terminal models is impractical since accurate simulations are very time consuming. In this paper, the problem is solved by distributing the simulation among several networked computers or on a multi-processor workstation. The distribution provides over 7-fold speed-up when the wireless network is simulated with eight Linux PCs. Eight-processor workstation provides over 5-fold speed-up for the same simulations.
{"title":"Practical distributed simulation of a network of wireless terminals","authors":"Jouni Riihimäki, Petri Kukkala, E. Salminen, Marko Hännikäinen, Kimmo Kuusilinna, T. Hämäläinen","doi":"10.1109/ISSOC.2004.1411144","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411144","url":null,"abstract":"Simulation with detailed register transfer-level models is crucial for many verification strategies. Thorough verification of a wireless network formed from several RTL WLAN terminal models is impractical since accurate simulations are very time consuming. In this paper, the problem is solved by distributing the simulation among several networked computers or on a multi-processor workstation. The distribution provides over 7-fold speed-up when the wireless network is simulated with eight Linux PCs. Eight-processor workstation provides over 5-fold speed-up for the same simulations.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115452301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411155
C. Panis, U. Hirnschrott, S. Farfeleder, A. Krall, G. Laure, W. Lazian, J. Nurmi
Increasing system complexity of SoC (system-on-chip) and SiP (system-in-package) applications leads to the strong demand of platform based solutions. Software programmable embedded cores are required to provide flexibility to these platforms. Compared with dedicated hardware implementations the provided flexibility leads to increased silicon area and power dissipation, which is problematic for high volume products. This paper introduces xDSPcore, a scalable embedded DSP processor which allows to scale major architectural features to application specific requirements. Compatibility issues caused by different core versions are covered by the support of efficient programming in high-level languages like C, which is achieved by an optimizing C-compiler and by a compiler friendly core architecture. A particular core definition is specified by a XML based configuration file.
{"title":"A scalable embedded DSP core for SoC applications","authors":"C. Panis, U. Hirnschrott, S. Farfeleder, A. Krall, G. Laure, W. Lazian, J. Nurmi","doi":"10.1109/ISSOC.2004.1411155","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411155","url":null,"abstract":"Increasing system complexity of SoC (system-on-chip) and SiP (system-in-package) applications leads to the strong demand of platform based solutions. Software programmable embedded cores are required to provide flexibility to these platforms. Compared with dedicated hardware implementations the provided flexibility leads to increased silicon area and power dissipation, which is problematic for high volume products. This paper introduces xDSPcore, a scalable embedded DSP processor which allows to scale major architectural features to application specific requirements. Compatibility issues caused by different core versions are covered by the support of efficient programming in high-level languages like C, which is achieved by an optimizing C-compiler and by a compiler friendly core architecture. A particular core definition is specified by a XML based configuration file.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125843925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：