Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411162
Alfred Blaickner, Susanne Albl, W. Scherr
Future systems on chip for wireless and multimedia applications will have a strong demand for interoperability and inexpensive hardware solutions. Extended functionality, advanced signal processing functions and even multi-mode or multi-standard capabilities are an important design goal. Configurable architectures, arithmetic hardware accelerators or so called application specific instruction processors (ASIPs) are bridging the gap between application derived hardwired logic and software programmed general purpose microprocessors. For wireless and software defined radio applications this work presents selected baseband processing and error correction solutions as, for example, a Galois-field-ASIP-based decoder, a channel-processor and a WCDMA-transceiver. The concept and the prototype of the units was designed and verified by bit-true MatLab and System C/C++ based high level design methods. After synthesis and translation to a VHDL architecture description the design was tested in real-time on a high density DSP/FPGA-prototyping unit (PASS - Programmable Array System Simulator).
{"title":"Configurable computing architectures for wireless and software defined radio - a FPGA prototyping experience using high level design-tool-chains","authors":"Alfred Blaickner, Susanne Albl, W. Scherr","doi":"10.1109/ISSOC.2004.1411162","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411162","url":null,"abstract":"Future systems on chip for wireless and multimedia applications will have a strong demand for interoperability and inexpensive hardware solutions. Extended functionality, advanced signal processing functions and even multi-mode or multi-standard capabilities are an important design goal. Configurable architectures, arithmetic hardware accelerators or so called application specific instruction processors (ASIPs) are bridging the gap between application derived hardwired logic and software programmed general purpose microprocessors. For wireless and software defined radio applications this work presents selected baseband processing and error correction solutions as, for example, a Galois-field-ASIP-based decoder, a channel-processor and a WCDMA-transceiver. The concept and the prototype of the units was designed and verified by bit-true MatLab and System C/C++ based high level design methods. After synthesis and translation to a VHDL architecture description the design was tested in real-time on a high density DSP/FPGA-prototyping unit (PASS - Programmable Array System Simulator).","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123369859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411051
S. Angioni, F. Lazare
The much-heralded concept of creating a single-processor cellular modem has now become reality. TTPCom's latest version of their cellular baseband engine (CBE 2000) combines both digital signal processor and microcontroller functions on a single processor, resulting in a greatly simplified programming model. This provides a more flexible way to partition tasks for easier maintenance and higher programming efficiency. In this paper, we present an innovation that demonstrates a new system architecture. StarCore's VLES (variable-length execution set) technology allows software developers to develop both signal processing and control code entirely in C and compile it into a seamlessly integrated application.
{"title":"Implementing a single-processor cellular modem on an SC1000-family core","authors":"S. Angioni, F. Lazare","doi":"10.1109/ISSOC.2004.1411051","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411051","url":null,"abstract":"The much-heralded concept of creating a single-processor cellular modem has now become reality. TTPCom's latest version of their cellular baseband engine (CBE 2000) combines both digital signal processor and microcontroller functions on a single processor, resulting in a greatly simplified programming model. This provides a more flexible way to partition tasks for easier maintenance and higher programming efficiency. In this paper, we present an innovation that demonstrates a new system architecture. StarCore's VLES (variable-length execution set) technology allows software developers to develop both signal processing and control code entirely in C and compile it into a seamlessly integrated application.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117219842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411182
G. Andrijevic, H. Magnusson, Henrik Olsson
We propose a fully integrated DVB-T receiver architecture for low cost CMOS implementation. The receiver uses a dual-IF architecture to cover the receive bands from 170 MHz to 862 MHz and a low-IF of 4.57 MHz. Key performance values meet the DVB-T requirements with competitive performance (sensitivity 72.5 dBm, noise figure 6.6 dB, adjacent channel protection ratio (ACPR)= -43 dB, available SNR=28 dB) and suggest that low cost receivers are realistic in volume for the coming digital broadcasting systems.
{"title":"A fully integrated low-IF DVB-T receiver architecture","authors":"G. Andrijevic, H. Magnusson, Henrik Olsson","doi":"10.1109/ISSOC.2004.1411182","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411182","url":null,"abstract":"We propose a fully integrated DVB-T receiver architecture for low cost CMOS implementation. The receiver uses a dual-IF architecture to cover the receive bands from 170 MHz to 862 MHz and a low-IF of 4.57 MHz. Key performance values meet the DVB-T requirements with competitive performance (sensitivity 72.5 dBm, noise figure 6.6 dB, adjacent channel protection ratio (ACPR)= -43 dB, available SNR=28 dB) and suggest that low cost receivers are realistic in volume for the coming digital broadcasting systems.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121083025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411165
T. Ahonen, J. Nurmi
Design reuse offers time-to-market reduction through exploitation of previously created components and subsystems. Wide adoption of design reuse lays the foundation for the development of system-level design methodologies. The study described here focused on the design for reuse of an HDSL2 transceiver SoC and its components. The problems faced when trying to reuse old macro components are discussed and the disciplines adopted to ensure reusability of the created intellectual property (IP) are summarized. The disciplines have proven effective, as the Viterbi decoder component was modified for reuse in an asynchronous environment in another university without any support from the original designer.
{"title":"Design reuse and design for reuse, a case study on HDSL2","authors":"T. Ahonen, J. Nurmi","doi":"10.1109/ISSOC.2004.1411165","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411165","url":null,"abstract":"Design reuse offers time-to-market reduction through exploitation of previously created components and subsystems. Wide adoption of design reuse lays the foundation for the development of system-level design methodologies. The study described here focused on the design for reuse of an HDSL2 transceiver SoC and its components. The problems faced when trying to reuse old macro components are discussed and the disciplines adopted to ensure reusability of the created intellectual property (IP) are summarized. The disciplines have proven effective, as the Viterbi decoder component was modified for reuse in an asynchronous environment in another university without any support from the original designer.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"2 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113993479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411159
H. Kariniemi, J. Nurmi
Platform-based design flows are coming into use in system-on-chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same platform, use also reusable interconnect IP (IIP) blocks as communication infrastructures. This work presents a new layout scheme named Backbone layout where a new extended-generalized-fat-tree (XGFT) IIP can be used as a single large block. It is especially usable on such SoC circuits where IP blocks which communicate across the XGFT IIP are approximately of the same size. This paper presents also two different implementations of the XGFT HP and compares their performance. These two networks are also compared to a two-dimensional mesh which will be commonly used in network-on-chip (NOC) implementations. The results of the performance simulations and logic syntheses show that XGFTs are able to produce approximately the same performance as the mesh with considerably smaller area consumption. In addition, they show that XGFTs are more scalable for different performance requirements and different traffic patterns than meshes, and that the performance of the XGFTs and meshes can be improved by suitable placement of communicating blocks or software processes.
{"title":"Reusable XGFT interconnect IP for network-on-chip implementations","authors":"H. Kariniemi, J. Nurmi","doi":"10.1109/ISSOC.2004.1411159","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411159","url":null,"abstract":"Platform-based design flows are coming into use in system-on-chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same platform, use also reusable interconnect IP (IIP) blocks as communication infrastructures. This work presents a new layout scheme named Backbone layout where a new extended-generalized-fat-tree (XGFT) IIP can be used as a single large block. It is especially usable on such SoC circuits where IP blocks which communicate across the XGFT IIP are approximately of the same size. This paper presents also two different implementations of the XGFT HP and compares their performance. These two networks are also compared to a two-dimensional mesh which will be commonly used in network-on-chip (NOC) implementations. The results of the performance simulations and logic syntheses show that XGFTs are able to produce approximately the same performance as the mesh with considerably smaller area consumption. In addition, they show that XGFTs are more scalable for different performance requirements and different traffic patterns than meshes, and that the performance of the XGFTs and meshes can be improved by suitable placement of communicating blocks or software processes.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"695 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411137
S. Sathe, D. Wiklund, Dake Liu
The complexity of system-on-chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. On-chip networks (OCNs) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router We present a prototype design of a 5-input, 5-output, scalable guaranteed throughput (GT) router The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN. The router supports wormhole routing, and is characterized by an area of 0.1 mm/sup 2/ in 0.18 micron CMOS technology.
{"title":"Design of a guaranteed throughput router for on-chip networks","authors":"S. Sathe, D. Wiklund, Dake Liu","doi":"10.1109/ISSOC.2004.1411137","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411137","url":null,"abstract":"The complexity of system-on-chip (SoC) designs continues to increase, and traditional bus-based interconnects will not be sufficient to manage the communication requirements of future billion transistor chips. On-chip networks (OCNs) provide a scalable alternative to existing on-chip interconnects. The key element of the OCN is the router We present a prototype design of a 5-input, 5-output, scalable guaranteed throughput (GT) router The router is constructed from a collection of parameterizable and reusable hardware blocks and is a basic building block of the OCN. The router supports wormhole routing, and is characterized by an area of 0.1 mm/sup 2/ in 0.18 micron CMOS technology.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124951493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411178
S. Gomi, K. Nakamura, Hiroyuki Ito, H. Sugita, K. Okada, K. Masu
This work presents a high speed and low power on-chip micro network circuit with differential transmission line for seamless intra- and inter-chip communication. A 4 Gbps pulse signal transmission was confirmed and an 8 Gbps pulse signal was confirmed at the receiver circuit in 0.35 /spl mu/m and 0.18 /spl mu/m CMOS process technologies, respectively. It is expected that over 10 Gbps signal transmission can be achieved by using sub-100 nm CMOS technologies. From the simulated results, the RLC differential transmission line is faster and has lower power consumption than the RC line.
{"title":"High speed and low power on-chip micro network circuit with differential transmission line","authors":"S. Gomi, K. Nakamura, Hiroyuki Ito, H. Sugita, K. Okada, K. Masu","doi":"10.1109/ISSOC.2004.1411178","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411178","url":null,"abstract":"This work presents a high speed and low power on-chip micro network circuit with differential transmission line for seamless intra- and inter-chip communication. A 4 Gbps pulse signal transmission was confirmed and an 8 Gbps pulse signal was confirmed at the receiver circuit in 0.35 /spl mu/m and 0.18 /spl mu/m CMOS process technologies, respectively. It is expected that over 10 Gbps signal transmission can be achieved by using sub-100 nm CMOS technologies. From the simulated results, the RLC differential transmission line is faster and has lower power consumption than the RC line.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411139
M. Forsell
Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming, even in step synchronous emulated shared memory machines (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper, we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.
{"title":"Efficient barrier synchronization mechanism for emulated shared memory NOCs","authors":"M. Forsell","doi":"10.1109/ISSOC.2004.1411139","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411139","url":null,"abstract":"Explicit synchronization mechanisms capable of arbitrary simultaneous barriers are needed to support parallely recursive synchronous MIMD programming, even in step synchronous emulated shared memory machines (ESMM) because control of threads may privately depend on input values. Current synchronization mechanisms fail to support arbitrary simultaneous barriers or are not scalable with future silicon technologies. In this paper, we propose a novel constant execution time barrier synchronization mechanism for scalable ESMMs using active memory. The mechanism is applied to our Eclipse network-on-chip architecture and evaluated briefly.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114289596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411154
K. Virk, J. Madsen
We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework.
{"title":"A system-level multiprocessor system-on-chip modeling framework","authors":"K. Virk, J. Madsen","doi":"10.1109/ISSOC.2004.1411154","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411154","url":null,"abstract":"We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128957695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-16DOI: 10.1109/ISSOC.2004.1411144
Jouni Riihimäki, Petri Kukkala, E. Salminen, Marko Hännikäinen, Kimmo Kuusilinna, T. Hämäläinen
Simulation with detailed register transfer-level models is crucial for many verification strategies. Thorough verification of a wireless network formed from several RTL WLAN terminal models is impractical since accurate simulations are very time consuming. In this paper, the problem is solved by distributing the simulation among several networked computers or on a multi-processor workstation. The distribution provides over 7-fold speed-up when the wireless network is simulated with eight Linux PCs. Eight-processor workstation provides over 5-fold speed-up for the same simulations.
{"title":"Practical distributed simulation of a network of wireless terminals","authors":"Jouni Riihimäki, Petri Kukkala, E. Salminen, Marko Hännikäinen, Kimmo Kuusilinna, T. Hämäläinen","doi":"10.1109/ISSOC.2004.1411144","DOIUrl":"https://doi.org/10.1109/ISSOC.2004.1411144","url":null,"abstract":"Simulation with detailed register transfer-level models is crucial for many verification strategies. Thorough verification of a wireless network formed from several RTL WLAN terminal models is impractical since accurate simulations are very time consuming. In this paper, the problem is solved by distributing the simulation among several networked computers or on a multi-processor workstation. The distribution provides over 7-fold speed-up when the wireless network is simulated with eight Linux PCs. Eight-processor workstation provides over 5-fold speed-up for the same simulations.","PeriodicalId":268122,"journal":{"name":"2004 International Symposium on System-on-Chip, 2004. Proceedings.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115452301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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