Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852761
I.S. Park, B. Lee, S. Choi, Jae Soon Im, Seung Hwan Lee, K. Park, Joo-Won Lee, Y. Hyung, Yeong-kwan Kim, H. Park, Y. Park, Sang In Lee, M. Lee
A novel MIS-Al/sub 2/O/sub 3/ capacitor technology was developed with the low thermal budget and showed the superior dielectric characteristics, which were achieved by adopting ALD technique for the Al/sub 2/O/sub 3/ film deposition. A fully integrated 1 Gbit DRAM with MIS-Al/sub 2/O/sub 3/ capacitor was successfully worked, where storage capacitance and leakage current at 1.2 V were 30 fF/cell and 0.5 fA/cell, respectively. Moreover, the excellent dielectric characteristics were confirmed from the result that Vp for generating solid "0" 10 sec fail bit counts was measured to be 2.4 V.
{"title":"Novel MIS Al/sub 2/O/sub 3/ capacitor as a prospective technology for Gbit DRAMs","authors":"I.S. Park, B. Lee, S. Choi, Jae Soon Im, Seung Hwan Lee, K. Park, Joo-Won Lee, Y. Hyung, Yeong-kwan Kim, H. Park, Y. Park, Sang In Lee, M. Lee","doi":"10.1109/VLSIT.2000.852761","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852761","url":null,"abstract":"A novel MIS-Al/sub 2/O/sub 3/ capacitor technology was developed with the low thermal budget and showed the superior dielectric characteristics, which were achieved by adopting ALD technique for the Al/sub 2/O/sub 3/ film deposition. A fully integrated 1 Gbit DRAM with MIS-Al/sub 2/O/sub 3/ capacitor was successfully worked, where storage capacitance and leakage current at 1.2 V were 30 fF/cell and 0.5 fA/cell, respectively. Moreover, the excellent dielectric characteristics were confirmed from the result that Vp for generating solid \"0\" 10 sec fail bit counts was measured to be 2.4 V.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123259150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852831
Y. Harada, K. Eriguchi, M. Niwa, T. Watanabe, I. Ohdomari
We clarify the effects of the strained-SiO/sub 2/ on the time dependent dielectric breakdown (TDDB) characteristics, the activation energy of the oxide breakdown and Weibull slope (/spl beta/) for the ultra-thin gate oxide. Considerations based on the extended-Stillinger-Weber potential model show that the built-in compressive strain in SiO/sub 2/ changes the statistical distribution of the Si-O-Si angle, leading to a decrease of T/sub pd/ and a spread of the distribution. The oxide breakdown tends to occur at the Si-O-Si network with a lower bond angle (/spl sim/115/spl deg/) for the 2 nm-thick SiO/sub 2//Si system.
{"title":"Impacts of strained SiO/sub 2/ on TDDB lifetime projection","authors":"Y. Harada, K. Eriguchi, M. Niwa, T. Watanabe, I. Ohdomari","doi":"10.1109/VLSIT.2000.852831","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852831","url":null,"abstract":"We clarify the effects of the strained-SiO/sub 2/ on the time dependent dielectric breakdown (TDDB) characteristics, the activation energy of the oxide breakdown and Weibull slope (/spl beta/) for the ultra-thin gate oxide. Considerations based on the extended-Stillinger-Weber potential model show that the built-in compressive strain in SiO/sub 2/ changes the statistical distribution of the Si-O-Si angle, leading to a decrease of T/sub pd/ and a spread of the distribution. The oxide breakdown tends to occur at the Si-O-Si network with a lower bond angle (/spl sim/115/spl deg/) for the 2 nm-thick SiO/sub 2//Si system.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116132416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852821
Seungheon Song, W.S. Kim, J.S. Lee, T. Choe, J.H. Choi, M. Kang, U. Chung, N. Lee, K. Fujihara, H. Kang, S.I. Lee, M.Y. Lee
Sub-100 nm CMOS transistors with ultra-thin gate dielectrics below 2.0 nm were fabricated and characterized. Super-steep retrograde channel profiles using boron (NMOS) or arsenic (PMOS) channel implantation followed by selective epitaxial growth of undoped-Si were found to effectively reduce short-channel effect and improve current drivability even in the sub-100 nm regime. For NMOS, indium implanted devices showed better short-channel immunity, however, no improvement in current drivability was observed. Optimization of the gate oxide thickness versus gate length was investigated in the presence of direct tunneling leakages and for the first time, an experimental guideline of oxide scaling is proposed. For PMOS, to suppress boron penetration, sub-2.0 nm stack gate dielectrics of oxynitride and LPCVD nitride were developed, which showed excellent transistor characteristics.
{"title":"Design of sub-100 nm CMOSFETs: gate dielectrics and channel engineering","authors":"Seungheon Song, W.S. Kim, J.S. Lee, T. Choe, J.H. Choi, M. Kang, U. Chung, N. Lee, K. Fujihara, H. Kang, S.I. Lee, M.Y. Lee","doi":"10.1109/VLSIT.2000.852821","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852821","url":null,"abstract":"Sub-100 nm CMOS transistors with ultra-thin gate dielectrics below 2.0 nm were fabricated and characterized. Super-steep retrograde channel profiles using boron (NMOS) or arsenic (PMOS) channel implantation followed by selective epitaxial growth of undoped-Si were found to effectively reduce short-channel effect and improve current drivability even in the sub-100 nm regime. For NMOS, indium implanted devices showed better short-channel immunity, however, no improvement in current drivability was observed. Optimization of the gate oxide thickness versus gate length was investigated in the presence of direct tunneling leakages and for the first time, an experimental guideline of oxide scaling is proposed. For PMOS, to suppress boron penetration, sub-2.0 nm stack gate dielectrics of oxynitride and LPCVD nitride were developed, which showed excellent transistor characteristics.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122674218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852776
Q. Xiang, C. Woo, E. Paton, J. Foster, B. Yu, M. Lin
CMOS devices down to 50 nm gate length were fabricated with NiSi salicide for the first time. Edge effects of Ni-polycide formation, enhanced by a recessed spacer, results in gate Rs roll-off with poly line width. Ultra low /spl sim/2 /spl Omega///spl square/ gate Rs is achieved for 50 nm line width with low junction leakage. Source/drain series resistance is significantly reduced and, consequently, drive current is improved with NiSi. Ring oscillator speed measurements showed significant improvement in gate delay with NiSi, especially for the ring oscillators made with large gate width devices.
{"title":"Deep sub-100 nm CMOS with ultra low gate sheet resistance by NiSi","authors":"Q. Xiang, C. Woo, E. Paton, J. Foster, B. Yu, M. Lin","doi":"10.1109/VLSIT.2000.852776","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852776","url":null,"abstract":"CMOS devices down to 50 nm gate length were fabricated with NiSi salicide for the first time. Edge effects of Ni-polycide formation, enhanced by a recessed spacer, results in gate Rs roll-off with poly line width. Ultra low /spl sim/2 /spl Omega///spl square/ gate Rs is achieved for 50 nm line width with low junction leakage. Source/drain series resistance is significantly reduced and, consequently, drive current is improved with NiSi. Ring oscillator speed measurements showed significant improvement in gate delay with NiSi, especially for the ring oscillators made with large gate width devices.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117014857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852767
K. Tokunaga, F. Koba, M. Miyasaka, Y. Takaishi, K. Noda, H. Yamashita, K. Nakajima, H. Nozue
Electron beam (EB) projection lithography (EPL), such as the EB stepper and the SCALPEL, is expected to be next generation lithography (NGL) for mass-production of sub-0.1 /spl mu/m ULSls. Adopting an EB scattering mask with 1.0/spl times/1.0 mm mask pattern area (4/spl times/) will drastically increase the writing throughput. In addition, a pattern resolution of 80 nm or less can be obtained using a 100 kV acceleration voltage. However, it is important to develop high sensitivity EB resists for achieving the writing throughput of 40 wafers/hour or more (8"/spl phi/) and to optimize the proximity effect correction for improving the CD accuracy of 10 nm or less (3/spl sigma/). In this report, we show the EPL for 60-80 nm ULSI fabrication using improved EB chemically amplified resist process and optimized proximity effect correction accompanied with pattern modification methods.
{"title":"EB projection lithography for 60-80 nm ULSI fabrication","authors":"K. Tokunaga, F. Koba, M. Miyasaka, Y. Takaishi, K. Noda, H. Yamashita, K. Nakajima, H. Nozue","doi":"10.1109/VLSIT.2000.852767","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852767","url":null,"abstract":"Electron beam (EB) projection lithography (EPL), such as the EB stepper and the SCALPEL, is expected to be next generation lithography (NGL) for mass-production of sub-0.1 /spl mu/m ULSls. Adopting an EB scattering mask with 1.0/spl times/1.0 mm mask pattern area (4/spl times/) will drastically increase the writing throughput. In addition, a pattern resolution of 80 nm or less can be obtained using a 100 kV acceleration voltage. However, it is important to develop high sensitivity EB resists for achieving the writing throughput of 40 wafers/hour or more (8\"/spl phi/) and to optimize the proximity effect correction for improving the CD accuracy of 10 nm or less (3/spl sigma/). In this report, we show the EPL for 60-80 nm ULSI fabrication using improved EB chemically amplified resist process and optimized proximity effect correction accompanied with pattern modification methods.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129723764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852814
T. Ghani, K. Mistry, P. Packan, Scott E. Thompson, M. Stettler, S. Tyagi, M. Bohr
Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.
{"title":"Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors","authors":"T. Ghani, K. Mistry, P. Packan, Scott E. Thompson, M. Stettler, S. Tyagi, M. Bohr","doi":"10.1109/VLSIT.2000.852814","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852814","url":null,"abstract":"Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129760300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852792
M. Togo, K. Watanabe, T. Yamamoto, N. Ikarashi, K. Shiba, T. Tatsumi, H. Ono, T. Mogami
We have developed a low-leakage and highly-reliable 1.5 nm SiON gate-dielectric by using radical oxynitridation. In this development, we introduce a new method for determining ultra-thin SiON gate-dielectric thickness based on the threshold voltage dependence on the substrate bias in MOSFETs. It was found that radical oxidation followed by radical nitridation provides 1.5 nm thick SiON in which leakage current is two orders of magnitude less than that of 1.5 nm thick SiO/sub 2/ without degrading device performance. The 1.5 nm thick SiON was also found to be ten times more reliable than 1.5 nm thick SiO/sub 2/.
{"title":"Low-leakage and highly-reliable 1.5 nm SiON gate-dielectric using radical oxynitridation for sub-0.1 /spl mu/m CMOS","authors":"M. Togo, K. Watanabe, T. Yamamoto, N. Ikarashi, K. Shiba, T. Tatsumi, H. Ono, T. Mogami","doi":"10.1109/VLSIT.2000.852792","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852792","url":null,"abstract":"We have developed a low-leakage and highly-reliable 1.5 nm SiON gate-dielectric by using radical oxynitridation. In this development, we introduce a new method for determining ultra-thin SiON gate-dielectric thickness based on the threshold voltage dependence on the substrate bias in MOSFETs. It was found that radical oxidation followed by radical nitridation provides 1.5 nm thick SiON in which leakage current is two orders of magnitude less than that of 1.5 nm thick SiO/sub 2/ without degrading device performance. The 1.5 nm thick SiON was also found to be ten times more reliable than 1.5 nm thick SiO/sub 2/.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128798907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852768
P. Mertens, G. Doumen, J. Lauerhaas, K. Kenis, W. Fyen, M. Meuris, S. Arnauts, K. Devriendt, R. Vos, M. Heyns
A novel fast drying method for single wafer wet cleaning is proposed. The water-mark free drying method is based on an efficient interaction between Marangoni forces and rotational forces. The method is shown to yield excellent particle performance.
{"title":"A high performance drying method enabling clustered single wafer wet cleaning","authors":"P. Mertens, G. Doumen, J. Lauerhaas, K. Kenis, W. Fyen, M. Meuris, S. Arnauts, K. Devriendt, R. Vos, M. Heyns","doi":"10.1109/VLSIT.2000.852768","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852768","url":null,"abstract":"A novel fast drying method for single wafer wet cleaning is proposed. The water-mark free drying method is based on an efficient interaction between Marangoni forces and rotational forces. The method is shown to yield excellent particle performance.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130550571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852817
A. Steegen, A. Lauwers, M. de Potter, G. Badenes, R. Rooyackers, K. Maex
For the first time, the influence of the mechanical stress, induced by silicidation of active areas in combination with stress from the Shallow Trench Isolation (STI), on the leakage current of n+/p and p+/n junctions has been studied. When scaling down the width of the diode structure from 2 /spl mu/m to 0.25 /spl mu/m, the anisotropic compressive stress in the junction area increases drastically. These experiments prove that regardless the contributions of the area and the perimeter to the total leakage current of this type of diode structure (=20%), 80% of the total leakage current of this diode structure can be attributed to stress and that this part of the leakage current increases with almost a factor of two when reducing the junction width from 2 /spl mu/m to 0.25 /spl mu/m. Therefore, in order to keep the diode leakage variation as low as possible when further down scaling the junction and the trench dimensions, the formation of a low stress silicide in combination with a low stress isolation technology is essential.
{"title":"Silicide and Shallow Trench Isolation line width dependent stress induced junction leakage","authors":"A. Steegen, A. Lauwers, M. de Potter, G. Badenes, R. Rooyackers, K. Maex","doi":"10.1109/VLSIT.2000.852817","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852817","url":null,"abstract":"For the first time, the influence of the mechanical stress, induced by silicidation of active areas in combination with stress from the Shallow Trench Isolation (STI), on the leakage current of n+/p and p+/n junctions has been studied. When scaling down the width of the diode structure from 2 /spl mu/m to 0.25 /spl mu/m, the anisotropic compressive stress in the junction area increases drastically. These experiments prove that regardless the contributions of the area and the perimeter to the total leakage current of this type of diode structure (=20%), 80% of the total leakage current of this diode structure can be attributed to stress and that this part of the leakage current increases with almost a factor of two when reducing the junction width from 2 /spl mu/m to 0.25 /spl mu/m. Therefore, in order to keep the diode leakage variation as low as possible when further down scaling the junction and the trench dimensions, the formation of a low stress silicide in combination with a low stress isolation technology is essential.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"68 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114023748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-06-13DOI: 10.1109/VLSIT.2000.852753
R. Islam, S. Venkatesan, M. Woo, R. Nagabushnam, D. Denning, K. Yu, O. Adetutu, J. Farkas, T. Stephens, T. Sparks
In this work a 0.20 /spl mu/m CMOS technology has been developed using copper-filled local interconnect and contact along with copper metallization. This technology is suitable for logic and SRAM applications. The presence of copper in close proximity to the gate oxide and source/drain regions does not induce any degradation to the transistor parameters. This study shows that copper, along with a robust diffusion barrier, can be used to fill local interconnect and contact holes without deteriorating device performance. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.63 /spl mu/m.
{"title":"A 0.20 /spl mu/m CMOS technology with copper-filled contact and local interconnect","authors":"R. Islam, S. Venkatesan, M. Woo, R. Nagabushnam, D. Denning, K. Yu, O. Adetutu, J. Farkas, T. Stephens, T. Sparks","doi":"10.1109/VLSIT.2000.852753","DOIUrl":"https://doi.org/10.1109/VLSIT.2000.852753","url":null,"abstract":"In this work a 0.20 /spl mu/m CMOS technology has been developed using copper-filled local interconnect and contact along with copper metallization. This technology is suitable for logic and SRAM applications. The presence of copper in close proximity to the gate oxide and source/drain regions does not induce any degradation to the transistor parameters. This study shows that copper, along with a robust diffusion barrier, can be used to fill local interconnect and contact holes without deteriorating device performance. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.63 /spl mu/m.","PeriodicalId":268624,"journal":{"name":"2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132032391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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