In this paper, a brick-based rotary oscillator array (ROA) synchronization scheme is proposed, which directs all the rotary traveling wave oscillators (RTWOs) in the ROA to rotate in a pre-determined direction. This synchronization scheme increases the speed of the ROA synchronization process by eliminating the repetitive start-up trials due to start-ups from incorrect points on the oscillatory array. Simulation results confirm the effectiveness of the ROA synchronization scheme. Furthermore, the synchronization scheme is applied to an ROA-based clock generation and distribution network designed for an ISPD 10 clock benchmark in order to demonstrate its application at a larger scale.
{"title":"Synchronization scheme for brick-based rotary oscillator arrays","authors":"Y. Teng, B. Taskin","doi":"10.1145/2206781.2206812","DOIUrl":"https://doi.org/10.1145/2206781.2206812","url":null,"abstract":"In this paper, a brick-based rotary oscillator array (ROA) synchronization scheme is proposed, which directs all the rotary traveling wave oscillators (RTWOs) in the ROA to rotate in a pre-determined direction. This synchronization scheme increases the speed of the ROA synchronization process by eliminating the repetitive start-up trials due to start-ups from incorrect points on the oscillatory array. Simulation results confirm the effectiveness of the ROA synchronization scheme. Furthermore, the synchronization scheme is applied to an ROA-based clock generation and distribution network designed for an ISPD 10 clock benchmark in order to demonstrate its application at a larger scale.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"14 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114031419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Noise such as voltage drop and temperature in integrated circuits can cause significant performance variation and even functional failure in lower technology nodes. In this paper, we propose a light-weight on-chip sensor that measures timing uncertainty induced by noise during functional and test operations. The proposed on-chip structure facilitates speed characterization under various workloads and test conditions. Simulation results show that it offers very high sensitivity to noise even under variations. The structure requires negligible area in the chip.
{"title":"TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations","authors":"Shuo Wang, M. Tehranipoor","doi":"10.1145/2206781.2206826","DOIUrl":"https://doi.org/10.1145/2206781.2206826","url":null,"abstract":"Noise such as voltage drop and temperature in integrated circuits can cause significant performance variation and even functional failure in lower technology nodes. In this paper, we propose a light-weight on-chip sensor that measures timing uncertainty induced by noise during functional and test operations. The proposed on-chip structure facilitates speed characterization under various workloads and test conditions. Simulation results show that it offers very high sensitivity to noise even under variations. The structure requires negligible area in the chip.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126313478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Piotr Patronik, Krzysztof S. Berezowski, J. Biernat, S. Piestrak, Aviral Shrivastava
In this paper, we present a new residue number system (RNS) {2n-1, 2n, 2n+1, 2n+1+1, 2n-1+1} of five well-balanced moduli that are co-prime for odd n. This new RNS complements the 5-moduli RNS system proposed before for even n {2n-1, 2n, 2n+1, 2n+1-1, 2n-1-1}. With the new set, we also present a novel approach to designing multi-moduli reverse converters that focuses strongly on critical path analysis and aims at strongly on moving a significant amount of computations off the critical path. The synthesis of the resulting design over the ST Microelectronics 65nm LP library demonstrates that the delay, area, and power characteristics improve the performance and power consumption of the existing complementary 5-moduli set.
{"title":"Design of an RNS reverse converter for a new five-moduli special set","authors":"Piotr Patronik, Krzysztof S. Berezowski, J. Biernat, S. Piestrak, Aviral Shrivastava","doi":"10.1145/2206781.2206799","DOIUrl":"https://doi.org/10.1145/2206781.2206799","url":null,"abstract":"In this paper, we present a new residue number system (RNS) {2<sup><i>n</i></sup>-1, 2<i>n</i>, 2<sup><i>n</i></sup>+1, 2<sup><i>n</i>+1</sup>+1, 2<sup><i>n</i>-1</sup>+1} of five well-balanced moduli that are co-prime for odd n. This new RNS complements the 5-moduli RNS system proposed before for even <i>n</i> {2<sup><i>n</i></sup>-1, 2<sup><i>n</i></sup>, 2<sup><i>n</i></sup>+1, 2<sup><i>n</i>+1</sup>-1, 2<sup><i>n</i>-1</sup>-1}. With the new set, we also present a novel approach to designing multi-moduli reverse converters that focuses strongly on critical path analysis and aims at strongly on moving a significant amount of computations off the critical path. The synthesis of the resulting design over the ST Microelectronics 65nm LP library demonstrates that the delay, area, and power characteristics improve the performance and power consumption of the existing complementary 5-moduli set.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134504936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents an approach for including energy consumption information in high-level modeling of active linear electrical circuits. The method introduced here proposes to start from a description of the system at a high-level of abstraction (transfer function or state space model) and refine it in order to generate the electrical circuit corresponding, in the form of a SPICE netlist, for example. The following steps of the proposed approach automatically extract the state space representation corresponding to this circuit. During the state space representation extraction, the information needed to find the power consumption is regarded as an output of the state space model. These outputs allow an instantaneous monitoring of the power consumption of the system at a high-level of abstraction. SystemC AMS has been used to model and simulate the examples presented in this paper.
{"title":"High-level modeling of power consumption in active linear analog circuits","authors":"L. Bousquet, E. Simeu","doi":"10.1145/2206781.2206804","DOIUrl":"https://doi.org/10.1145/2206781.2206804","url":null,"abstract":"This work presents an approach for including energy consumption information in high-level modeling of active linear electrical circuits. The method introduced here proposes to start from a description of the system at a high-level of abstraction (transfer function or state space model) and refine it in order to generate the electrical circuit corresponding, in the form of a SPICE netlist, for example. The following steps of the proposed approach automatically extract the state space representation corresponding to this circuit. During the state space representation extraction, the information needed to find the power consumption is regarded as an output of the state space model. These outputs allow an instantaneous monitoring of the power consumption of the system at a high-level of abstraction. SystemC AMS has been used to model and simulate the examples presented in this paper.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133878886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young
Link based non-tree clock network is an effective and economic way to reduce clock skew caused by variations. However, it is still an open topic where links should be inserted in order to achieve largest skew reduction with smaller extra resources. We propose a new method using linear program to solve this problem in this paper. In our approach, clock skew in a non-tree clock network is computed using the delay model in [13] and the information is used to select the node pairs for link insertion. Tradeoff between crosslink length and skew reduction effect is explored. Based on the analysis, we propose a new algorithm to insert crosslinks into a clock network. We compare our work with the method in [1] and a recent work [4] which inserts links between internal nodes of a tree. Experiments show that our method can reduce skew under variations effectively.
{"title":"Crosslink insertion for variation-driven clock network construction","authors":"Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young","doi":"10.1145/2206781.2206860","DOIUrl":"https://doi.org/10.1145/2206781.2206860","url":null,"abstract":"Link based non-tree clock network is an effective and economic way to reduce clock skew caused by variations. However, it is still an open topic where links should be inserted in order to achieve largest skew reduction with smaller extra resources. We propose a new method using linear program to solve this problem in this paper. In our approach, clock skew in a non-tree clock network is computed using the delay model in [13] and the information is used to select the node pairs for link insertion. Tradeoff between crosslink length and skew reduction effect is explored. Based on the analysis, we propose a new algorithm to insert crosslinks into a clock network. We compare our work with the method in [1] and a recent work [4] which inserts links between internal nodes of a tree. Experiments show that our method can reduce skew under variations effectively.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133635564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heterogeneous multicore system-on-chips (MPSoCs) provide many degrees of freedom to map functionalities on either SW and HW components. In this scenario, enabling the remapping of HW IPs as SW routines allows to fully exploit the computation power and flexibility provided by heterogeneous MPSoCs. On the other hand, reuse of existent IP cores is the key strategy to explore this large design space in a reasonable amount of time and to reduce the error risk during the MPSoC design flow. A methodology for automatic generation of parallel SW code taking into account these aspects is currently missing. This paper aims at overcoming this limitation, by presenting a methodology to automatically generate parallel SW IPs starting from existent RTL IP models.
{"title":"On the automatic synthesis of parallel SW from RTL models of hardware IPs","authors":"A. Acquaviva, N. Bombieri, F. Fummi, S. Vinco","doi":"10.1145/2206781.2206800","DOIUrl":"https://doi.org/10.1145/2206781.2206800","url":null,"abstract":"Heterogeneous multicore system-on-chips (MPSoCs) provide many degrees of freedom to map functionalities on either SW and HW components. In this scenario, enabling the remapping of HW IPs as SW routines allows to fully exploit the computation power and flexibility provided by heterogeneous MPSoCs. On the other hand, reuse of existent IP cores is the key strategy to explore this large design space in a reasonable amount of time and to reduce the error risk during the MPSoC design flow. A methodology for automatic generation of parallel SW code taking into account these aspects is currently missing. This paper aims at overcoming this limitation, by presenting a methodology to automatically generate parallel SW IPs starting from existent RTL IP models.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"608 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121984523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The memristor (M) is considered to be the fourth two-terminal passive element in electronics, alongside the resistor (R), the capacitor (C), and the inductor (L). Its existence was postulated in 1971 but its first implementation was reported in 2008. Where was it hiding all that time and what can we do with it? Come and learn how the memristor completes the roster of electronic devices much like a missing particle that physicists seek to complete their tableaus.
{"title":"Memristor: the illusive device","authors":"K. Salama","doi":"10.1145/2206781.2206831","DOIUrl":"https://doi.org/10.1145/2206781.2206831","url":null,"abstract":"The memristor (M) is considered to be the fourth two-terminal passive element in electronics, alongside the resistor (R), the capacitor (C), and the inductor (L). Its existence was postulated in 1971 but its first implementation was reported in 2008. Where was it hiding all that time and what can we do with it? Come and learn how the memristor completes the roster of electronic devices much like a missing particle that physicists seek to complete their tableaus.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116809050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Flip-flop (FF)/latch-based design has advantages on such as area and power compared to single register-type design (only FFs or latches). Considering FF/latch-based design at high-level synthesis is necessary, because resource binding process significantly affects the quality of resulting circuits. A major downside of FF/latch-based design is the increase in resources (functional units and registers) due to the modification of the lifetimes of operations and data. Therefore, as a first step, this paper addresses the datapath design problem in which resource binding and register-type selection are simultaneously optimized for resource optimization. An efficient comprehensive framework is presented, which has flexibility to incorporate other design objectives. Experiments show that the proposed approach can generate resource-efficient FF/latch-based datapaths.
{"title":"Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis","authors":"Keisuke Inoue, M. Kaneko","doi":"10.1145/2206781.2206802","DOIUrl":"https://doi.org/10.1145/2206781.2206802","url":null,"abstract":"Flip-flop (FF)/latch-based design has advantages on such as area and power compared to single register-type design (only FFs or latches). Considering FF/latch-based design at high-level synthesis is necessary, because resource binding process significantly affects the quality of resulting circuits. A major downside of FF/latch-based design is the increase in resources (functional units and registers) due to the modification of the lifetimes of operations and data. Therefore, as a first step, this paper addresses the datapath design problem in which resource binding and register-type selection are simultaneously optimized for resource optimization. An efficient comprehensive framework is presented, which has flexibility to incorporate other design objectives. Experiments show that the proposed approach can generate resource-efficient FF/latch-based datapaths.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"475 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116876319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an on-chip programmable voltage reference circuit whereat the main block, the switchable resistor array, was realized using four different layout styles. These different layouts, which result in different complexity and chip area consumptions, are analyzed regarding the influence on the calibration performance of the voltage reference circuit. Although a slight difference can be measured, there is no clear preference for one of the four layout versions. In contrast to the much smaller chip area of the more or less lumped approach (lay3) the distributed approach (lay0) shows only slight advantages in circuit performance.
{"title":"Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference","authors":"D. Gruber, T. Ostermann","doi":"10.1145/2206781.2206828","DOIUrl":"https://doi.org/10.1145/2206781.2206828","url":null,"abstract":"This paper presents an on-chip programmable voltage reference circuit whereat the main block, the switchable resistor array, was realized using four different layout styles. These different layouts, which result in different complexity and chip area consumptions, are analyzed regarding the influence on the calibration performance of the voltage reference circuit. Although a slight difference can be measured, there is no clear preference for one of the four layout versions. In contrast to the much smaller chip area of the more or less lumped approach (lay3) the distributed approach (lay0) shows only slight advantages in circuit performance.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128526156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose the use of voltage stacking for addressing some of the power delivery issues for many-core processors. To demonstrate the effectiveness of our method we first design a proxy for a many-core stacked processor in the form of a regular structure using multiple ring oscillators where we can control the voltage, frequency and switching activity for individual rings. For intermediate voltage rail regulation, we propose a push pull-based switched capacitor regulator designed specifically for balancing the stacked loads. Detailed Spice simulation results for the prototype model show a 4× reduction in supply current when using 4 layers of voltage stacking. We further validate our method by designing a voltage-stacked structure using two PIC cores.
{"title":"Breaking the power delivery wall using voltage stacking","authors":"K. Mazumdar, M. Stan","doi":"10.1145/2206781.2206795","DOIUrl":"https://doi.org/10.1145/2206781.2206795","url":null,"abstract":"We propose the use of voltage stacking for addressing some of the power delivery issues for many-core processors. To demonstrate the effectiveness of our method we first design a proxy for a many-core stacked processor in the form of a regular structure using multiple ring oscillators where we can control the voltage, frequency and switching activity for individual rings. For intermediate voltage rail regulation, we propose a push pull-based switched capacitor regulator designed specifically for balancing the stacked loads. Detailed Spice simulation results for the prototype model show a 4× reduction in supply current when using 4 layers of voltage stacking. We further validate our method by designing a voltage-stacked structure using two PIC cores.","PeriodicalId":272619,"journal":{"name":"ACM Great Lakes Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126644324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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