Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027087
Indira Rawat, M. K. Gupta, Virendra Singh
The semiconductor industry is always looking for some new technology in order to house the ever increasing number of devices in as small area as possible. One such solution is offered by the three dimensional SoCs which is vertical stacking of the various dies. It also has associated with it various challenges and constraints which need to be overcome before its adoption. Power density is also increasing, resuling in increased heat as more and more functions are being realised in a single chip. Cooling methods have to be adopted. Again testing results in more heat generation than functional mode of the chip. In this paper we have tried to analyze the effect of floorplanning on the maximum temperature. The benchmark circuit d695 has been taken and difference of temperature between various floorplans has been obtained. It shows here that the difference in temperature can be as high as 38K for a modified floorplan compared to original one.
{"title":"Temperature aware test scheduling by modified floorplanning","authors":"Indira Rawat, M. K. Gupta, Virendra Singh","doi":"10.1109/EWDTS.2014.7027087","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027087","url":null,"abstract":"The semiconductor industry is always looking for some new technology in order to house the ever increasing number of devices in as small area as possible. One such solution is offered by the three dimensional SoCs which is vertical stacking of the various dies. It also has associated with it various challenges and constraints which need to be overcome before its adoption. Power density is also increasing, resuling in increased heat as more and more functions are being realised in a single chip. Cooling methods have to be adopted. Again testing results in more heat generation than functional mode of the chip. In this paper we have tried to analyze the effect of floorplanning on the maximum temperature. The benchmark circuit d695 has been taken and difference of temperature between various floorplans has been obtained. It shows here that the difference in temperature can be as high as 38K for a modified floorplan compared to original one.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115010790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027081
J. Dostál, V. Smotlacha
This paper deals with an accurate time transfer and atomic clocks comparison in a geographically distant locations utilizing the optical lines. A new dual interpolating counter architecture for the clock comparison over an optical network is presented, especially utilizing dense wavelength division multiplexing (DWDM). There are described the time transfer method and the details of the interpolating counter implementation (the interpolator feed and the run time interpolator calibration). Experiences with the current embedded time interval counter design in the FPGA are presented as well.
{"title":"Dual interpolating counter architecture for atomic clock comparison","authors":"J. Dostál, V. Smotlacha","doi":"10.1109/EWDTS.2014.7027081","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027081","url":null,"abstract":"This paper deals with an accurate time transfer and atomic clocks comparison in a geographically distant locations utilizing the optical lines. A new dual interpolating counter architecture for the clock comparison over an optical network is presented, especially utilizing dense wavelength division multiplexing (DWDM). There are described the time transfer method and the details of the interpolating counter implementation (the interpolator feed and the run time interpolator calibration). Experiences with the current embedded time interval counter design in the FPGA are presented as well.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027046
N. Prokopenko, P. Budyakov, N. Butyrlagin
The paper reviews the features of the advanced high-frequency correction circuit for the resistive voltage dividers (attenuators, AT) operating on the capacitive load. The effect of the constant cutoff frequency of considered AT is shown at changing transfer ratio in a wide range. This feature of the considered circuit is the main advantage over the classical AT implementation for the analog-to-digital converters, telecommunication line drivers and other.
{"title":"The correction circuits for the broadband resistive voltage dividers with the capacitive load","authors":"N. Prokopenko, P. Budyakov, N. Butyrlagin","doi":"10.1109/EWDTS.2014.7027046","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027046","url":null,"abstract":"The paper reviews the features of the advanced high-frequency correction circuit for the resistive voltage dividers (attenuators, AT) operating on the capacitive load. The effect of the constant cutoff frequency of considered AT is shown at changing transfer ratio in a wide range. This feature of the considered circuit is the main advantage over the classical AT implementation for the analog-to-digital converters, telecommunication line drivers and other.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125655033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027107
V. Hahanov, W. Gharibi, L. Abramova, S. Chumachenko, E. Litvinova, A. Hahanova, Vladimir Rustinov, Vladimir Miz, A. Zhalilo, Artur Ziarmand
A cyber physical system for smart cloud traffic control is proposed. It is an intellectual (smart) road infrastructure for monitoring and control of traffic in real-time through the use of global systems for positioning and navigation, mobile gadgets and the Internet in order to improve the quality and safety of vehicle movement, as well as for minimizing the time and costs when vehicles are moved at the specified routes. The main innovative idea is step-by-step transfer of traffic lights from the ground to a virtual cloud space for vehicle management, equipped with a mobile gadget or computer, which displays on the screen map, route, coordinates of the road user and real traffic signals. A set of innovative technologies to address the social, humanitarian, economic, energy, insurance, crime and environmental problems through the creation and application of cloud-based digital traffic monitoring and management is developed. All of these technologies and functional components are integrated into the system automaton model of cyber physical system for interaction between an infrastructure cloud of exact monitoring and digital control and vehicle gadget or computer.
{"title":"Cyber physical system - smart cloud traffic control","authors":"V. Hahanov, W. Gharibi, L. Abramova, S. Chumachenko, E. Litvinova, A. Hahanova, Vladimir Rustinov, Vladimir Miz, A. Zhalilo, Artur Ziarmand","doi":"10.1109/EWDTS.2014.7027107","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027107","url":null,"abstract":"A cyber physical system for smart cloud traffic control is proposed. It is an intellectual (smart) road infrastructure for monitoring and control of traffic in real-time through the use of global systems for positioning and navigation, mobile gadgets and the Internet in order to improve the quality and safety of vehicle movement, as well as for minimizing the time and costs when vehicles are moved at the specified routes. The main innovative idea is step-by-step transfer of traffic lights from the ground to a virtual cloud space for vehicle management, equipped with a mobile gadget or computer, which displays on the screen map, route, coordinates of the road user and real traffic signals. A set of innovative technologies to address the social, humanitarian, economic, energy, insurance, crime and environmental problems through the creation and application of cloud-based digital traffic monitoring and management is developed. All of these technologies and functional components are integrated into the system automaton model of cyber physical system for interaction between an infrastructure cloud of exact monitoring and digital control and vehicle gadget or computer.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125482401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027092
V. Gorbachov
The paper addresses the threat to the security of using electronic systems, which may include malicious inclusions. The action classification of malicious hardware (MH) is given. The MH formal models, as well as formal model of unauthorized access, executed by MH, are based on the subject-object concept.
{"title":"Malicious hardware: Characteristics, classification and formal models","authors":"V. Gorbachov","doi":"10.1109/EWDTS.2014.7027092","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027092","url":null,"abstract":"The paper addresses the threat to the security of using electronic systems, which may include malicious inclusions. The action classification of malicious hardware (MH) is given. The MH formal models, as well as formal model of unauthorized access, executed by MH, are based on the subject-object concept.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124236763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027095
A. Banerjee, D. K. Das
Digital multipliers are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. But the implementation of squaring has the advantage that we can avoid the generation of many partial products used in multipliers by eliminating the redundant bits, thus resulting the circuit to be simpler with less hardware, propagation delay and power consumption. Our work proposes two designs of dedicated squaring techniques in reversible circuits. We use the recursion to achieve our design. The design for n bits is recursively obtained by appending some extra circuitry with the design for (n-1) bits. Our techniques make optimum use of ancillary inputs, garbage outputs and quantum cost and compare favourably with the recent work [1] in this area. Both the designs are having modular structures and can be systemically designed.
{"title":"Squaring in reversible logic using iterative structure","authors":"A. Banerjee, D. K. Das","doi":"10.1109/EWDTS.2014.7027095","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027095","url":null,"abstract":"Digital multipliers are indispensable in Digital signal processing and cryptography. In many mathematical computations, squaring and cubing are frequently used. Generally the multiplier is used in computing square. But the implementation of squaring has the advantage that we can avoid the generation of many partial products used in multipliers by eliminating the redundant bits, thus resulting the circuit to be simpler with less hardware, propagation delay and power consumption. Our work proposes two designs of dedicated squaring techniques in reversible circuits. We use the recursion to achieve our design. The design for n bits is recursively obtained by appending some extra circuitry with the design for (n-1) bits. Our techniques make optimum use of ancillary inputs, garbage outputs and quantum cost and compare favourably with the recent work [1] in this area. Both the designs are having modular structures and can be systemically designed.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132842728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027080
V. Lesnikov, T. Naumovich, A. Chastikov
Criterion for the BIBO stability of the IIR digital filters is well known. IIR filter is BIBO stable if and only if all of its poles are strictly inside the unit circle in the complex z-plane. To analyze the stability of biquad filters in the space of coefficients is constructed the famous “triangle of stability”. In this paper, this criterion extends on third order IIR digital filters.
{"title":"The formulation of criteria of BIBO stability of 3rd-order IIR digital filters in space of coefficients of a denominator of transfer function","authors":"V. Lesnikov, T. Naumovich, A. Chastikov","doi":"10.1109/EWDTS.2014.7027080","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027080","url":null,"abstract":"Criterion for the BIBO stability of the IIR digital filters is well known. IIR filter is BIBO stable if and only if all of its poles are strictly inside the unit circle in the complex z-plane. To analyze the stability of biquad filters in the space of coefficients is constructed the famous “triangle of stability”. In this paper, this criterion extends on third order IIR digital filters.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027044
Manjari Pradhan, D. K. Das, C. Giri, H. Rahaman
System-on-a-chip (SOC) uses embedded cores those require a test architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach may also be used for testing of three dimensional stacked integrated circuits (SICs) based on through silicon vias (TSVs). This paper presents an algorithm for minimizing the post bond test time for 3D core-based SOCs under the constraints on the number of TSVs and the available TAM width. Given a TAM width available to test a system-on-a-chip, our algorithm partitions this width into two groups and places the cores of these groups in two layers in 3D design with the goal to optimize the total test time. The experimental results establish the effectiveness of our algorithm.
{"title":"Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning","authors":"Manjari Pradhan, D. K. Das, C. Giri, H. Rahaman","doi":"10.1109/EWDTS.2014.7027044","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027044","url":null,"abstract":"System-on-a-chip (SOC) uses embedded cores those require a test architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. This approach may also be used for testing of three dimensional stacked integrated circuits (SICs) based on through silicon vias (TSVs). This paper presents an algorithm for minimizing the post bond test time for 3D core-based SOCs under the constraints on the number of TSVs and the available TAM width. Given a TAM width available to test a system-on-a-chip, our algorithm partitions this width into two groups and places the cores of these groups in two layers in 3D design with the goal to optimize the total test time. The experimental results establish the effectiveness of our algorithm.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115573362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027069
S. Krutchinsky, N. Prokopenko, P. Budyakov, V. Yugai
Microwave selective amplifiers (SA) with paraphase output that provide high Q-factor and voltage gain (K0) on quasi-resonance frequency f0 at low parametric sensibility are considered. The results of the mathematical analysis and simulation of SA on 0.25 μm SiGe process are given. Presented SA, along with selective properties has phase splitter feature and allow current control of Q-factor.
{"title":"Microwave selective amplifiers with paraphase output","authors":"S. Krutchinsky, N. Prokopenko, P. Budyakov, V. Yugai","doi":"10.1109/EWDTS.2014.7027069","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027069","url":null,"abstract":"Microwave selective amplifiers (SA) with paraphase output that provide high Q-factor and voltage gain (K0) on quasi-resonance frequency f0 at low parametric sensibility are considered. The results of the mathematical analysis and simulation of SA on 0.25 μm SiGe process are given. Presented SA, along with selective properties has phase splitter feature and allow current control of Q-factor.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114789923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027089
Olga Yanovskaya, M. Yanovsky, V. Kharchenko
The article focuses on the energy efficiency issue and the negative impact on the environment of Cloud computing based on data centers infrastructure. A modernization of Cloud architecture in terms of Green computing is proposed, using FPGA hardware accelerators and distributed peer-to-peer networks. Customer and FPGA as a Service (FAAS) interaction scenarios are discussed. A distributed peer-to-peer Cloud architecture is suggested. The energy efficiency analysis of the proposed architectures shows its advantages.
{"title":"The concept of green Cloud infrastructure based on distributed computing and hardware accelerator within FPGA as a Service","authors":"Olga Yanovskaya, M. Yanovsky, V. Kharchenko","doi":"10.1109/EWDTS.2014.7027089","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027089","url":null,"abstract":"The article focuses on the energy efficiency issue and the negative impact on the environment of Cloud computing based on data centers infrastructure. A modernization of Cloud architecture in terms of Green computing is proposed, using FPGA hardware accelerators and distributed peer-to-peer networks. Customer and FPGA as a Service (FAAS) interaction scenarios are discussed. A distributed peer-to-peer Cloud architecture is suggested. The energy efficiency analysis of the proposed architectures shows its advantages.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125891135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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