Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027052
P. Oleynik
This article describes an object-oriented design process of simple database application in terms of object system metamodel assuming the construction of conceptual, logical and physical models.
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Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027062
V. Kureichik, V. Kureichik, D. Zaruba
One of the most important design problems - electronic computing equipment (ECE) schemes components partitioning problem is considered in the article. It belongs to the class of NP-hard problems. Statement of a partitioning problem and an optimization criterion are defined. A new approach for solving partitioning problem based on the modified graph coloring algorithm is suggested. The modified partitioning algorithm which provides obtained solutions of a specified accuracy in polynomial time is developed. A modified graph coloring heuristic is described. Authors suggested a procedure for the transition from colored subsets to specify parts of the partition. The program environment and computing experiment are implemented. The series of tests and experiments have allowed specifying theoretical estimations of partitioning algorithms running time. The running time of the algorithm is represented as O (n2).
{"title":"Partitioning of ECE schemes components based on modified graph coloring algorithm","authors":"V. Kureichik, V. Kureichik, D. Zaruba","doi":"10.1109/EWDTS.2014.7027062","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027062","url":null,"abstract":"One of the most important design problems - electronic computing equipment (ECE) schemes components partitioning problem is considered in the article. It belongs to the class of NP-hard problems. Statement of a partitioning problem and an optimization criterion are defined. A new approach for solving partitioning problem based on the modified graph coloring algorithm is suggested. The modified partitioning algorithm which provides obtained solutions of a specified accuracy in polynomial time is developed. A modified graph coloring heuristic is described. Authors suggested a procedure for the transition from colored subsets to specify parts of the partition. The program environment and computing experiment are implemented. The series of tests and experiments have allowed specifying theoretical estimations of partitioning algorithms running time. The running time of the algorithm is represented as O (n2).","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131618490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027041
Vahid Janfaza, Paniz Foroutan, B. Forouzandeh, M. Haghbayan
Sequential circuit testing has been recognized as one of the most difficult problems in the area of fault detection. Controllability and observability of a sequential circuit is low because of their internal states. Therefore finding suitable sequence of test patterns is becoming increasingly complex. We have proposed a method to estimate an expectation graph by utilizing a mathematical model which exploits probabilistic 4-value system. The expectation graph is used to determine the minimum number of faults detected by a suitable sequence of test patterns. Experimental results show our mathematical model has reduced number of test patterns in specified fault coverage.
{"title":"A mathematical model for estimating acceptable ratio of test patterns","authors":"Vahid Janfaza, Paniz Foroutan, B. Forouzandeh, M. Haghbayan","doi":"10.1109/EWDTS.2014.7027041","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027041","url":null,"abstract":"Sequential circuit testing has been recognized as one of the most difficult problems in the area of fault detection. Controllability and observability of a sequential circuit is low because of their internal states. Therefore finding suitable sequence of test patterns is becoming increasingly complex. We have proposed a method to estimate an expectation graph by utilizing a mathematical model which exploits probabilistic 4-value system. The expectation graph is used to determine the minimum number of faults detected by a suitable sequence of test patterns. Experimental results show our mathematical model has reduced number of test patterns in specified fault coverage.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128378597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-11-25DOI: 10.1109/EWDTS.2014.7027040
Vahid Janfaza, B. Forouzandeh, Payman Behnam, M. Najafi
In spite of significant efforts in circuit testing, sequential circuit testing has remained a challenging problem. Existing test solutions like scan methods are proposed to facilitate Automatic Test Pattern Generation (ATPG), however, these methods suffer from large area and delay overhead. In this paper, a new hybrid history-based test overlapping method is presented to reduce test time in scan-based sequential circuits while almost no extra hardware overhead is imposed to the circuit. Experimental results show 30% reduction on average test time in comparison with existing works.
{"title":"Hybrid history-based test overlapping to reduce test application time","authors":"Vahid Janfaza, B. Forouzandeh, Payman Behnam, M. Najafi","doi":"10.1109/EWDTS.2014.7027040","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027040","url":null,"abstract":"In spite of significant efforts in circuit testing, sequential circuit testing has remained a challenging problem. Existing test solutions like scan methods are proposed to facilitate Automatic Test Pattern Generation (ATPG), however, these methods suffer from large area and delay overhead. In this paper, a new hybrid history-based test overlapping method is presented to reduce test time in scan-based sequential circuits while almost no extra hardware overhead is imposed to the circuit. Experimental results show 30% reduction on average test time in comparison with existing works.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130198862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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