Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027071
V. Melikyan, A. Sahakyan, Mikayel Piloyan, G. Hovhannisyan, Aram Shishmanyan, T. Hovhannisyan, Davit Trdatyan
A method of resistance calibration without external precision elements usage presented in paper. In the proposed method, used structures which operation based on technologically accurate elements and signals to have high accuracy resistance after calibration. Architecture produces a calibration code corresponding to 50Ohms PVT compensated termination impedance, which is needed to avoid reflections in transmission lines. Standard calibration methods using external ~1% accuracy precision discreet resistance (50 or 200Ohms). The presented calibration mechanism using internal elements and can provide ~ 4-7% accuracy of calibration. Method can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.
本文提出了一种无需外部精密元件的电阻校准方法。在该方法中，采用基于技术精确元件和信号运行的结构，校正后具有较高的精度电阻。架构产生对应于50欧姆PVT补偿终端阻抗的校准代码，该代码需要避免传输线中的反射。标准校准方法采用外部~1%精度的离散电阻(50或200欧姆)。所提出的校准机构采用内部元件，可提供~ 4-7%的校准精度。该方法可用于PCI (Peripheral Component Interconnect)、USB (Universal Serial Bus)、DDR (Double Data Rate)等标准的特殊输入/输出电路。
{"title":"Resistance calibration method without external precision elements","authors":"V. Melikyan, A. Sahakyan, Mikayel Piloyan, G. Hovhannisyan, Aram Shishmanyan, T. Hovhannisyan, Davit Trdatyan","doi":"10.1109/EWDTS.2014.7027071","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027071","url":null,"abstract":"A method of resistance calibration without external precision elements usage presented in paper. In the proposed method, used structures which operation based on technologically accurate elements and signals to have high accuracy resistance after calibration. Architecture produces a calibration code corresponding to 50Ohms PVT compensated termination impedance, which is needed to avoid reflections in transmission lines. Standard calibration methods using external ~1% accuracy precision discreet resistance (50 or 200Ohms). The presented calibration mechanism using internal elements and can provide ~ 4-7% accuracy of calibration. Method can be used in the special input/output circuits of several standards such as Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Double Data Rate (DDR) etc.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128274027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027106
Yu. M. Ryabukha, V. Krivonos, A. Hahanova
It is proposed to introduce new methods of video data compression for more efficient use of wireless technology. Therefore, we propose the method of reconstructing digital static images based on the restoration of transforms. There is a technology of renovating values of vector of significant subbands of the nonuniform DCT spectrum on a known code and base; the vector of scaling components based on the decoding of the first zero series and Bodo codes; low-frequency DC component using a statistical code. The decompression method proposed allows restoring an image without making the information loss for a given confidence level.
{"title":"Video decompression technology in information and communication technologies","authors":"Yu. M. Ryabukha, V. Krivonos, A. Hahanova","doi":"10.1109/EWDTS.2014.7027106","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027106","url":null,"abstract":"It is proposed to introduce new methods of video data compression for more efficient use of wireless technology. Therefore, we propose the method of reconstructing digital static images based on the restoration of transforms. There is a technology of renovating values of vector of significant subbands of the nonuniform DCT spectrum on a known code and base; the vector of scaling components based on the decoding of the first zero series and Bodo codes; low-frequency DC component using a statistical code. The decompression method proposed allows restoring an image without making the information loss for a given confidence level.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129734506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027053
D. Zaporozhets, D. Zaruba, V. Kureichik
The VLSI placement problem is presented in this article. A mechanism of representation of solutions for further genetic algorithm implementation is described. The proposed encoding algorithm is based on a placement tree and reverse Polish notation. The decoding algorithm is implemented in two stages: twinning of elements in macroblocks and calculation of real coordinates of elements. Experimental results show time-response characteristics of the proposed coding and decoding mechanisms. The time complexity of the encoding algorithm is represented by O(n) whereas the time complexity of the decoding algorithm is represented by O(n log n), where n is the number of elements.
{"title":"Representation of solutions in genetic VLSI placement algorithms","authors":"D. Zaporozhets, D. Zaruba, V. Kureichik","doi":"10.1109/EWDTS.2014.7027053","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027053","url":null,"abstract":"The VLSI placement problem is presented in this article. A mechanism of representation of solutions for further genetic algorithm implementation is described. The proposed encoding algorithm is based on a placement tree and reverse Polish notation. The decoding algorithm is implemented in two stages: twinning of elements in macroblocks and calculation of real coordinates of elements. Experimental results show time-response characteristics of the proposed coding and decoding mechanisms. The time complexity of the encoding algorithm is represented by O(n) whereas the time complexity of the decoding algorithm is represented by O(n log n), where n is the number of elements.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122366966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027061
V. Sargsyan
Built-in Self-Test (BIST) and Built-In Self-Repair (BISR) have been widely used for embedded memories test and repair purposes. One of the disadvantages of these circuits is the memory repair signature delivery process at what is typically known as hard repair flow. In this paper, a memory repair signature loading mechanism is introduced, which significantly reduces memory repair organization time.
{"title":"An efficient signature loading mechanism for memory repair","authors":"V. Sargsyan","doi":"10.1109/EWDTS.2014.7027061","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027061","url":null,"abstract":"Built-in Self-Test (BIST) and Built-In Self-Repair (BISR) have been widely used for embedded memories test and repair purposes. One of the disadvantages of these circuits is the memory repair signature delivery process at what is typically known as hard repair flow. In this paper, a memory repair signature loading mechanism is introduced, which significantly reduces memory repair organization time.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122582443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027054
K. Petrosyants, A. Kortunov, I. Kharitonov, A. Popov, Natalya Gomanilova, N. I. Rjabov
The temperature-current rise in modern (up to 100-150 microns wide) PCB traces is simulated using three software tools ANSYS, HyperLynxThermal and ELCUT. The results are compared with the IR measurements in PCB copper traces with different sizes and substrate materials. It is shown that ANSYS correctly describes the thermal behavior for all tests, other tools have some limitations for small size traces.
{"title":"Analysis and Simulation of temperature-current rise in modern PCB traces","authors":"K. Petrosyants, A. Kortunov, I. Kharitonov, A. Popov, Natalya Gomanilova, N. I. Rjabov","doi":"10.1109/EWDTS.2014.7027054","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027054","url":null,"abstract":"The temperature-current rise in modern (up to 100-150 microns wide) PCB traces is simulated using three software tools ANSYS, HyperLynxThermal and ELCUT. The results are compared with the IR measurements in PCB copper traces with different sizes and substrate materials. It is shown that ANSYS correctly describes the thermal behavior for all tests, other tools have some limitations for small size traces.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114138419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027112
V. Hahanov, S. A. Zaychenko, V. Varchenko
This article describes technology for diagnosis SoC HDL-models, based on Code-Flow Transaction Graph. Diagnosis method is focused to decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multi-tree of fault detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using test patterns; development of a method for analysis the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis.
{"title":"Method for diagnosing SoC HDL-code","authors":"V. Hahanov, S. A. Zaychenko, V. Varchenko","doi":"10.1109/EWDTS.2014.7027112","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027112","url":null,"abstract":"This article describes technology for diagnosis SoC HDL-models, based on Code-Flow Transaction Graph. Diagnosis method is focused to decrease the time of fault detection and memory for storage of diagnosis matrix by means of forming ternary relations between test, monitor, and functional component. The following problems are solved: creation of digital system model in the form of transaction graph and multi-tree of fault detection tables, as well as ternary matrices for activating functional components of the selected set of monitors by using test patterns; development of a method for analysis the activation matrix to detect the faulty blocks with given depth and synthesis logic functions for subsequent embedded hardware fault diagnosis.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125007725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027056
V. Sapozhnikov, V. Sapozhnikov, D. Efanov, A. Blyudov
In this paper authors consider the problem of concurrent error detection (CED) system of combinational circuit with unidirectionally independent outputs design using modulo codes with the summation. Considering of error detection features of modulo codes with the summation allows designing CED systems with reduced complexity comparing with the ones based on the classic Berger code. Authors determine conditions of application of modulo codes with the summation for CED system of combinational circuit with unidirectionally independent outputs design.
{"title":"On the synthesis of unidirectional combinational circuits detecting all single faults","authors":"V. Sapozhnikov, V. Sapozhnikov, D. Efanov, A. Blyudov","doi":"10.1109/EWDTS.2014.7027056","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027056","url":null,"abstract":"In this paper authors consider the problem of concurrent error detection (CED) system of combinational circuit with unidirectionally independent outputs design using modulo codes with the summation. Considering of error detection features of modulo codes with the summation allows designing CED systems with reduced complexity comparing with the ones based on the classic Berger code. Authors determine conditions of application of modulo codes with the summation for CED system of combinational circuit with unidirectionally independent outputs design.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122392777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027093
S. Krutchinsky, E. A. Zhebrun
A procedure for testing the pulse-potential ADC, aimed at minimizing the analog sections zero drift impact on input signal conversion accuracy is proposed. The procedure is based on the basic properties of the ADC - quantization of energy. It is shown that introduced testing phases allows to determine the binary words that are corrective in common additive sequence of measured quantity calculation and not increasing its sensitivity. Parametric conditions for the method applicability that justifies the need of support circuit design tasks solutions are formulated.
{"title":"Selftest ADCs for smart sensors","authors":"S. Krutchinsky, E. A. Zhebrun","doi":"10.1109/EWDTS.2014.7027093","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027093","url":null,"abstract":"A procedure for testing the pulse-potential ADC, aimed at minimizing the analog sections zero drift impact on input signal conversion accuracy is proposed. The procedure is based on the basic properties of the ADC - quantization of energy. It is shown that introduced testing phases allows to determine the binary words that are corrective in common additive sequence of measured quantity calculation and not increasing its sensitivity. Parametric conditions for the method applicability that justifies the need of support circuit design tasks solutions are formulated.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123029201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027084
E. Kuliev, A. N. Dukkardt, V. Kureychik, Andrey A. Legebokov
The article discusses the key problem of swarm algorithms and the bioinspired approach, which is to determine the proximity function and study the emerging neighborhoods in order to solve optimization problems. There is a detailed discussion of one of the most important design phases, namely, the VLSI components placement problem, whose solutions fineness directly affects the quality of circuit tracing. The solution of the neighborhoods and solution proximity problem is demonstrated by the study of the solutions by means of hybrid search methods. The main idea of this approach is the sequential use of genetic and swarm algorithms. We propose a new formation principle of the positions' neighborhood in the solution space based on the bee colony algorithm, which uses the concept of neighborhood in a circular search space. There are also experimental studies which show that the time complexity of the developed approach does not go beyond polynomial dependence.
{"title":"Neighborhood research approach in swarm intelligence for solving the optimization problems","authors":"E. Kuliev, A. N. Dukkardt, V. Kureychik, Andrey A. Legebokov","doi":"10.1109/EWDTS.2014.7027084","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027084","url":null,"abstract":"The article discusses the key problem of swarm algorithms and the bioinspired approach, which is to determine the proximity function and study the emerging neighborhoods in order to solve optimization problems. There is a detailed discussion of one of the most important design phases, namely, the VLSI components placement problem, whose solutions fineness directly affects the quality of circuit tracing. The solution of the neighborhoods and solution proximity problem is demonstrated by the study of the solutions by means of hybrid search methods. The main idea of this approach is the sequential use of genetic and swarm algorithms. We propose a new formation principle of the positions' neighborhood in the solution space based on the bee colony algorithm, which uses the concept of neighborhood in a circular search space. There are also experimental studies which show that the time complexity of the developed approach does not go beyond polynomial dependence.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121278950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-01DOI: 10.1109/EWDTS.2014.7027075
L. Gladkov, N. V. Gladkova, S. Leiba
An important problem of manufacturing scheduling and planning is reviewed. Basic criteria and heuristic rules used in scheduling are considered. The method of manufacturing scheduling based on combining genetic algorithms and fuzzy controller are suggested. Some logical rules for fuzzy controller are specified, and the structure of proposed algorithm is explained. In order to show the effectiveness of suggested techniques computing experiments are performed.
{"title":"Manufacturing scheduling problem based on fuzzy genetic algorithm","authors":"L. Gladkov, N. V. Gladkova, S. Leiba","doi":"10.1109/EWDTS.2014.7027075","DOIUrl":"https://doi.org/10.1109/EWDTS.2014.7027075","url":null,"abstract":"An important problem of manufacturing scheduling and planning is reviewed. Basic criteria and heuristic rules used in scheduling are considered. The method of manufacturing scheduling based on combining genetic algorithms and fuzzy controller are suggested. Some logical rules for fuzzy controller are specified, and the structure of proposed algorithm is explained. In order to show the effectiveness of suggested techniques computing experiments are performed.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133707901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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