Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313268
S. Matui, M. Yamamoto, I. Kawasaki, S. Narita, F. Arakawa, K. Uchiyama
The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed, illustrating the effect of a pipe bypass mechanism and dedicated resident branch instruction caches. The benefit of microprogram-controlled instruction execution for high-speed execution of high-level language instructions is shown. Overall GMICRO/500 performance is evaluated in Dhrystones.<>
{"title":"GMICRO/500 microprocessor: pipeline structure of superscalar architecture","authors":"S. Matui, M. Yamamoto, I. Kawasaki, S. Narita, F. Arakawa, K. Uchiyama","doi":"10.1109/TRON.1992.313268","DOIUrl":"https://doi.org/10.1109/TRON.1992.313268","url":null,"abstract":"The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed, illustrating the effect of a pipe bypass mechanism and dedicated resident branch instruction caches. The benefit of microprogram-controlled instruction execution for high-speed execution of high-level language instructions is shown. Overall GMICRO/500 performance is evaluated in Dhrystones.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313259
C. Nishimura, N. Iwata, T. Tanaka, K. Nakayama
To examine portability in CTRON, general program management software from CTRON extended OSs was ported across various architectures. To allow portability, various modifications to the target system and to incompatible interfaces were made. The modifications requiring the most time were to the general program management software in the source system and to the load module format in the target system. There were two portings to different architectures: in the first case, porting was achieved with modification of less than 10% of the source system's code; in the second case, less than 5% modification was needed. The authors compare the two projects, and consider the results of the two porting attempts. They examine possible areas where the CTRON specifications can be enhanced to increase the portability between Extended OSs.<>
{"title":"Portability experiment for CTRON general program management","authors":"C. Nishimura, N. Iwata, T. Tanaka, K. Nakayama","doi":"10.1109/TRON.1992.313259","DOIUrl":"https://doi.org/10.1109/TRON.1992.313259","url":null,"abstract":"To examine portability in CTRON, general program management software from CTRON extended OSs was ported across various architectures. To allow portability, various modifications to the target system and to incompatible interfaces were made. The modifications requiring the most time were to the general program management software in the source system and to the load module format in the target system. There were two portings to different architectures: in the first case, porting was achieved with modification of less than 10% of the source system's code; in the second case, less than 5% modification was needed. The authors compare the two projects, and consider the results of the two porting attempts. They examine possible areas where the CTRON specifications can be enhanced to increase the portability between Extended OSs.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130900372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313257
M. Wakano, N. Sugiyama
The CTRON technical committee has planned serveral CTRON portability evaluation tests. The CTRON portability experiment step 2 concentrates on layer 3, layers 4/5, FTAM, and CMISE. The authors give an overview of FTAM and CMISE tests. The portability of FTAM and CMISE interfaces is evaluated by examining problems, time taken, and source code modification required for porting them from their original CTRON basic operating systems to another CTRON basic operating system. The results confirm that the protocol parts of FTAM and CMISE have high portability.<>
{"title":"A study on the portability of CTRON FTAM-CCL and CMISE-CCL interfaces","authors":"M. Wakano, N. Sugiyama","doi":"10.1109/TRON.1992.313257","DOIUrl":"https://doi.org/10.1109/TRON.1992.313257","url":null,"abstract":"The CTRON technical committee has planned serveral CTRON portability evaluation tests. The CTRON portability experiment step 2 concentrates on layer 3, layers 4/5, FTAM, and CMISE. The authors give an overview of FTAM and CMISE tests. The portability of FTAM and CMISE interfaces is evaluated by examining problems, time taken, and source code modification required for porting them from their original CTRON basic operating systems to another CTRON basic operating system. The results confirm that the protocol parts of FTAM and CMISE have high portability.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128665447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313266
S. Hayashida, K. Tamaru
A description is given of the optimizing methods used in the ANSI-C compiler for the chip based on the TRON architecture. This C compiler is designed for the TLCS-90000/TX series microprocessors. For the C compiler, unique optimizing methods for the TRON architecture are used in the routines for optimization of intermediate language and code generation, in addition to the traditional global optimizing methods, such as copy propagation, loop optimization and register calling convention. Thus the compiling performance was improved. The unique features of the TRON architecture are: chained addressing mode, and the ACB and SSTR instructions. Finally, the performance of the optimizing compiler is evaluated in the terms of the execution time and object code size.<>
{"title":"Optimizing method of C compiler for TRON architecture","authors":"S. Hayashida, K. Tamaru","doi":"10.1109/TRON.1992.313266","DOIUrl":"https://doi.org/10.1109/TRON.1992.313266","url":null,"abstract":"A description is given of the optimizing methods used in the ANSI-C compiler for the chip based on the TRON architecture. This C compiler is designed for the TLCS-90000/TX series microprocessors. For the C compiler, unique optimizing methods for the TRON architecture are used in the routines for optimization of intermediate language and code generation, in addition to the traditional global optimizing methods, such as copy propagation, loop optimization and register calling convention. Thus the compiling performance was improved. The unique features of the TRON architecture are: chained addressing mode, and the ACB and SSTR instructions. Finally, the performance of the optimizing compiler is evaluated in the terms of the execution time and object code size.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133582789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313261
Akio Watanabe, Hiroaki Takada, Ken Sakamura
The multi-layered design diversity (MLDD) architecture achieves fault tolerance to design faults of application programs, operatoring systems, and hardware components through applying the design diversity approach to these three system layers. The introduction of design diversity into multiple system layers improves system reliability. However, its enormous costs makes it impractical. The authors solve this problem through the fact that the TRON Project standardization approach to achieve compatibility among systems is same as that of the design diversity approach. In order for the MLDD architecture to be effective in improving system reliability, a probability of a coincident error, that is, two or more independently developed implementations failing on the same input, must be low. A low coincident error rate can be achieved by using sufficiently high quality development procedures for real-life applications and different testing methods for developing multiple implementations.<>
{"title":"The multi-layered design diversity architecture: application of the design diversity approach to multiple system layers","authors":"Akio Watanabe, Hiroaki Takada, Ken Sakamura","doi":"10.1109/TRON.1992.313261","DOIUrl":"https://doi.org/10.1109/TRON.1992.313261","url":null,"abstract":"The multi-layered design diversity (MLDD) architecture achieves fault tolerance to design faults of application programs, operatoring systems, and hardware components through applying the design diversity approach to these three system layers. The introduction of design diversity into multiple system layers improves system reliability. However, its enormous costs makes it impractical. The authors solve this problem through the fact that the TRON Project standardization approach to achieve compatibility among systems is same as that of the design diversity approach. In order for the MLDD architecture to be effective in improving system reliability, a probability of a coincident error, that is, two or more independently developed implementations failing on the same input, must be low. A low coincident error rate can be achieved by using sufficiently high quality development procedures for real-life applications and different testing methods for developing multiple implementations.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127982152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313264
H. Takada, K. Sakamura
The design policies and overviews of the extended ITRON specifications supporting distributed systems and multiprocessor systems under investigation are described. Wide applicability and high run-time performance are primary goals of these extended specifications, which are realized by inheriting the design policy of the original specification that excessive virtualization of hardware should be avoided. The authors review the design policies of the ITRON specifications, and present how the policies are incorporated in the extended specifications. The extensions expand the application areas of ITRON and make important steps towards the realization of HFDS, which is the final goal of the TRON Project.<>
{"title":"Advances in ITRON specifications-supporting multiprocessor and distributed systems","authors":"H. Takada, K. Sakamura","doi":"10.1109/TRON.1992.313264","DOIUrl":"https://doi.org/10.1109/TRON.1992.313264","url":null,"abstract":"The design policies and overviews of the extended ITRON specifications supporting distributed systems and multiprocessor systems under investigation are described. Wide applicability and high run-time performance are primary goals of these extended specifications, which are realized by inheriting the design policy of the original specification that excessive virtualization of hardware should be avoided. The authors review the design policies of the ITRON specifications, and present how the policies are incorporated in the extended specifications. The extensions expand the application areas of ITRON and make important steps towards the realization of HFDS, which is the final goal of the TRON Project.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130704228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313267
Y. Kashiwagi, Y. Tawara, H. Chaki, K. Yamada, M. Kainaga, T. Isobe
The GMICRO/500 is a superscalar microprocessor based on the TRON specification. An optimizing C compiler for the microprocessor is under development. The compiler implements both hardware-independent optimizations and GMICRO/500-specific optimizations with a performance target of 100 MIPS at 50 MHz. The hardware-independent optimizations gave a good basis for the effective improvement of hardware/software performance. On the other hand, GMICRO-specific optimizations was a challenging problem because of the complexity of the superscalar CISC architecture. The authors describe these optimization techniques with emphasis on the implementation strategy of the GMICRO/500-specific superscalar optimization.<>
{"title":"An optimizing C compiler for the GMICRO/500 microprocessor","authors":"Y. Kashiwagi, Y. Tawara, H. Chaki, K. Yamada, M. Kainaga, T. Isobe","doi":"10.1109/TRON.1992.313267","DOIUrl":"https://doi.org/10.1109/TRON.1992.313267","url":null,"abstract":"The GMICRO/500 is a superscalar microprocessor based on the TRON specification. An optimizing C compiler for the microprocessor is under development. The compiler implements both hardware-independent optimizations and GMICRO/500-specific optimizations with a performance target of 100 MIPS at 50 MHz. The hardware-independent optimizations gave a good basis for the effective improvement of hardware/software performance. On the other hand, GMICRO-specific optimizations was a challenging problem because of the complexity of the superscalar CISC architecture. The authors describe these optimization techniques with emphasis on the implementation strategy of the GMICRO/500-specific superscalar optimization.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"58 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128258615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313271
N. Koshizuka, M. Uematsu, N. Kimura, K. Skamura
EnableWare is a specification and implementation of the human-machine interface (HMI) which enables physically disabled people to access computers. The BTRON HMI specification includes the EnableWare specification in standard. This assures that physically impaired people can use BTRON with no or a little software/hardware modification. The authors first analyze the difficulties of physically impaired people to use computers. Second, they propose EnableWare functions which help motor, visually, and auditory impaired users, and the architecture realizing them. Finally, on the basis of their EnableWare implementation experience on BTRONI, they propose several architectural design guidelines for the HMI system which can be operated by the physically disabled.<>
{"title":"Design and implementation of the EnableWare specification-a human-machine interface for physically challenging people","authors":"N. Koshizuka, M. Uematsu, N. Kimura, K. Skamura","doi":"10.1109/TRON.1992.313271","DOIUrl":"https://doi.org/10.1109/TRON.1992.313271","url":null,"abstract":"EnableWare is a specification and implementation of the human-machine interface (HMI) which enables physically disabled people to access computers. The BTRON HMI specification includes the EnableWare specification in standard. This assures that physically impaired people can use BTRON with no or a little software/hardware modification. The authors first analyze the difficulties of physically impaired people to use computers. Second, they propose EnableWare functions which help motor, visually, and auditory impaired users, and the architecture realizing them. Finally, on the basis of their EnableWare implementation experience on BTRONI, they propose several architectural design guidelines for the HMI system which can be operated by the physically disabled.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123758864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313260
K. Saito
A description is given of the design principles, syntax, and semantics of the distributed real-time programming language TGHC (timed guarded Horn clauses). TGHC is a descendant of concurrent logic programming languages and it is capable of explicitly expressing time constraints by introducing the timed guard to GHC. A formal semantics of a subset of TGHC is also given.<>
{"title":"TGHC: timed guarded Horn clauses","authors":"K. Saito","doi":"10.1109/TRON.1992.313260","DOIUrl":"https://doi.org/10.1109/TRON.1992.313260","url":null,"abstract":"A description is given of the design principles, syntax, and semantics of the distributed real-time programming language TGHC (timed guarded Horn clauses). TGHC is a descendant of concurrent logic programming languages and it is capable of explicitly expressing time constraints by introducing the timed guard to GHC. A formal semantics of a subset of TGHC is also given.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126359092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-12-02DOI: 10.1109/TRON.1992.313255
T. Ozeki, T. Ogawa, T. Noda, M. Matsushita
The OKITRON series of products are microcomputer systems running a CTRON-specification operating system (OS). The latest of the series to be developed is the mid-range OKITRON-SV single-board computer system, which is reported on. OKITRON-SV is equipped with a CTRON-conformant Basic OS and Extended OS, and is intended for use as a highly functional real-time platform for communication systems. It adopts the MC68030 microprocessor in a hot-standby duplex processor configuration, and features a virtual memory system, making use of the built-in MMU (memory management unit) in the MC68030. The authors outline the hardware configuration of the system, and discuss technical issues involved in their implementation of the CTRON specifications. They further describe the system features, and the environment supporting development of application software to run on the OS.<>
{"title":"Development of a CTRON-conformant operating system on the OKITRON-SV processor system","authors":"T. Ozeki, T. Ogawa, T. Noda, M. Matsushita","doi":"10.1109/TRON.1992.313255","DOIUrl":"https://doi.org/10.1109/TRON.1992.313255","url":null,"abstract":"The OKITRON series of products are microcomputer systems running a CTRON-specification operating system (OS). The latest of the series to be developed is the mid-range OKITRON-SV single-board computer system, which is reported on. OKITRON-SV is equipped with a CTRON-conformant Basic OS and Extended OS, and is intended for use as a highly functional real-time platform for communication systems. It adopts the MC68030 microprocessor in a hot-standby duplex processor configuration, and features a virtual memory system, making use of the built-in MMU (memory management unit) in the MC68030. The authors outline the hardware configuration of the system, and discuss technical issues involved in their implementation of the CTRON specifications. They further describe the system features, and the environment supporting development of application software to run on the OS.<<ETX>>","PeriodicalId":275803,"journal":{"name":"Proceedings [1992] The Ninth TRON Project Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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