Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060540
Kunj Jain, S. Singh, A. Majumder, Abir J. Mondai
As technology scales down toward deep submicron, large numbers of IP blocks are being integrated on the same Silicon die, thereby enabling large amount of parallel computations, such as those required for multimedia workloads. Network-on-chip (NOC) serves as an important agent to eliminate the communication bottleneck of future multicore systems. Arbiter, a prime component has a great impact on the feasibility of router. In this paper, we concentrate our ideas on the basic arbitration techniques with their features and found some problems with their roles in improving the performance of the routers and finally extending our range to a novel notion of overcoming extensive problems of starvation, HOL, congestion, etc. in a novel and feasible manners with a combination of the existing arbitration techniques in a more compact and sequential form.
{"title":"Problems encountered in various arbitration techniques used in NOC router: A survey","authors":"Kunj Jain, S. Singh, A. Majumder, Abir J. Mondai","doi":"10.1109/EDCAV.2015.7060540","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060540","url":null,"abstract":"As technology scales down toward deep submicron, large numbers of IP blocks are being integrated on the same Silicon die, thereby enabling large amount of parallel computations, such as those required for multimedia workloads. Network-on-chip (NOC) serves as an important agent to eliminate the communication bottleneck of future multicore systems. Arbiter, a prime component has a great impact on the feasibility of router. In this paper, we concentrate our ideas on the basic arbitration techniques with their features and found some problems with their roles in improving the performance of the routers and finally extending our range to a novel notion of overcoming extensive problems of starvation, HOL, congestion, etc. in a novel and feasible manners with a combination of the existing arbitration techniques in a more compact and sequential form.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"54 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120995249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060549
B. Roy, A. Bhattacharya, A. Bhattacharjee, S. Chowdhury
In this paper a novel wideband spade-shaped monopole antenna with ring geometry is designed for several wideband microwave applications. The antenna is designed in CST Microwave Studio Suite™ environment. Round Slot Geometry is applied in design of the patch structure. The finalized monopole is proposed to be applicable in the microwave frequency band from 4.2 GHz to 12.2 GHz. The antenna exhibits a gain of 3.4 dBi, 3.5 dBi, 3.7 dBi, 3.8 dBi, 4.6 dBi and 1.9 dBi at frequencies 5 GHz, 5.2 GHz, 5.5 GHz and 5.8 GHz, 10 GHz and 12 GHz respectively. The antenna exhibits a wide bandwidth of 8 GHz (4.2 GHz to 12.2 GHz).
{"title":"A novel wideband spade shaped monopole antenna with ring geometry for wireless applications","authors":"B. Roy, A. Bhattacharya, A. Bhattacharjee, S. Chowdhury","doi":"10.1109/EDCAV.2015.7060549","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060549","url":null,"abstract":"In this paper a novel wideband spade-shaped monopole antenna with ring geometry is designed for several wideband microwave applications. The antenna is designed in CST Microwave Studio Suite™ environment. Round Slot Geometry is applied in design of the patch structure. The finalized monopole is proposed to be applicable in the microwave frequency band from 4.2 GHz to 12.2 GHz. The antenna exhibits a gain of 3.4 dBi, 3.5 dBi, 3.7 dBi, 3.8 dBi, 4.6 dBi and 1.9 dBi at frequencies 5 GHz, 5.2 GHz, 5.5 GHz and 5.8 GHz, 10 GHz and 12 GHz respectively. The antenna exhibits a wide bandwidth of 8 GHz (4.2 GHz to 12.2 GHz).","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121781217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060533
M. R. Bharath Kumar, C. M. Sibu
One of the technical challenges for the modern society to detect and find a solution for visually impaired, with increased security and service motto towards the society helped to bring a solution which would help the visually impaired in the industries and other companies. Here we had come out with a prototype as a way of finding a solution to the visually impaired The navigation assistant technology using RFID Tag Grid minimizes the dependency. The reader used in this system is embedded in the mobile and shoes to avoid dependency on travel The RFID reader matches with the information specified to that ID and a voice signal is generated Wireless RF links is placed in the Bluetooth device/ headphone for voice guidance The proximity sensing unit is an auxiliary unit is added as a solution to address unexpected and non-mapped obstacles in the user's path. Basically it contains ultrasonic Sensor Unit interfaced with microcontroller which is inter-linked to a vibrator that would be activated when nearing obstacles. This system is technically and economically feasible and may offer a maximum benefit to the disabled.
{"title":"Design for visually impaired to work at Industry using RFID technology","authors":"M. R. Bharath Kumar, C. M. Sibu","doi":"10.1109/EDCAV.2015.7060533","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060533","url":null,"abstract":"One of the technical challenges for the modern society to detect and find a solution for visually impaired, with increased security and service motto towards the society helped to bring a solution which would help the visually impaired in the industries and other companies. Here we had come out with a prototype as a way of finding a solution to the visually impaired The navigation assistant technology using RFID Tag Grid minimizes the dependency. The reader used in this system is embedded in the mobile and shoes to avoid dependency on travel The RFID reader matches with the information specified to that ID and a voice signal is generated Wireless RF links is placed in the Bluetooth device/ headphone for voice guidance The proximity sensing unit is an auxiliary unit is added as a solution to address unexpected and non-mapped obstacles in the user's path. Basically it contains ultrasonic Sensor Unit interfaced with microcontroller which is inter-linked to a vibrator that would be activated when nearing obstacles. This system is technically and economically feasible and may offer a maximum benefit to the disabled.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128729342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060537
Ansh, Rakesh Yadav, D. Deb, Ashok Ray
This paper proposes a unique embedded system architecture which results in a multi-purpose, auto-programmable, reconfìgurable and power efficient embedded system. The proposed architecture involves single microcontroller along with another digital system and a low cost memory chip to perform a large number of tasks, thus eliminating the use of large number of microcontrollers, by performing tasks of all these microcontrollers alone. This architecture eliminates the use of a programmer to repeatedly program the microcontroller. It re-programs itself whenever necessary, without human intervention (auto-programmable) and can be configured to perform different set of tasks just by replacing the memory chip with another one containing a different set of programs (re-configurable).
{"title":"Multi-purpose auto-programmable reconfigurable embedded system architecture","authors":"Ansh, Rakesh Yadav, D. Deb, Ashok Ray","doi":"10.1109/EDCAV.2015.7060537","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060537","url":null,"abstract":"This paper proposes a unique embedded system architecture which results in a multi-purpose, auto-programmable, reconfìgurable and power efficient embedded system. The proposed architecture involves single microcontroller along with another digital system and a low cost memory chip to perform a large number of tasks, thus eliminating the use of large number of microcontrollers, by performing tasks of all these microcontrollers alone. This architecture eliminates the use of a programmer to repeatedly program the microcontroller. It re-programs itself whenever necessary, without human intervention (auto-programmable) and can be configured to perform different set of tasks just by replacing the memory chip with another one containing a different set of programs (re-configurable).","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133920177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060528
K. Sarma, Santanu Sharma
A method for scale length determination of Gate all around (Octagonal cross section) Junctionless Transistor is reported in this paper. The scale length expression is obtained by solving the 3D Poisson's equation. Variation of scale length with gate oxide thickness, side length of octagon and dielectric constant is shown. The Transverse and central electrostatic potential profile is also shown for different values of gate oxide thickness, side length of octagon, Channel length and Drain voltage and Gate Voltage are shown. Longitudinal electric field profile for different value of drain voltage is also shown. The scale length value decreases linearly with decreasing gate oxide thickness and side length of octagon and decreases nonlinearly with increasing dielectric constant.
{"title":"Scale length determination of Gate all around (Octagonal cross section) Junctionless Transistor","authors":"K. Sarma, Santanu Sharma","doi":"10.1109/EDCAV.2015.7060528","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060528","url":null,"abstract":"A method for scale length determination of Gate all around (Octagonal cross section) Junctionless Transistor is reported in this paper. The scale length expression is obtained by solving the 3D Poisson's equation. Variation of scale length with gate oxide thickness, side length of octagon and dielectric constant is shown. The Transverse and central electrostatic potential profile is also shown for different values of gate oxide thickness, side length of octagon, Channel length and Drain voltage and Gate Voltage are shown. Longitudinal electric field profile for different value of drain voltage is also shown. The scale length value decreases linearly with decreasing gate oxide thickness and side length of octagon and decreases nonlinearly with increasing dielectric constant.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132333830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060543
A. Saha, Koj Sambyo, C. Bhunia
Power consumption of any microprocessor depends on its applied operating voltage & its applied frequency and this power consumption is proportional to V2f. Therefore, scaling of the voltage or frequency will affect the reduction of the power consumption. Again, now-a-days multi CPUs in microprocessors are available. Enabling & disabling of CPUs in a multiprocessor can also effect in reduction of the power consumption. This paper proposed a power saving algorithm of CPU frequency scaling along with enabling & disabling of number of CPUs based on its utilization or Workload. Here both frequency scaling and enabling & disabling of number of CPUs are combined together. The proposed algorithm is implemented in Linux based environment. This policy can be applied in Laptop, Desktop, small gadgets and Server etc.
{"title":"Integration of DVFS and multi CPUs scaling in a multi-processor","authors":"A. Saha, Koj Sambyo, C. Bhunia","doi":"10.1109/EDCAV.2015.7060543","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060543","url":null,"abstract":"Power consumption of any microprocessor depends on its applied operating voltage & its applied frequency and this power consumption is proportional to V2f. Therefore, scaling of the voltage or frequency will affect the reduction of the power consumption. Again, now-a-days multi CPUs in microprocessors are available. Enabling & disabling of CPUs in a multiprocessor can also effect in reduction of the power consumption. This paper proposed a power saving algorithm of CPU frequency scaling along with enabling & disabling of number of CPUs based on its utilization or Workload. Here both frequency scaling and enabling & disabling of number of CPUs are combined together. The proposed algorithm is implemented in Linux based environment. This policy can be applied in Laptop, Desktop, small gadgets and Server etc.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127074132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-16DOI: 10.1109/EDCAV.2015.7060556
B. Das, Ashim kumar Mahato, Ajoy Kumar Khan
Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.
{"title":"A novel approach for constrained via minimization problem in VLSI channel routing","authors":"B. Das, Ashim kumar Mahato, Ajoy Kumar Khan","doi":"10.1109/EDCAV.2015.7060556","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060556","url":null,"abstract":"Constrained Via Minimization is a typical problem in VLSI channel routing. The objective of via minimization is to improve the circuit performance and productivity and to reduce the completion rate of routing. In CVM problem, some vias may be non essential to the given layout. Here we have to be selected and remove from the layout. In this paper, we present a procedure to find out non essential vias. This procedure we used to solve constrained via minimization problems. Then, we show the experimental results and hardcopy solutions of some layout to prove that our approach obtains better results compared to conventional algorithms.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116735397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDCAV.2015.7060552
Subrata Das, Nikumani Choudhury, Leena Barua, Ajoy Kr Khan
Via minimization plays an increasingly important role in the routing phase in the design process of VLSI circuits and systems. A via is an electrical connection that establishes the connectivity between two layers. Vias are established at points where a net changes layer. But if the number of vias is more, then it not only reduces the reliability of the product but also causes delay and affects the circuit performance. Therefore, via minimization plays an increasingly vital role in the efficient yield of the circuit. In this paper, we devise an algorithm for reducing the number of vias by using the concepts of maximum independent set, net intersection graph and segment intersection graph. Also in this approach the number of horizontal tracks is minimized, thus minimizing the routing area.
{"title":"An algorithm for Via minimization in two layer channel routing of VLSI design","authors":"Subrata Das, Nikumani Choudhury, Leena Barua, Ajoy Kr Khan","doi":"10.1109/EDCAV.2015.7060552","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060552","url":null,"abstract":"Via minimization plays an increasingly important role in the routing phase in the design process of VLSI circuits and systems. A via is an electrical connection that establishes the connectivity between two layers. Vias are established at points where a net changes layer. But if the number of vias is more, then it not only reduces the reliability of the product but also causes delay and affects the circuit performance. Therefore, via minimization plays an increasingly vital role in the efficient yield of the circuit. In this paper, we devise an algorithm for reducing the number of vias by using the concepts of maximum independent set, net intersection graph and segment intersection graph. Also in this approach the number of horizontal tracks is minimized, thus minimizing the routing area.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122334638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDCAV.2015.7060536
R. Lorenzo, Saurabh Chaudhary
This paper presents a novel design to reduce sub threshold leakage current. The leakage controlled transistors are utilized to change dynamically the ground voltage level which is based on output voltage level of logic gate. The leakage controlled transistors (LCT's) are utilized to reduce the leakage power and static energy consumption (static power-delay product) while maintaining the performance of delay. Simulation result based on 32nm Berkeley predictive technology model shows that the proposed technique achieves better performance than conventional designs.
{"title":"Low leakage and minimum energy consumption in CMOS logic circuits","authors":"R. Lorenzo, Saurabh Chaudhary","doi":"10.1109/EDCAV.2015.7060536","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060536","url":null,"abstract":"This paper presents a novel design to reduce sub threshold leakage current. The leakage controlled transistors are utilized to change dynamically the ground voltage level which is based on output voltage level of logic gate. The leakage controlled transistors (LCT's) are utilized to reduce the leakage power and static energy consumption (static power-delay product) while maintaining the performance of delay. Simulation result based on 32nm Berkeley predictive technology model shows that the proposed technique achieves better performance than conventional designs.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116315540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDCAV.2015.7060551
Pyreddy Mary Arpita, K. Datta, R. Vemula, I. Sengupta
The paper presents an approach for optimizing a reversible netlist consisting of multiple-control Toffoli (MCT) gates with the objective of reducing quantum cost. The MCT gates are first decomposed into smaller gates with up to three control lines, and then a template matching method is applied on the netlist for optimization. The templates are constructed by considering all possible 3-gate sequences with up to four lines. This work constitutes an extension of a previous work by Dueck et al., where 2-gate sequences were considered in the templates. The input gate netlists are generated from the reversible benchmarks available in RevLib, followed by Barenco decomposition to produce Toffoli gates with at most three control connections. The proposed approach is applied on these netlists, and the final quantum cost calculated. Experimental results on standard benchmarks show that the method can lead to reductions in quantum cost.
{"title":"Optimization of reversible circuits using triple-gate templates at quantum gate level","authors":"Pyreddy Mary Arpita, K. Datta, R. Vemula, I. Sengupta","doi":"10.1109/EDCAV.2015.7060551","DOIUrl":"https://doi.org/10.1109/EDCAV.2015.7060551","url":null,"abstract":"The paper presents an approach for optimizing a reversible netlist consisting of multiple-control Toffoli (MCT) gates with the objective of reducing quantum cost. The MCT gates are first decomposed into smaller gates with up to three control lines, and then a template matching method is applied on the netlist for optimization. The templates are constructed by considering all possible 3-gate sequences with up to four lines. This work constitutes an extension of a previous work by Dueck et al., where 2-gate sequences were considered in the templates. The input gate netlists are generated from the reversible benchmarks available in RevLib, followed by Barenco decomposition to produce Toffoli gates with at most three control connections. The proposed approach is applied on these netlists, and the final quantum cost calculated. Experimental results on standard benchmarks show that the method can lead to reductions in quantum cost.","PeriodicalId":277103,"journal":{"name":"2015 International Conference on Electronic Design, Computer Networks & Automated Verification (EDCAV)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122997088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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