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2008 Asia and South Pacific Design Automation Conference最新文献

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Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm 基于门块选择算法的低功耗预计算内容可寻址存储器参数提取器的合成与设计
Pub Date : 2008-01-21 DOI: 10.5555/1356802.1356884
Jui-Yuan Hsieh, S. Ruan
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in fast search time, it also significantly increases power consumption. In this paper, we propose a gate- block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based CAM (PB-CAM) to improve the efficiency for specific applications such as embedded systems. Through experimental results, we found that our approach effectively reduces the number of comparison operations for specific data types (ranging from 19.24% to 27.42%) compared with the 1's count approach. We used Synopsys Nanosim to estimate the power consumption in TSMC 0.35 um CMOS process. Compared to the 1's count PB-CAM, our proposed PB-CAM achieves 17.72% to 21.09% in power reduction for specific data types.
内容可寻址内存(CAM)经常用于需要高速搜索的应用程序,例如查找表、数据库、关联计算和网络,因为它能够通过使用并行比较来减少搜索时间来提高应用程序性能。虽然使用并行比较可以缩短搜索时间,但也会显著增加功耗。本文提出了一种门块选择算法,该算法可以合成一个合适的基于预计算的CAM参数提取器(PB-CAM),以提高嵌入式系统等特定应用的效率。通过实验结果,我们发现与1's count方法相比,我们的方法有效地减少了特定数据类型的比较操作次数(范围从19.24%到27.42%)。我们使用Synopsys Nanosim来估算TSMC 0.35 um CMOS工艺的功耗。与1的计数PB-CAM相比,我们提出的PB-CAM在特定数据类型上实现了17.72%到21.09%的功耗降低。
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引用次数: 11
Temperature-aware MPSoC scheduling for reducing hot spots and gradients 温度感知MPSoC调度,减少热点和梯度
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484002
A. Coskun, T. Simunic, K. Whisnant, K. Gross
Thermal hot spots and temperature gradients on the die need to be minimized to manufacture reliable systems while meeting energy and performance constraints. In this work, we solve the task scheduling problem for multiprocessor system-on-chips (MPSoCs) using Integer Linear Programming (ILP). The goal of our optimization is minimizing the hot spots and balancing the temperature distribution on the die for a known set of tasks. Under the given assumptions about task characteristics, the solution is optimal. We compare our technique against optimal scheduling methods for energy minimization, energy balancing, and hot spot minimization, and show that our technique achieves significantly better thermal profiles. We also extend our technique to handle workload variations at runtime.
模具上的热热点和温度梯度需要最小化,以制造可靠的系统,同时满足能源和性能限制。在这项工作中,我们使用整数线性规划(ILP)来解决多处理器片上系统(mpsoc)的任务调度问题。我们优化的目标是最小化热点并平衡已知任务的模具温度分布。在给定的任务特征假设下,解是最优的。我们将我们的技术与能量最小化、能量平衡和热点最小化的最佳调度方法进行了比较,并表明我们的技术获得了明显更好的热剖面。我们还扩展了我们的技术来处理运行时的工作负载变化。
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引用次数: 97
Faster projection based methods for circuit level verification 基于快速投影的电路电平验证方法
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483985
Chao Yan, M. Greenstreet
As VLSI fabrication technology progresses to 65 nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits using continuous models. Recently, we showed how such verification can be performed using projection based methods.However, the verification was slow, requiring nearly four CPU days to verify a nine-transistor toggle flip-flop. Here, we describe improvements to the reachability algorithms and optimizations of the software architecture. These produce a 15 x reduction in computation time and significant reductions in the overapproximation errors. With these changes, the same toggle flip-flop can be verified in a few hours, making formal verification a viable alternative to circuit simulation.
随着VLSI制造技术发展到65nm及更小的特征尺寸,晶体管不再是理想的开关。这激发了使用连续模型验证数字电路的动机。最近,我们展示了如何使用基于投影的方法来执行这样的验证。然而,验证是缓慢的,需要近4个CPU天来验证一个9晶体管的开关触发器。在这里,我们描述了可达性算法的改进和软件架构的优化。这使计算时间减少了15倍,并大大减少了过度近似误差。通过这些更改,可以在几个小时内验证相同的开关触发器,使正式验证成为电路仿真的可行替代方案。
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引用次数: 13
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis 一种利用行为综合中专门功能单元的高效绩效改进方法
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483969
Tsuyoshi Sadakata, Y. Matsunaga
This paper proposes a novel behavioral synthesis method that improves performance of synthesized circuits utilizing specialized functional units effectively. Specialized functional units (e.g. multiply-accumulator) are designed for specific operation patterns to achieve shorter delay and/or smaller area than cascaded basic functional units. Almost all conventional methods cannot use specialized functional units effectively under a total area constraint because of their less flexibility for resource sharing. The proposed method makes it possible to solve module selection, scheduling, and functional unit allocation problems utilizing specialized functional units in practical time with some heuristics, and to reduce the number of clock cycles under total area and clock cycle time constraints. Experimental results show that the proposed method has achieved up to 35% and on average 14% reduction of the number of cycles with specialized functional units in practical time.
本文提出了一种新的行为合成方法,有效地提高了利用专门功能单元的合成电路的性能。专门的功能单元(如乘法累加器)是为特定的操作模式而设计的,以实现比级联基本功能单元更短的延迟和/或更小的面积。在总面积约束下,由于资源共享的灵活性较差,几乎所有传统方法都不能有效地利用专业化功能单元。该方法利用启发式方法在实际时间内利用专门的功能单元解决模块选择、调度和功能单元分配问题,并在总面积和时钟周期时间限制下减少时钟周期数。实验结果表明,该方法在实际时间内可将专用功能单元的循环次数减少35%,平均减少14%。
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引用次数: 2
Distribution arithmetic for stochastical analysis 随机分析的分布算法
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484009
M. Olbrich, E. Barke
This paper presents a novel arithmetic which allows calculations with fluctuating values. The arithmetic consists of a special representation of random variables and procedures for performing numerical operations between them. Given the distributions of initial random variables, the moments (such as expected value, variance and higher moments) of any calculated variable can be determined. Our approach is not limited to normal distributions and works with linear and nonlinear functions. Correlations between variables are taken into account automatically by the arithmetic. Examples show the accuracy and runtimes compared to Monte Carlo simulation.
本文提出了一种新的算法,允许计算波动值。该算法由随机变量的特殊表示和在随机变量之间执行数值运算的程序组成。给定初始随机变量的分布,可以确定任何计算变量的矩(如期望值、方差和更高矩)。我们的方法不仅限于正态分布,而且适用于线性和非线性函数。算法自动考虑变量之间的相关性。示例显示了与蒙特卡罗模拟相比的准确性和运行时间。
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引用次数: 5
Load scheduling: Reducing pressure on distributed register files for free 负载调度:免费减少分布式寄存器文件的压力
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483971
M. Wen, N. Wu, Maolin Guan, Chunyuan Zhang
In this paper we describe load scheduling, a novel method that balances load among register files by residual resources. Load scheduling can reduce register pressure for clustered VLIW processors with distributed register files while not increasing VLIW scheduling length. We have implemented load scheduling in compiler for Imagine and FT64 stream processors. The result shows that the proposed technique effectively reduces the number of variables spilled to memory, and can even eliminate it. The algorithm presented in this paper is extremely efficient in embedded processor with limited register resource because it can improve registers utilization instead of increasing the requirement for the number of registers.
负载调度是一种利用剩余资源平衡寄存器文件负载的新方法。负载调度可以减少具有分布式寄存器文件的集群VLIW处理器的寄存器压力,同时不会增加VLIW调度长度。我们在编译器中实现了Imagine和FT64流处理器的负载调度。结果表明,该方法有效地减少了溢出到内存中的变量数量,甚至可以消除溢出到内存中的变量数量。本文提出的算法在寄存器资源有限的嵌入式处理器中是非常高效的,因为它可以提高寄存器的利用率,而不是增加对寄存器数量的要求。
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引用次数: 3
Design rule optimization of regular layout for leakage reduction in nanoscale design 纳米尺度设计中减少泄漏的规则布局设计规则优化
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483997
Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao
The effect of non-rectilinear gate (NRG) due to sub-wavelength lithograph dramatically increases the leakage current by more than 15X. To mitigate this penalty, we have developed a systematic procedure to optimize key layout parameters in regular layout with minimum area and speed overhead. As demonstrated in 65 nm technology, the optimization of regular layout achieves more than 70% reduction in leakage under NRG, with area penalty of ~10% and marginal impact on circuit speed and active power.
亚波长光刻引起的非直线栅(NRG)效应使漏电流显著增加15倍以上。为了减轻这种损失,我们开发了一个系统的程序,以最小的面积和速度开销来优化常规布局中的关键布局参数。在65纳米技术中,优化规则布局可以使NRG下的泄漏减少70%以上,面积损失约为10%,对电路速度和有功功率的影响很小。
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引用次数: 25
Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization 基于进化蚁群优化的粗粒度可重构系统协同软硬件划分
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484037
Dawei Wang, Sikun Li, Y. Dou
The flexibility, performance and cost effectiveness of reconfigurable architectures have lead to its widespread use for embedded applications. Coarse-grained reconfigurable system design is very complex for multi-fields experts to collaborate on application algorithm design, hardware/software co-design and system decision. However, existing reconfigurable system design methods and environments can only support hardware/software co-design, ignoring the collaboration between multi-field experts. This paper presents a collaborative partition approach of coarse-grained reconfigurable system design using evolutionary ant colony optimization. We create a distributed collaborative design environment for system decision engineers, software designers, hardware designers and application algorithm developers. The method not only utilizes the advantages of ant colony optimization for searching global optimal solutions, but also provides a framework for multi-field experts to work collaboratively. Experimental results show that the method improves the quality and speed of hardware/software partition for coarse-grained reconfigurable system design.
可重构架构的灵活性、性能和成本效益使其在嵌入式应用中得到广泛应用。粗粒度可重构系统设计非常复杂,需要多领域专家在应用算法设计、软硬件协同设计和系统决策等方面进行协作。然而,现有的可重构系统设计方法和环境只能支持硬件/软件协同设计,忽略了多领域专家之间的协作。提出了一种基于进化蚁群优化的粗粒度可重构系统设计协同划分方法。我们为系统决策工程师、软件设计人员、硬件设计人员和应用算法开发人员创建了一个分布式协作设计环境。该方法不仅利用蚁群算法在全局最优解搜索中的优势,而且为多领域专家协同工作提供了一个框架。实验结果表明,该方法提高了粗粒度可重构系统设计的硬件/软件划分质量和速度。
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引用次数: 9
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults 一种既能诊断扫描链故障又能诊断组合电路故障的诊断设计技术
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484017
Fei Wang, Yu Hu, Huawei Li, Xiaowei Li
The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.
扫描链和扫描控制电路所消耗的模具面积可达15%~30%,扫描链故障几乎占芯片故障的50%。由于常规诊断过程通常运行在故障的空闲扫描链上,扫描链故障可能导致诊断过程中断,导致故障区域较大,需要进行耗时的故障分析。本文提出了一种诊断设计(DFD)技术,可以精确、高效地诊断故障扫描链,并利用该技术对故障扫描链进行常规的逻辑诊断。所提出的方法与传统的基于扫描的设计完全兼容。以前提出的基于软件的传统扫描设计诊断方法仍然可以应用于我们的设计。在ISCAS’89基准电路上进行了实验,验证了DFD技术的有效性。
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引用次数: 8
Analytical model for the impact of multiple input switching noise on timing 多输入开关噪声对时序影响的分析模型
Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484005
Rajeshwary Tayade, S. Nassif, J. Abraham
The timing models used in current Static Timing Analysis tools use gate delays only for single input switching events. It is well known that the temporal proximity of signals arriving at different inputs causes significant variation in the gate delay. This variation in delay affects the accuracy of our timing estimates. In this paper, we derive simple analytical models for incorporating the effect of simultaneous multiple input switching events on gate delay. The model presented requires minimum additional characterization effort, and can be employed in a statistical timing engine. The dynamic delay variability of a path caused by MIS noise can be accurately estimated using the proposed model.
当前静态时序分析工具中使用的时序模型仅对单输入开关事件使用门延迟。众所周知,到达不同输入端的信号的时间接近性会导致门延迟的显著变化。这种延迟的变化影响了我们时间估计的准确性。在本文中,我们推导了一个简单的分析模型来考虑同时多输入开关事件对门延迟的影响。提出的模型需要最小的额外表征工作,并且可以在统计定时引擎中使用。利用该模型可以准确地估计由MIS噪声引起的路径动态延迟变化。
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引用次数: 8
期刊
2008 Asia and South Pacific Design Automation Conference
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